64M-Bit (4Mx16) CMOS MASK Switchable organization 4,194,304 16(wo
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K3N7V(U)4000B-DC
64M-Bit (4Mx16) CMOS MASK
Switchable organization 4,194,304 16(word mode) Fast access time 3.3V Operation 100ns(Max.)@CL=50pF, 120ns(Max.)@C L=100pF 3.0V Operation 120ns(Max.)@CL=100pF Supply voltage single +3.3V/ single +3.0V Current consumption Operating 40mA(Max.) Fully static operation inputs outputs compatible Three state outputs Package K3N7V(U)4000B-DC: 42-DIP-600
CMOS MASK
GENERAL DESCRIPTION
K3N7V(U)4000B-DC fully static mask programmable organized 4,194,304x16 bit. fabricated using silicongate CMOS process technology. This device operates with 3.0V 3.3V power supply, inputs outputs compatible. Because asynchronous operation, requires external clock assuring extremely easy operation. suitable program memory microprocessor, data memory, character generator. K3N7V(U)4000B-DC packaged 42-DIP
FUNCTIONAL BLOCK DIAGRAM
CONFIGURATION
BUFFERS DECODER
MEMORY CELL MATRIX (4,194,304x16)
BUFFERS DECODER
SENSE AMP. BUFFERS
CONTROL LOGIC
Name
Function Address Inputs Data Outputs Output Enable Power Ground
K3N7V(U)4000B-DC
K3N7V(U)4000B-DC
ABSOLUTE MAXIMUM RATINGS
Item Voltage Relative Temperature Under Bias Storage Temperature Symbol TBIAS TSTG Rating
CMOS MASK
Unit
-0.3 +4.5 +150
NOTE Permanent device damage occur "ABSOLUTE MAXIMUM RATINGS" exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference VSS, TA=0 70°C)
Item Supply Voltage Supply Voltage Symbol 2.7/3.0 3.0/3.3 3.3/3.6 Unit
CHARACTERISTICS
Parameter Operating Current Input Leakage Current Output Leakage Current Input High Voltage, Inputs Input Voltage, Inputs Output High Voltage Level Output Voltage Level Symbol IOH=-400µA IOL=2.1mA Test Conditions Cycle=5MHZ, outputs open, OE=VIL, VIN=0.45V 2.4V Test Condition) VIN=0 VOUT=0 VCC=3.3V±0.3V VCC=3.0V±0.3V -0.3 VCC+0.3 Unit
NOTE Minimum Voltage(VIL) -0.3V input pins. During transitions, this level undershoot -2.0V periods <20ns. Maximum voltage input pins(VIH VCC+0.3V which, during transitions, overshoot VCC+2.0V periods <20ns.
MODE SELECTION
Mode Operating Operating Data High-Z Q0~Q15 Dout Power Active Active
CAPACITANCE(TA=25°C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol COUT Test Conditions VOUT=0V VIN=0V Unit
NOTE Capacitance periodically sampled 100% tested.
K3N7V(U)4000B-DC
TEST CONDITIONS
Item Input Pulse Levels Input Rise Fall Times Input Output timing Levels Output Loads Value
CMOS MASK
CHARACTERISTICS(TA=0°C +70°C, VCC=3.3V/3.0V±0.3V, unless otherwise noted.)
0.45V 2.4V 10ns 1.5V Gate CL=50pF 100pF
READ CYCLE
Item Read Cycle Time Address Access Time Output Enable Access Time Output Chip Disable Output High-Z Output Hold from Address Change Symbol K3N7V4000B-DC10 (CL=50pF) K3N7V4000B-DC12 (CL=100pF) K3N7U4000B-DC12 (CL=100pF) Unit
TIMING DIAGRAM
READ
A0~A21
ADD1
ADD2
tDF(*1) DOUT D0~D15 VALID DATA VALID DATA
NOTES defined time which outputs achieve open circuit condition referenced level.
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