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Stratix Device Family Overview
SIII51001-1.1
Stratix® family provides most architecturally advanced, high performance, power FPGAs market place. Stratix FPGAs lower power consumption through Altera's innovative Programmable Power Technology, which provides ability turn performance where needed turn down power consumption everywhere else. Selectable Core Voltage latest silicon process optimizations also employed deliver industry's lowest power, high performance FPGAs. Specifically designed ease rapid system integration, Stratix FPGA family offers three family variants optimized meet different application needs:
Stratix family provides balanced logic, memory, multiplier ratios mainstream applications. Stratix family memory multiplier rich data-centric applications. Stratix family contains embedded high-speed serial transceivers extensive internal memory high bandwidth applications.
Modular banks with common bank structure vertical migration lend efficiency flexibility high speed I/O. Package enhancements with dynamic on-chip termination, output delay current strength control provide best-in-class signal integrity. Based 1.1-V, 65-nm all-layer copper SRAM process, Stratix family programmable alternative custom ASICs programmable processors high performance logic, digital signal processing (DSP), embedded designs architects. Stratix devices include optional configuration stream security through volatile non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability required, Stratix devices include automatic error detection circuitry detect data corruption soft errors configuration random-access memory (CRAM) user memory cells.
Altera Corporation 2007
Features
Stratix devices offer following features:
48,000 338,000 equivalent logic elements (LEs), Table 2,430 20,497 Kbits enhanced TriMatrix memory consisting three block sizes implement true dual-port memory first-in first-out (FIFO) buffers High-speed blocks provide dedicated implementation multipliers MHz), multiplyaccumulate functions, finite impulse response (FIR) filters I/O:GND:PWR ratio 8:1:1 along with on-die on-package decoupling robust signal integrity Programmable Power Technology, which minimizes power while maximizing device performance Selectable Core Voltage, available low-voltage devices ordering code suffix), enables selection lowest power highest performance operation global clocks, regional clocks peripheral clocks device phase-locked loops (PLLs) device that support reconfiguration, clock switchover, programmable bandwidth, clock synthesis dynamic phase shifting Memory interface support with dedicated logic banks Support high-speed external memory interfaces including DDR,DDR2,DDR3 SDRAM, RLDRAM SRAM modular banks 1,104 user pins arranged modular banks that support wide range industry standards Dynamic On-Chip Termination (OCT) with auto calibration support banks High-speed differential support with serializer/deserializer (SERDES) dynamic phase alignment (DPA) circuitry 1.25 Gbps performance Support high-speed networking communications standards including SPI-4.2, SFI-4, SGMII, Utopia Gigabit Ethernet XSLI, Rapid NPSI only high-density, high-performance FPGA with support 256-bit (AES) volatile non-volatile security protect designs Robust on-chip socketing power sequencing support Integrated cyclical redundancy check (CRC) configuration memory error detection with critical error determination high availability systems support Built-in error correction coding (ECC) circuitry detect correct configuration user memory error events
Stratix Device Handbook, Volume
Altera Corporation 2007
Stratix Device Family Overview
Nios embedded processor support Support multiple intellectual property megafunctions from Altera® MegaCore® functions Altera Megafunction Partners Program (AMPP)
Table lists Stratix FPGA family features.
Table 1-1. Stratix FPGA Family Features
Device/ Feature Stratix Logic Family
EP3SL50 EP3SL70 EP3SL110 EP3SL150 EP3SL200 EP3SE260 EP3SL340
ALMs
102K 135K 102K
47.5K 67.5K 107.5K 142.5K 200K 255K 337.5K 47.5K 107.5K 255K
blocks
1,040
M144K blocks
MLAB Blocks
1,350 2,150 2,850 4,000 5,100 6,750 1,600 2,150 5,100
Total Total MLAB Memory multipliers PLLs Embedded Kbits (FIR Mode) Kbits Kbits
1,836 2,214 4,203 5,499 7,668 14,688 16,272 5,328 6,183 8,055 14,688 1,344 1,781 2,500 3,188 4,219 1,000 1,344 3,188 2,430 3,058 5,547 7,280 10,168 17,876 20,491 5,922 7,183 9,399 17,876
Stratix Enhanced Family
EP3SE50 EP3SE80 EP3SE110 EP3SE260
Note Table 1-1:
EP3SE260 device rich memory, multiplier resources. Hence, aligns with both logic enhanced variants.
Stratix logic family offers balanced logic, memory, multipliers address wide range applications, while enhanced family offers more memory multipliers logic ideal wireless, medical imaging, military applications. Stratix devices available space-saving FineLine packages (see Table Table 1-3).
Altera Corporation 2007
Stratix Device Handbook, Volume
Table lists Stratix FPGA package options counts.
Table 1-2. Package Options Counts Note Device
EP3SL50 EP3SL70 EP3SL110 EP3SL150 EP3SL200 EP3SL340 EP3SE50 EP3SE80 EP3SE110 EP3SE260 Note Table 1-2:
arrows indicate vertical migration. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p CLK10n) that used data inputs. counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, CLK10n) eight dedicated corner clock inputs (PLL_L1_CLKp, PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp, PLL_R1_CLKn) that used data inputs. Bank available EP3SL200 F1517 FPGA.
484-Pin FineLine
780-Pin FineLine
1152-Pin FineLine
1,517-Pin FineLine
1,760-Pin FineLine
1,120
Stratix devices support vertical migration within same package (for example, migrate between EP3SL50 EP3SL70 devices 780-pin FineLine package). Vertical migration allows migrate devices whose dedicated pins, configuration pins, power pins same given package across device densities. ensure that board layout supports migratable densities within package offering, enable applicable vertical migration path within Quartus® software (Assignments menu Device Migration Devices). migrate from family family without increasing number available. This minimizes cost vertical migration.
Stratix Device Handbook, Volume
Altera Corporation 2007
Stratix Device Family Overview
Table lists Stratix FBGA package sizes.
Table 1-3. FineLine Package Sizes Dimension
Pitch (mm) Area (mm2) Length/Width (mm/
1.00 23/23
1.00 29/29
1152
1.00 1,225 35/35
1,517
1.00 1,600 40/40
1760
1.00 1,849 43/43
Stratix devices available three speed grades, with being fastest. Stratix devices offered both commercial industrial temperature range ratings with leaded lead-free packages. Selectable Core Voltage available specially marked lowvoltage devices ordering code suffix).
Architecture Features
following section briefly describes various features Stratix family FPGAs.
Logic Array Blocks Adaptive Logic Modules
Logic Array Block (LAB) composed basic building blocks known Adaptive Logic Modules (ALMs) that configured implement logic, arithmetic, register functions. Each consists ALMs, carry chains, shared arithmetic chains, control signals, local interconnect, register chain connection lines. ALMs part unique, innovative logic structure that delivers faster performance, minimizes area, reduces power consumption. ALMs expand traditional 4-input look-up table architecture inputs, increasing performance reducing LEs, logic levels, associated routing. addition, ALMs maximize performance with dedicated functionality efficiently implement adder trees other complex arithmetic functions. Quartus Compiler places associated logic adjacent LABs, allowing local, shared arithmetic chain, register chain connections performance area efficiency. Logic Array Block (LAB) Stratix-III derivative called Memory MLAB), which adds SRAM memory capability LAB. MLAB superset includes features. MLABs support maximum 640-bits simple dual-port Static Random Access Memory (SRAM). Each MLAB configured either block, resulting configuration simple dual port SRAM block. MLAB blocks always co-exist pairs Stratix-III families allowing logic (LABs) traded memory (MLABs).
Altera Corporation 2007
Stratix Device Handbook, Volume
Architecture Features
more information LABs ALMs, refer Logic Array Blocks Adaptive Logic Modules Stratix Devices chapter volume Stratix Device Handbook. more information MLAB modes, features design considerations, refer TriMatrix Embedded Memory Blocks Stratix Devices chapter volume Stratix Device Handbook.
MultiTrack Interconnect
Stratix architecture, connections between ALMs, TriMatrix memory, blocks, device pins provided MultiTrack interconnect structure with DirectDrive technology. MultiTrack interconnect consists continuous, performance-optimized column interconnects that span fixed distances. routing structure with fixed length resources devices allows predictable repeatable performance when migrating through different device densities. MultiTrack interconnect provides 1-hop connection adjacent LABs, 2-hop connections adjacent LABs connections adjacent LABs. DirectDrive technology deterministic routing technology that ensures identical routing resource usage function regardless placement device. MultiTrack interconnect DirectDrive technology simplify integration stage block-based designing eliminating reoptimization cycles that typically follow design changes additions. Quartus Compiler also automatically places critical design paths faster interconnects improve design performance.
more information, refer MultiTrack Interconnect Stratix Devices chapter Stratix Device Handbook, Volume
TriMatrix Embedded Memory Blocks
TriMatrix embedded memory blocks provide three different sizes embedded SRAM efficiently address needs Stratix FPGA designs. TriMatrix memory includes following blocks:
640-bit MLAB blocks optimized implement filter delay lines, small FIFO buffers shift registers 9-Kbit blocks that used general purpose memory applications 144-Kbit M144K blocks that ideal processor code storage, packet video frame buffering
Stratix Device Handbook, Volume
Altera Corporation 2007
Stratix Device Family Overview
Each embedded memory block independently configured single- dual-port RAM, ROM, shift register Quartus MegaWizard. Multiple blocks same type also stitched together produce larger memories with minimal timing penalty. TriMatrix memory provides 16,272 Kbits embedded SRAM operation.
more information TriMatrix memory blocks, modes, features, design considerations, refer TriMatrix Embedded Memory Blocks Stratix Devices chapter volume Stratix Device Handbook.
Blocks
Stratix devices have dedicated high-performance digital signal processing (DSP) blocks optimized applications requiring high data throughput. Stratix devices provide with ability implement various high performance functions easily. Complex systems such WiMAX, 3GPP WCDMA, CDMA2000, voice over Internet protocol (VoIP), H.264 video compression high-definition television (HDTV) require high performance blocks process data. These system designs typically blocks implement finite impulse response (FIR) filters, complex filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, discrete cosine transform (DCT) functions. Stratix devices have blocks. architectural highlights Stratix block following:
High performance, power optimized, fully pipelined multiplication operations Native support 9-bit, 12-bit, 18-bit, 36-bit word lengths Native support 18-bit complex multiplications Efficient support floating point arithmetic formats (24-bit Single Precision 53-bit Double Precision) Signed unsigned input support Built-in addition, subtraction, accumulation units efficiently combine multiplication results Cascading 18-bit input form tap-delay lines Cascading 44-bit output propagate output results from block next block Rich flexible arithmetic rounding saturation units Efficient barrel shifter support Loopback capability support adaptive filtering
block multipliers optionally feed adder/subtractor accumulator block depending user configuration. This option saves routing resources increases performance, because
Altera Corporation 2007
Stratix Device Handbook, Volume
Architecture Features
connections blocks inside block. Additionally, Block input registers efficiently implement shift registers filter applications, Stratix blocks support rounding saturation. Quartus software includes megafunctions that control mode operation blocks based user parameter settings.
more information, refer Blocks Stratix Devices chapter volume Stratix Device Handbook.
Clock Networks PLLs
Stratix devices provide dedicated Global Clock Networks (GCLKs), Regional Clock Networks (RCLKs), Periphery Clock Networks (PCLKs). These clocks organized into hierarchical clock structure that provides unique clock domains GCLK RCLK) within Stratix device allows GCLK RCLK) unique GCLK/RCLK clock sources device quadrant. Stratix delivers abundant resources with PLLs device outputs PLL. Every output independently programmed creating unique, customizable clock frequency with fixed relation other input output clock. Inherent jitter filtration fine granularity control over multiply, divide ratios dynamic phase-shift reconfiguration provide high-performance precision required today's high-speed applications. Stratix device PLLs feature rich, supporting advanced capabilities such clock switchover, reconfigurable phase shift, reconfiguration, reconfigurable bandwidth. PLLs used general-purpose clock management supporting multiplication, phase shifting, programmable duty cycle. Stratix PLLs also support external feedback mode, spread-spectrum input clock tracking post-scale counter cascading.
more information, refer Clock Networks PLLs Stratix Devices chapter volume Stratix Device Handbook.
Banks Structure
Stratix devices contain modular banks, each which contains I/Os. This modular bank structure improves efficiency eases device migration. left right side banks contain circuitry support external memory interfaces speeds high-speed differential interfaces meeting 1.25 Gbps performance. bottom banks contain circuitry support external memory interfaces speeds MHz, high-speed differential inputs outputs running speeds respectively.
Stratix Device Handbook, Volume
Altera Corporation 2007
Stratix Device Family Overview
Stratix devices support wide range industry standards, including single-ended, voltage referenced single-ended, differential standards. Stratix supports programmable hold, programmable pull-up resistor, programmable slew rate, programmable output delay control, open-drain output. Stratix devices also support on-chip series (RS) on-chip parallel (RT) termination with auto calibration single-ended standards on-chip differential termination (RD) LVDS standards Left/Right banks. Dynamic also supported bi-directional pins banks.
more information, refer Stratix Device Features chapter volume Stratix Device Handbook.
External Memory Interfaces
Stratix structure been completely redesigned from ground provide flexibility enable high-performance support existing emerging external memory standards such DDR, DDR2, DDR3, QDRII, QDRII+ RLDRAMII frequencies MHz. Packed with features such dynamic on-chip termination, trace mismatch compensation, read/write levelling, half-rate registers, 36-bit programmable group widths, Stratix I/O's supply built functionality required rapid robust implementation external memory interfaces. Double data-rate support found sides Stratix device. Stratix devices provide efficient architecture quickly easily wide external memory interfaces exactly where want them. self-calibrating soft core (ALTMEMPHY) optimized take advantage Stratix device along with Quartus timing analysis tool (TimeQuest) provide total solution highest reliable frequency operation across process voltage temperature.
more information external memory interfaces, refer External Memory Interfaces Stratix Devices chapter volume Stratix Device Handbook.
Altera Corporation 2007
Stratix Device Handbook, Volume
Architecture Features
High Speed Differential Interfaces with
Stratix devices contain dedicated circuitry supporting differential standards speeds 1.25 Gbps. high-speed differential circuitry supports following high speed interconnect standards applications: Utopia SPI-4.2, SFI-4, Gigabit Ethernet XSLI, Rapid I/O, NPSI. Stratix devices support SERDES modes high speed differential interfaces SERDES modes when using dedicated circuitry. minimizes errors, simplifies layout timing management high-speed data transfer, eliminates channel-to-channel channelto-clock skew high-speed data transmission systems. Soft also implemented, enabling low-cost 1.25-Gbps clock embedded serial links. Stratix devices have following dedicated circuitry high-speed differential support:
Differential buffer Transmitter serializer Receiver deserializer Data realignment Dynamic phase aligner (DPA) Soft functionality Synchronizer (FIFO buffer) PLLs
more information, refer High Speed Differential Interfaces with Stratix Devices chapter volume Stratix Device Handbook.
Socketing Power-On Reset
Stratix devices hot-socketing compliant. socketing also known plug-in swap, power sequencing support without external devices. Robust on-chip hot-socketing power-sequencing support ensures proper device operation independent power-up sequence. insert remove Stratix board system during system operation without causing undesirable effects running system board that inserted into system. hot-socketing feature also makes easier Stratix devices printed circuit boards (PCBs) that also contain mixture 3.0-V, 2.5-V, 1.8-V, 1.5-V 1.2-V devices. With Stratix socketing feature, longer need ensure proper power-up sequence each device board.
1-10 Stratix Device Handbook, Volume
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Stratix Device Family Overview
more information, refer Socketing Power-On Reset Stratix Devices chapter volume Stratix Device Handbook.
Configuration
Stratix devices configured using following four configuration schemes:
Fast passive parallel (FPP) Fast active serial (AS) Passive serial (PS) Joint Test Action Group (JTAG)
configuration schemes either external controller (for example, MAX® device microprocessor), configuration device, download cable. Stratix devices support configuration data decompression, which saves configuration memory space time. This feature allows store compressed configuration data configuration devices other memory transmit this compressed bitstream Stratix devices. During configuration, Stratix device decompresses bitstream real time programs SRAM cells. Stratix devices support decompression when using device/microprocessor flash, fast configuration schemes. Stratix decompression feature available when using enhanced configuration device JTAG configuration schemes.
more information, refer Configuring Stratix Devices chapter volume Stratix Device Handbook.
Remote System Upgrades
Stratix devices feature remote system upgrade capability, allowing error-free deployment system upgrades from remote location securely reliably. Soft logic (either Nios embedded processor user logic) implemented Stratix device download configuration image from remote location, store configuration memory, direct dedicated remote system upgrade circuitry initiate reconfiguration cycle. dedicated circuitry performs error detection during after configuration process, recover from error condition reverting back safe configuration image, provides error status information. This dedicated remote system upgrade circuitry unique Stratix series FPGAs helps avoid system downtime.
Altera Corporation 2007
1-11 Stratix Device Handbook, Volume
Architecture Features
more information refer Remote System Upgrades with Stratix Devices chapter volume Stratix Device Handbook.
IEEE 1149.1 (JTAG) Boundary Scan Testing
Stratix devices support JTAG IEEE Std. 1149.1 specification. Boundary-Scan Test (BST) architecture offers capability test connections without using physical test probes capture functional data while device operating normally. Boundary-scan cells Stratix device force signals onto pins capture data from logic array signals. Forced test data serially shifted into boundaryscan cells. Captured data serially shifted externally compared expected results. addition BST, IEEE Std. 1149.1 controller Stratix device in-circuit reconfiguration (ICR).
more information refer IEEE 1149.1 (JTAG) Boundary Scan Testing Stratix Devices chapter volume Stratix Device Handbook.
Design Security
Stratix devices only high-density, high-performance FPGAs with support 256-bit volatile non-volatile security keys protect designs against copying, reverse engineering, tampering. Stratix devices have ability decrypt configuration bitstream using Advanced Encryption Standard (AES) algorithm, industry standard encryption algorithm that FIPS-197 certified requires 256-bit security key. design security feature available when configuring Stratix FPGAs using fast passive parallel (FPP) configuration mode with external host (such device microprocessor), when using fast active serial (AS) passive serial (PS) configuration schemes.
more information design security feature, refer Design Security Stratix Devices chapter volume Stratix Device Handbook.
Mitigation
Stratix devices have built-in error detection circuitry detect data corruption soft errors configuration random-access memory (CRAM) cells. This feature allows CRAM contents read verified continuously during user mode operation match configuration-computed value. enhanced circuit frame-based configuration architecture allows detection location multiple, single, adjacent errors which, conjunction with soft
1-12 Stratix Device Handbook, Volume Altera Corporation 2007
Stratix Device Family Overview
circuit supplied reference design, allows don't-care soft errors CRAM ignored during device operation. This provides step decrease effective soft error rate, increasing system reliability. On-chip memory block mitigation also offered using configurable Megafunction Quartus MLAB blocks while M144K memory blocks have built-in error correction code (ECC) circuitry.
more information dedicated error detection circuitry, refer Mitigation Stratix Devices chapter volume Stratix Device Handbook.
Programmable Power
Stratix delivers Programmable Power, only FPGA with user programmable power options balancing today's power performance requirements. Stratix devices utilize most advanced power saving techniques including variety process, circuit, architecture optimizations innovations. addition, user controllable power reduction techniques provide optimal balance performance power reduction specific each design configured into Stratix FPGA. Quartus software (starting from Version 6.1) automatically optimizes designs meet performance goals while simultaneously leveraging programmable power saving options available Stratix FPGA without need changes design flow.
more information Programmable Power Stratix devices, refer following documents:
Programmable Power Temperature Sensing Diode Stratix Devices chapter Stratix Device Handbook, Volume Power Optimization Stratix Devices Application Note Stratix Power White Paper
Signal Integrity
Stratix devices simplify challenge signal integrity through number chip, package, board level enhancements enable efficient high speed data transfer into device. These enhancements include:
8:1:1 user I/O/Gnd/Vcc ratio reduce loop inductance package Dedicated power supply each bank, limit I/Os I/Os bank, help limit simultaneous switching noise
Altera Corporation 2007
1-13 Stratix Device Handbook, Volume
Reference Ordering Information
Programmable slew-rate support with settings match desired standard, control noise, overshoot Programmable output-current drive strength support with settings match desired standard performance Programmable output-delay support control rise/fall times adjust duty cycle, compensate skew reduce simultaneous switching outputs (SSO) noise Dynamic with auto calibration support series parallel differential support LVDS standard left/right banks
more information support Quartus refer Quartus Handbook. following section describes Stratix device software support ordering information.
Reference Ordering Information
Software
Stratix devices supported Altera Quartus design software, version 6.1, which provides comprehensive environment system-on-a-programmable-chip (SOPC) design. Quartus software includes schematic design entry, compilation logic synthesis, full simulation advanced timing analysis, SignalTap® logic analyzer, device configuration. Quartus Handbook more information Quartus software features. Quartus software supports Windows XP/2000/NT/98, Solaris, Linux v7.1 HP-UX operating systems. also supports seamless integration with industry-leading tools through NativeLink® interface.
1-14 Stratix Device Handbook, Volume
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Stratix Device Family Overview
Ordering Information
Figure describes ordering codes Stratix devices. more information specific package, refer Package Information Stratix Devices chapter Stratix Device Handbook. Figure 1-1. Stratix Device Packaging Ordering Information
EP3SL Family Signature EP3SL: Stratix Logic EP3SE: Stratix DSP/Memory EP3SGX: Stratix Transceiver Device Type Speed Grade Package Type FineLine (FBGA) Count Number pins particular package: 1152 1517 1760 with being fastest 1152 Optional Suffix Indicates specific device options Engineering sample Lead-free devices Low-voltage devices
Operating Temperature Commercial temperature Industrial temperature
Altera Corporation 2007
1-15 Stratix Device Handbook, Volume
Document Revision History
Document Revision History
Table shows revision history this document.
Table 1-4. Document Revision History Date Document Version
2007
Changes Made
Minor formatting changes, fixed numbers ALM, MLAB counts Table 1-1.
Summary Changes
November 2006 Initial Release v1.0
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Altera Corporation 2007
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