HCPL-314J Features Minimum Peak Output Current High Speed Respons

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HCPL-314J Features Minimum Peak Output Current High Speed Respons

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Output Current IGBT Gate Drive Optocoupler Technical Data
HCPL-314J Features
Minimum Peak Output Current High Speed Response: Max. Propagation Delay over Temp. Range Ultra High CMR: Min. kV/µs Bootstrappable Supply Current: Max. Wide Operating Temp. Range: -40°C 100°C Wide Operating Range: over Temp. Range Available DIP8 (Single) SO16 (Dual) Package Safety Approvals: Recognized, 3750 Vrms Minute. Approval Pending. Approval Pending VIORM=891 peak
Functional Diagram Description
HCPL-314J family devices consists AlGaAs optically coupled integrated circuit with power output stage. These optocouplers ideally suited driving power IGBTs MOSFETs used motor control inverter applications. high operating voltage range output stage provides drive voltages required gate controlled devices. voltage current supplied this optocoupler makes ideally suited directly driving small medium power IGBTs. IGBTs with higher ratings HCPL-3150(0.5A) HCPL-3120 (2.0A) optocouplers used.
ANODE CATHODE
SHIELD
ANODE CATHODE
SHIELD
HCPL-314J
Truth Table
HIGH
Applications
Isolated IGBT/Power MOSFET Gate Drive Brushless Motor Drives Inverters Appliances Industrial Inverters Switch Mode Power Supplies (SMPS) Uninterruptable Power Supplies (UPS)
bypass capacitor must connected between pins CAUTION: advised that normal static precautions taken handling assembly this component prevent damage and/or degradation which induced ESD.
Selection Guide
Package Type SO16 Part Number HCPL-314J Number Channels
Ordering Information
Specify part number followed option number desired Example
HCPL-314J#YYY option SO16 Package. Tape Reel Packaging Option.
Package Outline Drawing
HCPL-314J SO16 Package:
VIEW
GND1
VCC1
8.76 0.20 (0.345 0.008)
GND2
7.49 0.10 (0.295 0.004)
HCPL-314J
VIN1
VIN2
VCC2
0.10 0.30 (0.004 0.0118) STANDOFF
8.76 0.20 (0.345 0.008)
VIEW FROM 0.64 (0.025 MIN.) VIEW FROM 3.51 0.13 (0.138 0.005)
0.23 (0.0091) 10.36 0.20 (0.408 0.008)
1.27 0.457 (0.050) (0.018) 0.016 0.0003 (0.406 0.007)
LEADS COPLANAR 0.05 (0.002 INCHES) DIMENSIONS MILLIMETERS (INCHES).
Solder Reflow Temperature Profile
100°C, 1.5°C/SEC 145°C, 1°C/SEC 115°C, 0.3°C/SEC
Regulatory Information
HCPL-314J pending approval following organizations: Approval under 0884/06.92 with VIORM Vpeak expected prior product release. Approval under 1577, component recognition program VISO 3750 Vrms expected prior product release. File E55361. Approved under Component Acceptance Notice File 88324 expected prior product release.
TEMPERATURE
TIME MINUTES (NOTE: NON-CHLORINE ACTIVATED FLUXES RECOMMENDED.)
0884 Insulation Characteristics
Description Installation classification 0110/1.89, Table rated mains voltage Vrms rated mains voltage Vrms rated mains voltage Vrms Climatic Classification Pollution Degree (DIN 0110/1.89) Maximum Working Insulation Voltage Input Output Test Voltage, Method VIORM 1.875=V 100% Production Test with tm=1 sec, Partial discharge Input Output Test Voltage, Method VIORM 1.5=VPR, Type Sample Test, tm=60 sec, Partial discharge Highest Allowable Overvoltage (Transient Overvoltage tini sec) Safety-limiting values maximum values allowed event failure. Case Temperature Input Current** Output Power** Insulation Resistance VIORM Symbol Characteristic I-II 55/100/21 1670 Vpeak Vpeak Unit
IO
1336 6000
Vpeak Vpeak
IS,INPUT OUTPUT
1200 >109
Refer optocoupler section Isolation Control Components Designer's Catalog, under Product Safety Regulations section, (VDE 0884) detailed description Method Method partial discharge test profiles. Refer following figure dependence ambient temperature.
OUTPUT POWER INPUT CURRENT
(mW) (mA)
CASE TEMPERATURE
Insulation Safety Related Specifications
Parameter Minimum External (Clearance) Minimum External Tracking (Creepage) Minimum Internal Plastic (Internal Clearance) Symbol L(101) HCPL-314J Units Conditions Measured from input terminals output terminals, shortest distance through air. Measured from input terminals output terminals, shortest distance path along body. Through insulation distance conductor conductor, usually straight line distance thickness between emitter detector. 112/VDE 0303 Part Material Group (DIN 0110, 1/89, Table
L(102)
Tracking Resistance (Comparative Tracking Index) Isolation Group
>175 IIIa
Absolute Maximum Ratings
Parameter Storage Temperature Operating Temperature Average Input Current Peak Transient Input Current pulse width, 300pps) Reverse Input Voltage "High" Peak Output Current "Low" Peak Output Current Supply Voltage Output Voltage Output Power Dissipation Input Power Dissipation Lead Solder Temperature Solder Reflow Temperature Profile Symbol IF(AVG) IF(TRAN) IOH(PEAK) IOL(PEAK) VCC-VEE VO(PEAK) -0.5 -0.5 Min. Max. Units Note
260°C sec., below seating plane Package Outline Drawings section
Recommended Operating Conditions
Parameter Power Supply Input Current (ON) Input Voltage (OFF) Operating Temperature Symbol -VEE IF(ON) VF(OFF) Min. -3.0 Max. Units Note
Electrical Specifications (DC)
Over recommended operating conditions unless otherwise specified. Parameter High Level Output Current Level Output Current High Level Output Voltage Level Output Voltage High Level Supply Current Level Supply Current Threshold Input Current High Threshold Input Voltage High Input Forward Voltage Temperature Coefficient Input Forward Voltage Input Reverse Breakdown Voltage Input Capacitance Symbol ICCH ICCL IFLH VFHL VF/TA Min. VCC-4 Typ. VCC-1.8 Max. Units -1.2 mV/°C Test Conditions VCC- CC-10 EE+2.5 EE+10 -100 Vo>5 Fig. 9,15 Note
MHz,
Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified. Parameter Propagation Delay Time High Output Level Propagation Delay Time Output Level Propagation Delay Difference Between Parts Channels Rise Time Fall Time Output High Level Common Mode Transient Immunity Output Level Common Mode Transient Immunity Symbol tPLH tPHL Min. -0.5 Typ. Max. Units Test Conditions kHz, Duty Cycle 50%, Fig. Note 10,11, 12,13, 14,17
|CMH| |CML|
kV/µs kV/µs
25°C,
Package Characteristics
each channel unless otherwise specified. Parameter Input-Output Momentary Withstand Voltage Output-Output Momentary Withstand Voltage Input-Output Resistance Input-Output Capacitance Symbol VISO VO-O RI-O CI-O Min. 3750 1500 1012 Typ. Max. Units Vrms Vrms Test Conditions TA=25°C, RH<50% min. VI-O=500 Freq=1 Fig. Note
Notes: Derate linearly above 70°C free temperature rate mA/°C. Maximum pulse width maximum duty cycle 0.2%. This value intended allow component tolerances designs with peak minimum Application section additional details limiting peak. Derate linearly above 85°C, free temperature rate mW/°C. Input power dissipation does require derating. Maximum pulse width maximum duty cycle 0.5%. this test, measured with load current. When driving capacitive load will approach approaches zero amps. Maximum pulse width maximum duty cycle 20%. accordance with 1577, each HCPL-314J optocoupler proof tested applying insulation test voltage 5000 Vrms second (leakage detection current limit II-O µA). This test performed before 100% production test partial discharge (method shown 0884 Insulation Characteristics Table, applicable. Device considered two-terminal device: pins input side shorted together pins output side shorted together. difference between tPHL tPLH between parts channels under same test conditions. Pins (HCPL-314J) need connected common. Common mode transient immunity high state maximum tolerable |dVcm/dt| common mode pulse assure that output will remain high state (i.e. Common mode transient immunity state maximum tolerable |dVCM/dt| common mode pulse, assure that output will remain state (i.e. This load condition approximates gate load 1200 V/25 IGBT. each channel. power supply current increases when operating frequency driven IGBT increases. Device considered terminal device: Channel output side pins shorted together, channel output side pins shorted together.
(VOH-VCC) HIGH OUTPUT VOLTAGE DROP
OUTPUT HIGH CURRENT
0.40
(VOH-VCC) OUTPUT HIGH VOLTAGE DROP
-0.5
0.38
-1.0
0.36
-1.5
0.34
-2.0
0.32
-2.5
0.30
TEMPERATURE
TEMPERATURE
OUTPUT HIGH CURRENT
Figure Temperature.
Figure Temperature.
Figure
0.44
OUTPUT VOLTAGE
0.470 0.465 0.460 0.455 0.450 0.445 0.440
OUTPUT VOLTAGE
OUTPUT CURRENT
0.43
0.42
0.41
0.40
0.39
OUTPUT CURRENT
TEMPERATURE
TEMPERATURE
Figure Temperature.
Figure Temperature.
Figure
SUPPLY CURRENT
IFLH HIGH CURRENT THRESHOLD
ICCL ICCH
SUPPLY CURRENT
ICCL ICCH
TEMPERATURE
SUPPLY VOLTAGE
TEMPERATURE
Figure Temperature.
Figure
Figure Temperature.
PROPAGATION DELAY
PROPAGATION DELAY
PROPAGATION DELAY
TPLH TPHL
TPLH TPHL
SUPPLY VOLTAGE
FORWARD CURRENT
TEMPERATURE
Figure Propagation Delay VCC.
Figure Propagation Delay
Figure Propagation Delay Temperature.
PROPAGATION DELAY
PROPAGATION DELAY
OUTPUT VOLTAGE
TPLH TPHL
TPLH TPHL
SERIES LOAD RESISTANCE
LOAD CAPACITANCE
FORWARD CURRENT
Figure Propagation Delay
Figure Propagation Delay
Figure Transfer Characteristics.
FORWARD CURRENT
FORWARD VOLTAGE
Figure Input Current Forward Voltage.
DUTY CYCLE
VOUT tPLH tPHL
Figure Propagation Delay Test Circuit Waveforms.
SWITCH SWITCH 1500
Figure Test Circuit Waveforms.
Applications Information
Eliminating Negative IGBT Gate Drive keep IGBT firmly off, HCPL-314J very maximum specification Minimizing lead inductance from HCPL-314J IGBT gate emitter (possibly mounting HCPL-314J small board
directly above IGBT) eliminate need negative IGBT gate drive many applications shown Figure Care should taken with such board design avoid routing IGBT collector emitter traces close HCPL-314J input this result unwanted coupling transient signals into input
HCPL-314J degrade performance. IGBT drain must routed near HCPL-314J input, then should reverse biased when state, prevent transient signals coupled from IGBT drain from turning HCPL-314J.)
CONTROL INPUT 74XX OPEN COLLECTOR
HCPL-314J
FLOATING SUPPLY
HVDC
3-PHASE
CONTROL INPUT 74XX OPEN COLLECTOR
HVDC
Figure Recommended Drive Application Circuit HCPL-314J.
ENERGY SWITCHING CYCLE
Selecting Gate Resistor (Rg) Step Calculate minimum from peak specification. IGBT Figure analyzed simple circuit with voltage supplied HCPL-314J. OLPEAK 0.6A
value previous equation peak current 0.6A. (See Figure Step Check HCPL-314J power dissipation increase necessary. HCPL-314J total power dissipation (PT) equal emitter power (PE) output power (PO). Duty Cycle PO(BIAS) PO(SWITCHING) (ICCBIAS KICC (Rg,Qg) where KICC increase switching constant 0.001 mA/(nC*kHz). circuit Figure with (worst case) Duty Cycle 80%, TAMAX 85°C: (0.001 mA/(nC kHz)) (PO(MAX) 85°C) value previous equation max. over entire operating temperature range. Since this case less than PO(MAX), alright power dissipation.
GATE RESISTANCE
Figure Energy Dissipated HCPL-314J Each IGBT Switching Cycle.
Drive Circuit Considerations Ultra High Performance Without detector shield, dominant cause optocoupler failure capacitive coupling from input side optocoupler, through package, detector shown Figure HCPL-314J improves performance using detector with optically transparent Faraday shield, which diverts capacitively coupled current away from sensitive circuitry. However, this shield does eliminate capacitive coupling between optocoupler pins shown Figure This capacitive coupling causes perturbations current during common mode transients becomes major source failures shielded optocoupler. main design objective high drive circuit becomes keeping proper state during common mode transients. example, recommended application circuit (Figure 19), achieve kV/µs while minimizing component complexity. Techniques keep proper state discussed next sections.
CLEDP
CLEDO1 CLEDP
CLEDO2
CLEDN
CLEDN
SHIELD
Figure Optocoupler Input Output Capacitance Model Unshielded Optocouplers.
Figure Optocoupler Input Output Capacitance Model Shielded Optocouplers.
CLEDP
ILEDP
VSAT
CLEDN
SHIELD
ARROWS INDICATE DIRECTION CURRENT FLOW DURING -dVCM/dt.
Figure Equivalent Circuit Figure During Common Mode Transient.
CLEDP
CLEDP
CLEDN ILEDN
CLEDN
SHIELD
SHIELD
Figure Recommended Open Collector Drive Circuit.
Figure Recommended Drive Circuit Ultra-High Dead Time Propagation Delay Specifications.
with (CMRH) high drive circuit must keep during common mode transients. This achieved overdriving current beyond input threshold that pulled below threshold during transient. minimum current provides adequate margin over maximum IFLH achieve kV/µs CMR. with (CMRL) high drive circuit must keep VF(OFF)) during common mode transients. example, during -dVCM/dt transient Figure current flowing through CLEDP also flows through RSAT VSAT logic gate. long state voltage developed across logic gate less than VF(OFF) will remain common mode failure will occur. open collector drive circuit, shown Figure keep during +dVCM transient, since current flowing through CLEDN must supplied LED,
recommended applications requiring ultra high CMR1 performance. alternative drive circuit which like recommended application circuit (Figure 19), does achieve ultra high performance shunting state. Dead Time Propagation Delay Specifications HCPL-314J includes Propagation Delay Difference (PDD) specification intended help designers minimize "dead time" their power inverter designs. Dead time time high side power transistors off. overlap conduction will result large currents flowing through power devices from high-voltage lowvoltage motor rails. minimize dead time given design, turn LED2 should delayed (relative turn LED1) that under worstcase conditions, transistor just turned when transistor turns shown Figure amount delay necessary achieve this condition equal
maximum value propagation delay difference specification, max, which specified over operating temperature range -40° 100°C. Delaying signal maximum propagation delay difference ensures that minimum dead time zero, does tell designer what maximum dead time will maximum dead time equivalent difference between maximum minimum propagation delay difference specification shown Figure maximum dead time HCPL-314J (-0.5 µs)) over operating temperature range -40°C 100°C. Note that propagation delays used calculate dead time taken equal temperatures test conditions since optocouplers under consideration typically mounted close proximity each other switching identical IGBTs.
ILED1
VOUT1
VOUT2 ILED2
tPHL tPLH PDD* (tPHL- tPLH)MAX tPHL tPLH
*PDD PROPAGATION DELAY DIFFERENCE NOTE: CALCULATIONS PROPAGATION DELAYS TAKEN SAME TEMPERATURE TEST CONDITIONS.
Figure Minimum Skew Zero Dead Time.
ILED1
VOUT1
VOUT2
ILED2 tPHL tPHL tPLH
tPLH (tPHL-tPLH) PDD* MAXIMUM DEAD TIME (DUE OPTOCOUPLER) (tPHL tPHL MIN) (tPLH tPLH MIN) (tPHL tPLH MIN) (tPHL tPLH MAX) PDD* PDD* *PDD PROPAGATION DELAY DIFFERENCE NOTE: DEAD TIME CALCULATIONS PROPAGATION DELAYS TAKEN SAME TEMPERATURE TEST CONDITIONS.
Figure Waveforms Dead Time.
www.semiconductor.agilent.com Data subject change. Copyright 1999 Agilent Technologies 5968-2361E (11/99)

HCPL-314J Features Minimum Peak Output Current High Speed Respons

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