250MHz Video Buffer HA-5033 unity gain monolithic designed applic
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HA-5033
250MHz Video Buffer
HA-5033 unity gain monolithic designed application requiring fast, wideband buffer. Featuring bandwidth 250MHz outstanding differential phase/ gain characteristics, this high performance voltage follower excellent choice video circuit design. Other features, which include minimum slew rate 1000V/µs high output drive capability, make HA-5033 applicable line driver high speed data conversion circuits. high performance this product result Intersil Dielectric Isolation process. major feature this process that produces both high frequency transistors which makes wide bandwidth designs, such HA-5033, practical. Alternative process methods typically produce lower performance.
Features
Differential Phase Error 0.02 Degrees Differential Gain Error. 0.03% High Slew Rate. 1100V/µs Wide Bandwidth (Small Signal) 250MHz Wide Power Bandwidth 17.5MHz Fast Rise Time High Output Drive. ±10V With Load Wide Power Supply Range. ±16V Replace Costly Hybrids
Applications
Video Buffer High Frequency Buffer
Ordering Information
PART NUMBER (BRAND) HA2-5033-2 HA2-5033-5 HA3-5033-5 HA4P5033-5 HA9P5033-5 (H50335) TEMP. RANGE (oC) (Note PACKAGE Metal Metal PDIP PLCC PSOP PKG. T12.C T12.C E8.3 N20.35 M8.15A
Isolation Buffer High Speed Line Driver Impedance Matching Current Boosters High Speed Input Buffers Related Literature AN548, Designer's Guide HA-5033
Pinouts
HA-5033 (PDIP, PSOP) VIEW
HA-5033 (PLCC) VIEW
HA-5033 (METAL CAN) VIEW
CASE
SUBSTRATE
SUBSTRATE
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Copyright Intersil Corporation 1999
HA-5033
Absolute Maximum Ratings
Voltage Between Pins Input Voltage VOutput Current (Peak) (50ms On/1 Second Off) ±200mA Rating Human Body Model (Per MIL-STD-883 Method 3015.7) 2000V
Thermal Information
Thermal Resistance (Typical, Note (oC/W) (oC/W) Metal Package PDIP Package PSOP Package (Note PLCC Package. Maximum Junction Temperature (Note .175oC Maximum Junction Temperature (Plastic Packages) .150oC Maximum Storage Temperature Range -65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (PSOP PLCC Lead Tips Only)
Operating Conditions
Temperature Ranges HA-5033-2 -55oC 125oC HA-5033-5 (Note 75oC HA9P5033-5 (Notes -40oC 60oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: Maximum power dissipation, including load conditions, must designed maintain maximum junction temperature below 175oC metal package, below 150oC plastic packages (See Figure 5.). measured with component mounted evaluation board free air. Maximum operating temperature PSOP package limited 60oC, VSUPPLY ±12V prevent junction temperature from exceeding 150oC. maximum operating temperature have derated further, depending output load condition. operating temperature increased HA9P5033 operated lower VSUPPLY. example, quiescent operating temperature increased 75oC operating VSUPPLY ±9.7V. Figure more information. Direct attach PSOP copper slug copper area reduce value <100oC/W. Consult Intersil Application Group more information.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS Offset Voltage
VSUPPLY ±12V, 100, 10pF, Unless Otherwise Specified TEST CONDITIONS TEMP. (oC) HA-5033-2 HA-5033-5 UNITS
Full
µV/oC µVP-P
Average Offset Voltage Drift Bias Current
Full Full
Input Resistance Input Capacitance Input Noise Voltage TRANSFER CHARACTERISTICS Voltage Gain -3dB Bandwidth OUTPUT CHARACTERISTICS Output Voltage Swing ±15V Output Current Output Resistance Full Power Bandwidth Full Power Bandwidth (Note TRANSIENT RESPONSE Rise Time Propagation Delay Overshoot Slew Rate (Note VOUT 500mV VOUT 1VRMS 10Hz 100MHz
Full
0.93 0.93 0.92 15.9
0.99 ±100 17.5
0.93 0.93 0.92 15.9
0.99 ±100 17.5
Full Full
V/ns
HA-5033
Electrical Specifications
PARAMETER Settling Time 0.1% Differential Phase Error (Note Differential Gain Error (Note POWER SUPPLY CHARACTERISTICS Supply Current Full Power Supply Rejection Ratio Harmonic Distortion 1VRMS 100kHz Full <0.1 <0.1 VSUPPLY ±12V, 100, 10pF, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP. (oC) HA-5033-2 0.02 0.03 HA-5033-5 0.02 0.03 UNITS Degree
NOTES: VSUPPLY ±15V, VOUT ±10V, Differential gain phase error nonlinear signal distortions found video systems defined follows: Differential gain error defined change amplitude color subcarrier frequency picture signal varied from blanking white level. Differential phase error defined change phase color subcarrier picture signal varied from blanking white level. 300.
Test Circuits Waveforms
+15V 0.1µF +12V 0.1µF
0.1µF -15V
0.1µF -12V
FIGURE SLEW RATE SETTLING TIME
INPUT
FIGURE TRANSIENT RESPONSE
500mV INPUT
OVERSHOOT SLEW RATE SETTLING TIME ERROR BAND ±10mV FROM FINAL VALUE OUTPUT
OUTPUT
NOTE: Measured both positive negative transitions.
FIGURE SETTLING TIME SLEW RATE
FIGURE RISE TIME OVERSHOOT
VOUT
VOUT
25oC, +10V RESPONSE
25oC, +10V RESPONSE
HA-5033 Test Circuits Waveforms
500mV
(Continued)
500mV VOUT
25oC, PULSE RESPONSE
Schematic Diagram
VOUT
Application Information
Layout Considerations
wide bandwidth HA-5033 necessitates that high frequency circuit layout procedures followed. Failure follow these guidelines result marginal performance. Probably most crucial RF/video layout rules ground plane. ground plane provides isolation minimizes distributed circuit capacitance inductance which will degrade high frequency performance. This ground plane shielding also incorporate metal case HA-5033 since internally tied package. This feature allows user make metal metal contact between ground plane package, which extends shielding, provides additional heat sinking eliminates socket, sockets contribute inter-lead capacitance which limits device bandwidth should avoided. PDIP tied either supply, grounded, simply used. optimize device performance improve isolation, recommended that this grounded. Other considerations proper power supply bypassing keeping input output connections short possible which minimizes distributed capacitance reduces board space.
Power Supply Decoupling
optimum device performance, recommended that positive negative power supplies bypassed with capacitors ground. Ceramic capacitors ranging value from 0.01µF 0.1µF will minimize high frequency variations supply voltage. Solid tantalum capacitors larger will optimize frequency performance.
HA-5033
MAXIMUM TOTAL POWER DISSIPATION
also recommended that bypass capacitors connected close HA-5033 (preferably directly supply pins).
Figure based JMAX DMAX Where: TJMAX Maximum Junction Temperature Device Ambient Temperature Junction Ambient Thermal Resistance
TEMPERATURE (oC) QUIESCENT 0.72W ±12V, 30mA PSOP PDIP PLCC
FIGURE MAXIMUM POWER DISSIPATION TEMPERATURE
Typical Applications
(Also Application Note AN548)
HA-2539 VIDEO SIGNAL INPUT VIDEO OUTPUT
+12V 0.1µF
HA-5033
V900
0.1µF -12V
FIGURE VIDEO COAXIAL LINE DRIVER SYSTEM
FIGURE VIDEO GAIN BLOCK
VOUT VOUT
25oC, POSITIVE PULSE RESPONSE
25oC, NEGATIVE PULSE RESPONSE
HA-5033 Typical Performance Curves
OFFSET VOLTAGE (mV) ±10V ±12V ±15V ±10V
INPUT BIAS CURRENT (µA)
±12V ±15V
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE INPUT OFFSET VOLTAGE TEMPERATURE
FIGURE INPUT BIAS CURRENT TEMPERATURE
±15V SUPPLY CURRENT (mA) SLEW RATE (V/µs)
3000
±15V, ±10V
FALL 2000 FALL 100)
±12V ±10V
1000 RISE RISE 100)
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE SUPPLY CURRENT TEMPERATURE
FIGURE SLEW RATE TEMPERATURE
2400 2200 ±15V, 25oC, ±10V 2000 1800 SLEW RATE (V/µs) 1600 1400 1200 1000 1000 5000 10,000 RISE FALL SLEW RATE (V/µs)
1400 1300 1200 1100 1000
±15V, 25oC, ±10V
FALL
RISE
1000
5000
10,000
CAPACITANCE (pF)
CAPACITANCE (pF)
FIGURE SLEW RATE LOAD CAPACITANCE
FIGURE SLEW RATE LOAD CAPACITANCE
HA-5033 Typical Performance Curves
OUTPUT INPUT (mV) OUTPUT INPUT (mV) ±15V, 25oC
(Continued)
-100 -300 -500 -700 -900 INPUT VOLTAGE
±15V, 25oC
INPUT VOLTAGE
FIGURE GAIN ERROR INPUT VOLTAGE
FIGURE GAIN ERROR INPUT VOLTAGE
±15V, ±10V OUTPUT INPUT (mV) VOUT (mV) ±15, 25oC TEMPERATURE (oC) IOUT (mA) VOUT SOURCING CURRENT VOUT SINKING CURRENT VOUT VOUT
FIGURE GAIN ERROR TEMPERATURE
FIGURE VOUT IOUT
PHASE ANGLE (DEGREES) -135 -180
Y21, 10-1 MAGNITUDE 10-2
10-3
10-4
10-5
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE PARAMETERS PHASE FREQUENCY
FIGURE PARAMETER MAGNITUDE FREQUENCY
HA-5033 Typical Performance Curves
POWER SUPPLY REJECTION RATIO (dB)
(Continued)
0.10 TOTAL HARMONIC DISTORTION 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 FREQUENCY (Hz) 100K ±12V, 1VRMS
±12V, 25oC
100K FREQUENCY (Hz)
FIGURE POWER SUPPLY REJECTION RATIO FREQUENCY
TOTAL HARMONIC DISTORTION ±12V ±12V, 100kHz
FIGURE TOTAL HARMONIC DISTORTION FREQUENCY
25oC ±10V LOAD RESISTANCE
PEAK PEAK OUTPUT VOLTAGE
±15V ±12V
0.01
INPUT VOLTAGE (RMS)
FIGURE TOTAL HARMONIC DISTORTION INPUT VOLTAGE
OUTPUT VOLTAGE (VRMS) 100K FREQUENCY (Hz) 100M HEAT SINK FREE ±15V,
FIGURE OUTPUT VOLTAGE SWING LOAD RESISTANCE
OUTPUT VOLTAGE (VRMS) 100K FREQUENCY (Hz) 100M HEAT SINK FREE ±15V,
FIGURE OUTPUT SWING FREQUENCY (NOTE)
FIGURE OUTPUT SWING FREQUENCY (NOTE)
NOTE: This curve obtained noting output voltage necessary produce observable distortion given frequency. higher distortion acceptable, then higher output voltage given frequency obtained. However, operating HA-5033 with increased distortion right curve shown), will also accompanied increase supply current. resulting increase chip temperature must considered heat sinking will necessary prevent thermal runaway. This characteristic result output transistor operation. signal amplitude signal frequency both increased beyond curve shown, NPN, output transistors will approach condition being simultaneously Under this condition, thermal runaway occur.
HA-5033 Characteristics
DIMENSIONS: mils mils mils 1300µm 1700µm 483µm METALLIZATION: Type: Thickness: PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2 Phos.) Silox Thickness: Nitride Thickness: SUBSTRATE POTENTIAL (Powered Up): Unbiased TRANSISTOR COUNT: PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5033
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil semiconductor products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries. information regarding Intersil Corporation products, site http://www.intersil.com
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