110MHz, High Slew Rate, High Output Current Buffer HA-5002 monoli

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110MHz, High Slew Rate, High Output Current Buffer HA-5002 monoli

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HA-5002
110MHz, High Slew Rate, High Output Current Buffer
HA-5002 monolithic, wideband, high slew rate, high output current, buffer amplifier. Utilizing advantages Intersil D.I. technologies, HA-5002 current buffer offers 1300V/µs slew rate with 110MHz bandwidth. ±200mA output current capability enhanced output impedance. monolithic HA-5002 will replace hybrid LH0002 with corresponding performance increases. These characteristics range from 3000k input impedance increased output voltage swing. Monolithic design technologies have allowed more precise buffer developed with more than order magnitude smaller gain error. HA-5002 will provide many present hybrid users with higher degree reliability same time increase overall circuit performance. military grade product, refer HA-5002/883 datasheet, AnswerFAX document #3705.
Features
Voltage Gain 0.995 High Input Impedance 3000k Output Impedance Very High Slew Rate 1300V/µs Very Wide Bandwidth 110MHz High Output Current ±200mA Pulsed Output Current 400mA Monolithic Construction
Applications
Line Driver Data Acquisition 110MHz Buffer Radar Cable Driver High Power Current Booster High Power Current Source Sample Holds Video Products
Ordering Information
PART NUMBER (BRAND) HA2-5002-2 HA2-5002-5 HA3-5002-5 HA4P5002-5 HA7-5002-2 HA7-5002-5 HA9P5002-5 (H50025) HA9P5002-9 (H50029) TEMP. RANGE (oC) PACKAGE Metal Metal PDIP PLCC CERDIP CERDIP SOIC SOIC PKG. T8.C T8.C E8.3 N20.35 F8.3A F8.3A M8.15 M8.15
Pinouts
HA-5002 (PDIP, CERDIP, SOIC) VIEW HA-5002 (PLCC) VIEW
HA-5002 (METAL CAN) VIEW
V2NC
V1V2-
V113
NOTE: Case Voltage Floating
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 321-724-7143 Copyright Intersil Corporation 1999
HA-5002
Absolute Maximum Ratings
Voltage Between Terminals. Input Voltage V1Output Current (Continuous) ±200mA Output Current (50ms Off) ±400mA
Thermal Information
Thermal Resistance (Typical, Note (oC/W)JC (oC/W) CERDIP Package. PDIP Package Metal Package PLCC Package. SOIC Package Junction Temperature (Hermetic Packages, Note 175oC Junction Temperature (Plastic Packages, Note 150oC Storage Temperature Range -65oC 150oC Lead Temperature (Soldering 10s) 300oC (PLCC SOIC Lead Tips Only)
Operating Conditions
Temperature Range HA-5002-2 -55oC 125oC HA-5002-5 75oC HA-5002-9 -40oC 85oC
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTES: Maximum power dissipation, including load conditions, must designed maintain maximum junction temperature below 175oC ceramic packages, below 150oC plastic packages. measured with component mounted evaluation board free air.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS Offset Voltage
VSUPPLY ±12V ±15V, 10pF, Unless Otherwise Specified TEST CONDITIONS TEMP (oC) HA-5002-2 HA-5002-5, UNITS
Full
µV/C µVP-P A/mA
Average Offset Voltage Drift Bias Current
Full Full
Input Resistance Input Noise Voltage TRANSFER CHARACTERISTICS Voltage Gain (VOUT ±10V) -3dB Bandwidth Current Gain OUTPUT CHARACTERISTICS Output Voltage Swing ±15V ±12V Output Current Output Resistance Harmonic Distortion TRANSIENT RESPONSE Full Power Bandwidth (Note Rise Time Propagation Delay Overshoot Slew Rate Settling Time Differential Gain Differential Phase 0.1% 1VRMS, 10kHz ±10V, 1VP-P 10Hz-1MHz
Full
Full
0.980
0.900 0.971 0.995 ±10.7 ±13.5 ±10.5 <0.005
0.980
0.900 0.971 0.995 ±11.2 ±13.9 ±10.5 <0.005
Full Full Full
20.7 0.06 0.22
20.7 0.06 0.22
V/ns Degrees
HA-5002
Electrical Specifications
PARAMETER POWER REQUIREMENTS Supply Current Full Power Supply Rejection Ratio NOTE: Slew Rate Full VSUPPLY ±12V ±15V, 10pF, Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) HA-5002-2 HA-5002-5, UNITS
Test Circuit Waveforms
+15V V1-15V V2OUT
FIGURE LARGE SMALL SIGNAL RESPONSE
VOUT
VOUT
SMALL SIGNAL WAVEFORMS
SMALL SIGNAL WAVEFORMS
VOUT
VOUT
LARGE SIGNAL WAVEFORMS
LARGE SIGNAL WAVEFORMS
HA-5002 Schematic Diagram
V1R2 V2Q2
Application Information
Layout Considerations
wide bandwidth HA-5002 necessitates that high frequency circuit layout procedures followed. Failure follow these guidelines result marginal performance. Probably most crucial RF/video layout rules ground plane. ground plane provides isolation minimizes distributed circuit capacitance inductance which will degrade high frequency performance. Other considerations proper power supply bypassing keeping input output connections short possible which minimizes distributed capacitance reduces board space.
Short Circuit Protection
output current limited using following circuit:
OUTMAX OUTMAX
IOUTMAX 200mA (CONTINUOUS) RLIM V2RLIM
Power Supply Decoupling
optimal device performance, recommended that positive negative power supplies bypassed with capacitors ground. Ceramic capacitors ranging value from 0.01 0.1µF will minimize high frequency variations supply voltage, while frequency bypassing requires larger valued capacitors since impedance capacitor dependent frequency. also recommended that bypass capacitors connected close HA-5002 (preferably directly supply pins).
Capacitive Loading
HA-5002 will drive large capacitive loads without oscillation peak current limits should exceeded. Following formula Cdv/dt implies that slew rate capacitive load must controlled keep peak current below maximum current limiting approach shown. HA-5002 become unstable with small capacitive loads (50pF) certain precautions taken. Stability enhanced following: source resistance series with input increasing capacitive load 150pF greater; decreasing CLOAD 20pF less; adding output resistor adding feedback capacitance 50pF greater. Adding source resistance generally yields best results.
Operation Reduced Supply Levels
HA-5002 operate supply voltage levels lower. Output swing directly affected well slight reductions slew rate bandwidth.
HA-5002
MAXIMUM POWER DISSIPATION TEMPERATURE (oC) QUIESCENT POWER DISSIPATION ±15V SUPPLIES SOIC PDIP
PLCC
JMAX DMAX Where: TJMAX Maximum Junction Temperature Device Ambient
CERDIP
Junction Case Thermal Resistance Case Heat Sink Thermal Resistance Heat Sink Ambient Thermal Resistance Graph based JMAX DMAX
FIGURE MAXIMUM POWER DISSIPATION TEMPERATURE
Typical Application
+12V V1-12V VOUT V2V2+ VOUT
FIGURE COAXIAL CABLE DRIVER SYSTEM
Typical Performance Curves
VOLTAGE GAIN (dB) GAIN PHASE FREQUENCY (MHz) PHASE SHIFT 135o 180o ±15V, VOLTAGE GAIN (dB) PHASE FREQUENCY (MHz) 135o 180o PHASE SHIFT GAIN ±15V,
FIGURE GAIN/PHASE FREQUENCY
FIGURE GAIN/PHASE FREQUENCY
HA-5002 Typical Performance Curves
0.994 0.992 0.990 VOLTAGE GAIN (V/V) VOLTAGE GAIN (V/V) 0.988 0.986 0.984 0.982 0.980 0.978 0.976 0.974 TEMPERATURE (oC) 0.991 VOUT -10V +10V 0.996 0.995 0.994 0.993 0.992 VOUT -10V VOUT +10V ±15V 0.997
(Continued)
0.998 ±15V
TEMPERATURE (oC)
FIGURE VOLTAGE GAIN TEMPERATURE 100)
FIGURE VOLTAGE GAIN TEMPERATURE
±15V BIAS CURRENT (µA) TEMPERATURE (oC) TEMPERATURE (oC) ±15V
OFFSET VOLTAGE (mV)
FIGURE OFFSET VOLTAGE TEMPERATURE
FIGURE BIAS CURRENT TEMPERATURE
±15V, RLOAD SUPPLY CURRENT (mA)
±15V, IOUT
OUTPUT VOLTAGE
+VOUT
-VOUT
TEMPERATURE (oC)
TEMPERATURE (oC)
FIGURE MAXIMUM OUTPUT VOLTAGE TEMPERATURE
FIGURE SUPPLY CURRENT TEMPERATURE
HA-5002 Typical Performance Curves
IOUT 125oC, 25oC SUPPLY CURRENT (mA) IMPEDANCE -55oC 100K
(Continued)
±15V
1000
SUPPLY VOLTAGE (±V) ZOUT
100K
100M
FREQUENCY (Hz)
FIGURE SUPPLY CURRENT SUPPLY VOLTAGE
FIGURE INPUT/OUTPUT IMPEDANCE FREQUENCY
RLOAD PSRR (dB)
VOUT MAX, VP-P 100kHz
25oC 125oC, -55oC
SUPPLY VOLTAGE (±V)
100K
FREQUENCY (Hz)
100M
FIGURE VOUT MAXIMUM VSUPPLY
FIGURE PSRR FREQUENCY
1500 1400 SLEW RATE (V/µs) 1300 1200 1100 1000 SUPPLY VOLTAGE (±V) VOUT (mV)
±15V 25oC
-100 -150 INPUT VOLTAGE (VOLTS)
FIGURE SLEW RATE SUPPLY VOLTAGE
FIGURE GAIN ERROR INPUT VOLTAGE
HA-5002 Characteristics
DIMENSIONS: mils mils mils 2050µm 2030µm 483µm METALLIZATION: Type: Thickness: PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, Phos.) Silox Thickness: Nitride Thickness: SUBSTRATE POTENTIAL (Powered Up): V1TRANSISTOR COUNT: PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5002
V1IN
(ALT) (ALT)
HA-5002 Metal Packages (Can)
REFERENCE PLANE BASE SEATING PLANE BASE METAL LEAD FINISH
T8.C MIL-STD-1835 MACY1-X8 (A1)
LEAD METAL PACKAGE INCHES SYMBOL 0.165 0.016 0.016 0.016 0.335 0.305 0.110 0.185 0.019 0.021 0.024 0.375 0.335 0.160 MILLIMETERS 4.19 0.41 0.41 0.41 8.51 7.75 2.79 4.70 0.48 0.53 0.61 9.40 8.51 4.06 NOTES Rev. 5/18/94
0.200 0.100 0.027 0.027 0.500 0.250 0.010 0.040 0.034 0.045 0.750 0.050 0.045
5.08 2.54 1.02 0.86 1.14 19.05 1.27 1.14
0.69 0.69 12.70 6.35 0.25
SECTION
NOTES: (All leads) applies between applies between 0.500 from reference plane. Diameter uncontrolled beyond 0.500 from reference plane. Measured from maximum diameter product. basic spacing from centerline terminal basic spacing each lead lead position places) from looking bottom package. maximum number terminal positions. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH.
HA-5002 Dual-In-Line Plastic Packages (PDIP)
INDEX AREA
E8.3 (JEDEC MS-001-BA ISSUE
LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
MILLIMETERS 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES Rev. 12/93
0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240
0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280
BASE PLANE SEATING PLANE 0.010 (0.25)
NOTES: Controlling Dimensions: INCH. case conflict between English Metric dimensions, inch dimensions control. Dimensioning tolerancing ANSI Y14.5M-1982. Symbols defined Series Symbol List" Section Publication Dimensions measured with package seated JEDEC seating plane gauge GS-3. dimensions include mold flash protrusions. Mold flash protrusions shall exceed 0.010 inch (0.25mm). measured with leads constrained perpendicular datum measured lead tips with leads unconstrained. must zero greater. maximum dimensions include dambar protrusions. Dambar protrusions shall exceed 0.010 inch (0.25mm). maximum number terminal positions. Corner leads E8.3, E16.3, E18.3, E28.3, E42.6 will have dimension 0.030 0.045 inch (0.76 1.14mm).
0.100 0.300 0.115 0.430 0.150
2.54 7.62 10.92 3.81
2.93
HA-5002 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.050 (1.27)
N20.35 (JEDEC MS-018AA ISSUE
0.004 (0.10)
LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL 0.165 0.090 0.385 0.350 0.141 0.385 0.350 0.141 0.180 0.120 0.395 0.356 0.169 0.395 0.356 0.169 MILLIMETERS 4.20 2.29 9.78 8.89 3.59 9.78 8.89 3.59 4.57 3.04 10.03 9.04 4.29 10.03 9.04 4.29 NOTES Rev. 11/97
0.025 (0.64) 0.045 (1.14)
D2/E2 D2/E2 VIEW
0.020 (0.51) PLCS
0.020 (0.51)
SEATING PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14)
0.025 (0.64) VIEW TYP.
NOTES: Controlling dimension: INCH. Converted millimeter dimensions necessarily exact. Dimensions tolerancing ANSI Y14.5M-1982. Dimensions include mold protrusions. Allowable mold protrusion 0.010 inch (0.25mm) side. Dimensions include mold mismatch measured extreme material condition body parting line. measured seating plane contact point. Centerline determined where center leads exit plastic body. number terminal positions.
HA-5002 Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
-A-DBASE METAL -Bbbb BASE PLANE SEATING PLANE SECTION LEAD FINISH
F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION
LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES SYMBOL 0.014 0.014 0.045 0.023 0.008 0.008 0.220 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS 0.36 0.36 1.14 0.58 0.20 0.20 5.59 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 NOTES Rev. 4/94
eA/2
eA/2
0.100 0.300 0.150 0.125 0.015 0.005 0.200 0.060 105o 0.015 0.030 0.010 0.0015
2.54 7.62 3.81 3.18 0.38 0.13 5.08 1.52 105o 0.38 0.76 0.25 0.038
NOTES: Index area: notch identification mark shall located adjacent shall located within shaded area shown. manufacturer's identification shall used identification mark. maximum limits lead dimensions shall measured centroid finished lead surfaces, when solder plate lead finish applied. Dimensions apply lead base metal only. Dimension applies lead plating finish thickness. Corner leads N/2, N/2+1) configured with partial lead paddle. this configuration dimension replaces dimension This dimension allows off-center lid, meniscus, glass overrun. Dimension shall measured from seating plane base plane. Measure dimension four corners. maximum number terminal positions. Dimensioning tolerancing ANSI Y14.5M 1982. Controlling dimension: INCH
HA-5002 Small Outline Plastic Packages (SOIC)
INDEX AREA SEATING PLANE 0.25(0.010)
M8.15 (JEDEC MS-012-AA ISSUE LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 MILLIMETERS 1.35 0.10 0.33 0.19 4.80 3.80 1.75 0.25 0.51 0.25 5.00 4.00 NOTES Rev. 12/93
0.10(0.004)
0.050 0.2284 0.0099 0.016 0.2440 0.0196 0.050
1.27 5.80 0.25 0.40 6.20 0.50 1.27
0.25(0.010)
NOTES: Symbols defined Series Symbol List" Section Publication Number Dimensioning tolerancing ANSI Y14.5M-1982. Dimension does include mold flash, protrusions gate burrs. Mold flash, protrusion gate burrs shall exceed 0.15mm (0.006 inch) side. Dimension does include interlead flash protrusions. Interlead flash protrusions shall exceed 0.25mm (0.010 inch) side. chamfer body optional. present, visual index feature must located within crosshatched area. length terminal soldering substrate. number terminal positions. Terminal numbers shown reference only. lead width "B", measured 0.36mm (0.014 inch) greater above seating plane, shall exceed maximum value 0.61mm (0.024 inch). Controlling dimension: MILLIMETER. Converted inch dimensions necessarily exact.
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110MHz, High Slew Rate, High Output Current Buffer HA-5002 monoli

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