16-Bit, 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER
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ADS8341
16-Bit, 4-Channel Serial Output Sampling ANALOG-TO-DIGITAL CONVERTER
FEATURES
WITH ADS7841 SINGLE SUPPLY: 2.7V 4-CHANNEL SINGLE-ENDED 2-CHANNEL DIFFERENTIAL INPUT 100kHz CONVERSION RATE 86dB SINAD SERIAL INTERFACE SSOP-16 PACKAGE
DESCRIPTION
ADS8341 4-channel, 16-bit sampling analogto-digital converter (ADC) with synchronous serial interface. Typical power dissipation 100kHz throughput rate supply. reference voltage (VREF) varied between 500mV VCC, providing corresponding input voltage range VREF. device includes shutdown mode which reduces power dissipation under 15µW. ADS8341 guaranteed down 2.7V operation. power, high speed, onboard multiplexer make ADS8341 ideal battery-operated systems such personal digital assistants, portable multichannel data loggers, measurement equipment. serial interface also provides low-cost isolation remote data acquisition. ADS8341 available SSOP-16 package guaranteed over -40°C +85°C temperature range.
APPLICATIONS
DATA ACQUISITION TEST MEASUREMENT INDUSTRIAL PROCESS CONTROL PERSONAL DIGITAL ASSISTANTS BATTERY-POWERED SYSTEMS
DCLK
VREF Four Channel Multiplexer CDAC Comparator Serial Interface Control SHDN DOUT BUSY
Copyright 2000, Texas Instruments Incorporated
SBAS136A
Printed U.S.A. December, 2000
SPECIFICATION:
-40°C +85°C, +VCC +5V, VREF +5V, fSAMPLE 100kHz, fCLK fSAMPLE 2.4MHz, unless otherwise noted. ADS8341E, PARAMETER RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE Missing Codes Integral Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) Signal-to-(Noise Distortion) Spurious Free Dynamic Range Channel-to-Channel Isolation REFERENCE INPUT Range Resistance Input Current ±0.05 Positive Input Negative Input Positive Input Negative Input -0.2 -0.2 ±0.024 CONDITIONS VREF +VCC +0.2 +1.25 ADS8341EB, UNITS BITS Bits LSB(1) µVrms LSB(1) Cycles Cycles +0.8 Straight Binary Specified Performance fSAMPLE 12.5kHz Power-Down Mode(3), +VCC Power Dissipation TEMPERATURE RANGE Specified Performance Same specifications ADS8341E. NOTES: means Least Significant Bit. With VREF equal +5.0V, 76µV. First five harmonics test frequency. Auto power-down mode (PD1 active SHDN GND. 4.75 5.25
+4.75V 5.25V
0.024 DCLK Static fSAMPLE 12.5kHz DCLK Static 0.001 CMOS +5µA +5µA -250µA 250µA -0.3 +VCC
SHDN Data Transfer Only 5Vp-p 5Vp-p 5Vp-p 5Vp-p 10kHz 10kHz 10kHz 50kHz
DIGITAL INPUT/OUTPUT Logic Family Logic Levels Data Format POWER SUPPLY REQUIREMENTS +VCC Quiescent Current
ADS8341
SBAS136A
SPECIFICATION: +2.7V
-40°C +85°C, +VCC +2.7V, VREF +2.5V, fSAMPLE 100kHz, fCLK fSAMPLE 2.4MHz, unless otherwise noted. ADS8341E, PARAMETER RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range Capacitance Leakage Current SYSTEM PERFORMANCE Missing Codes Integral Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter Internal Clock Frequency External Clock Frequency ±0.05 Positive Input Negative Input Positive Input Negative Input -0.2 -0.2 ±0.5 ±0.0024 CONDITIONS VREF +VCC +0.2 +0.2 ADS8341EB, UNITS BITS Bits µVrms LSB(1) Cycles Cycles
+2.7 +3.3V
0.024 0.024 +VCC 0.001 CMOS +5µA +5µA -250µA 250µA +VCC -0.3 +VCC Straight Binary Specified Performance fSAMPLE 12.5kHz Power-Down Mode(3), +VCC 1.85 +0.8
SHDN When Used with Internal Clock Data Transfer Only
DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) Signal-to-(Noise Distortion) Spurious Free Dynamic Range Channel-to-Channel Isolation REFERENCE INPUT Range Resistance Input Current 2.5Vp-p 2.5Vp-p 2.5Vp-p 2.5Vp-p 10kHz 10kHz 10kHz 50kHz DCLK Static fSAMPLE 12.5kHz DCLK Static DIGITAL INPUT/OUTPUT Logic Family Logic Levels Data Format POWER SUPPLY REQUIREMENTS +VCC Quiescent Current
Power Dissipation TEMPERATURE RANGE Specified Performance Same specifications ADS8341E.
NOTES: means Least Significant Bit. With VREF equal +5.0V, 76µV. First five harmonics test frequency. Auto power-down mode (PD1 active SHDN GND.
ADS8341
SBAS136A
CONFIGURATIONS
View SSOP
ABSOLUTE MAXIMUM RATINGS(1)
+VCC -0.3V Analog Inputs -0.3V +VCC 0.3V Digital Inputs -0.3V Power Dissipation 250mW Maximum Junction Temperature +150°C Operating Temperature Range -40°C +85°C Storage Temperature Range -65°C +150°C Lead Temperature (soldering, 10s) +300°C NOTE: Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum conditions extended periods affect device reliability.
+VCC SHDN VREF
ADS8341
DCLK BUSY DOUT +VCC
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit damaged ESD. Burr-Brown recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
DESCRIPTIONS
NAME +VCC SHDN VREF +VCC DOUT BUSY DCLK DESCRIPTION Power Supply, 2.7V Analog Input Channel Analog Input Channel Analog Input Channel Analog Input Channel Ground Reference Analog Inputs. Sets zero code voltage single-ended mode. Connect this ground ground reference point. Shutdown. When LOW, device enters very power shutdown mode. Voltage Reference Input. Specification Table ranges. Power Supply, 2.7V Ground. Connect Analog Ground Ground. Connect Analog Ground. Serial Data Output. Data shifted falling edge DCLK. This output high impedance when HIGH. Busy Output. This output high impedance when HIGH. Serial Data Input. LOW, data latched rising edge DCLK. Chip Select Input. Controls conversion timing enables serial input/output register. External Clock Input. This clock runs conversion process synchronizes serial data I/O. Maximum input clock frequency equals 2.4MHz achieve 100kHz sampling rate.
PACKAGE/ORDERING INFORMATION
MAXIMUM INTEGRAL LINEARITY ERROR (LSB) MISSING CODES ERROR (LSB)
PRODUCT ADS8341E ADS8341EB
SPECIFICATION TEMPERATURE RANGE -40°C +85°C -40°C +85°C
PACKAGE SSOP-16 SSOP-16
PACKAGE DRAWING NUMBER
ORDERING NUMBER(1) ADS8341E ADS8341E/2K5 ADS8341EB ADS8341EB/2K5
TRANSPORT MEDIA Rails Tape Reel Rails Tape Reel
NOTE: Models with slash available only Tape Reel quantities indicated (e.g., /2K5 indicates 2500 devices reel). Ordering 2500 pieces "ADS8341E/2K5" will single 2500-piece Tape Reel.
ADS8341
SBAS136A
TYPICAL PERFORMANCE CURVES:
+25°C, +VCC +5V, VREF +5V, fSAMPLE 100kHz, fCLK fSAMPLE 2.4MHz, unless otherwise noted.
FREQUENCY SPECTRUM (4096 Point FFT; 1.001kHz, -0.2dB)
Amplitude (dB)
FREQUENCY SPECTRUM (4096 Point FFT; 9.985kHz, -0.2dB)
Amplitude (dB)
-100 -120 -140 -160 Frequency (kHz)
-100 -120 -140 -160 Frequency (kHz)
SIGNAL-TO-NOISE RATIO SIGNAL-TO- (NOISE+DISTORTION) INPUT FREQUENCY
SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION INPUT FREQUENCY -100 SFDR
SINAD (dB)
SFDR (dB)
SINAD
(dB)
THD*
First Nine Harmonics Input Frequency
Frequency (kHz)
Frequency (kHz)
EFFECTIVE NUMBER BITS INPUT FREQUENCY 15.0 14.5 Effective Number Bits 14.0 13.5 13.0 12.5 12.0 11.5 11.0 Frequency (kHz) Delta from 25°C (dB)
-0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4
CHANGE SIGNAL-TO-(NOISE+DISTORTION) TEMPERATURE 9.985kHz, -0.2dB
Temperature (°C)
ADS8341
SBAS136A
TYPICAL PERFORMANCE CURVES: (Cont.)
+25°C, +VCC +5V, VREF +5V, fSAMPLE 100kHz, fCLK fSAMPLE 2.4MHz, unless otherwise noted.
INTEGRAL LINEARITY ERROR CODE
DIFFERENTIAL LINEARITY ERROR CODE
(LSBS)
(LSBS)
0000h
0000h
4000h
8000h Output Code
C000h
FFFFh
4000h
8000h Output Code
C000h
FFFFh
CHANGE OFFSET TEMPERATURE 0.40 0.30
CHANGE GAIN TEMPERATURE
Change Offset (LSB)
0.50
Change Gain (LSB)
0.20 0.10 0.00 -0.10 -0.20
0.00
-0.50
-1.00
-1.50 Temperature (°C)
-0.30 Temperature (°C)
WORST CASE CHANNEL-TO-CHANNEL OFFSET MATCH TEMPERATURE 2.50
0.35 0.30
WORST CASE CHANNEL-TO-CHANNEL GAIN MATCH TEMPERATURE
2.00
Offset Match (LSB)
1.50
Gain Match (LSB)
0.25 0.20 0.15 0.10 0.05
1.00
0.50
0.00 Temperature (°C)
0.00 Temperature (°C)
ADS8341
SBAS136A
TYPICAL PERFORMANCE CURVES: (Cont.)
+25°C, +VCC +5V, VREF +5V, fSAMPLE 100kHz, fCLK fSAMPLE 2.4MHz, unless otherwise noted.
TEMPERATURE 1.45
1.40
(mA)
1.35
1.20
1.25 Temperature (°C)
ADS8341
SBAS136A
TYPICAL PERFORMANCE CURVES: +2.7V
+25°C, +VCC +2.7V, VREF +2.5V, fSAMPLE 100kHz, fCLK fSAMPLE 2.4MHz, unless otherwise noted.
FREQUENCY SPECTRUM (4096 Point FFT; 1.001kHz, -0.2dB)
Amplitude (dB)
FREQUENCY SPECTRUM (4096 Point FFT; 9.985kHz, -0.2dB)
Amplitude (dB)
-100 -120 -140 -160 Frequency (kHz)
-100 -120 -140 -160 Frequency (kHz)
SIGNAL-TO-NOISE RATIO SIGNAL-TO- (NOISE+DISTORTION) INPUT FREQUENCY SINAD (dB) Frequency (kHz) SINAD
SPURIOUS FREE DYNAMIC RANGE TOTAL HARMONIC DISTORTION INPUT FREQUENCY
SFDR
SFDR (dB)
THD*
First nine harmonics input frequency. Frequency (kHz)
EFFECTIVE NUMBER BITS INPUT FREQUENCY
CHANGE SIGNAL-TO-(NOISE+DISTORTION) TEMPERATURE 9.985kHz, -0.2dB
Effective Number Bits
Delta from 25°C (dB)
Frequency (kHz)
-0.5 -1.0 -1.5 -2.0 Temperature (°C)
ADS8341
SBAS136A
TYPICAL PERFORMANCE CURVES: +2.7V (Cont.)
+25°C, +VCC +2.7V, VREF +2.5V, fSAMPLE 100kHz, fCLK fSAMPLE 2.4MHz, unless otherwise noted.
INTEGRAL LINEARITY ERROR CODE
(LSBS) (LSBS)
DIFFERENTIAL LINEARITY ERROR CODE 0000h
0000h
4000h
8000h Output Code
C000h
FFFFh
4000h
8000h Output Code
C000h
FFFFh
CHANGE OFFSET TEMPERATURE 0.30 0.20
Change Offset (LSB)
0.200
CHANGE GAIN TEMPERATURE
0.100
0.10 0.00 -0.10 -0.20 -0.30 Temperature (°C)
Change Gain (LSB)
0.000
-0.100
-0.200
-0.300 Temperature (°C)
WORST CASE CHANNEL-TO-CHANNEL OFFSET MATCH TEMPERATURE 0.400
WORST CASE CHANNEL-TO-CHANNEL GAIN MATCH TEMPERATURE 0.200
Offset Match (LSB)
0.300
0.150
Gain Match (LSB)
0.200
0.100
0.100
0.050
0.000 Temperature (°C)
0.000 Temperature (°C)
ADS8341
SBAS136A
TYPICAL PERFORMANCE CURVES: +2.7V (Cont.)
+25°C, +VCC +2.7V, VREF +2.5V, fSAMPLE 100kHz, fCLK fSAMPLE 2.4MHz, unless otherwise noted.
SUPPLY CURRENT +VSS Supply Current (mA) fSAMPLE 100kHz VREF +VSS
TEMPERATURE 1.15
1.10
(mA)
1.05
1.00
+VSS
0.95 Temperature (°C)
ADS8341
SBAS136A
THEORY OPERATION
ADS8341 classic successive approximation register (SAR) analog-to-digital (A/D) converter. architecture based capacitive redistribution which inherently includes sample/hold function. converter fabricated 0.6µm CMOS process. basic operation ADS8341 shown Figure device requires external reference external clock. operates from single supply 2.7V 5.25V. external reference voltage between 500mV +VCC. value reference voltage directly sets input range converter. average reference input current depends conversion rate ADS8341. analog input converter differential provided four-channel multiplexer. input provided reference voltage (which generally ground) differentially using four input channels (CH0 CH3). particular configuration selectable digital interface. ANALOG INPUT Figure shows block diagram input multiplexer ADS8341. differential input converter derived from four inputs reference four inputs. Table Table show relationship between SGL/DIF control bits configuration analog multiplexer. control bits provided serially pin, Digital Interface section this data sheet more details. When converter enters hold mode, voltage difference between inputs (see Figure captured internal capacitor array. voltage input limited between -0.2V 1.25V, allowing input reject small signals which common both input. input range -0.2V +VCC 0.2V.
input current analog inputs depends conversion rate device. During sample period, source must charge internal sampling capacitor (typically 25pF). After capacitor been fully charged, there further input current. rate charge transfer from analog source converter function conversion rate.
TABLE Single-Ended Channel Selection (SGL/DIF HIGH).
TABLE Differential Channel Control (SGL/DIF LOW).
A2-A0 (Shown 001B)
Converter
SGL/DIF (Shown HIGH)
FIGURE Simplified Diagram Analog Input.
+2.7V ADS8341 10µF 0.1µF Single-ended differential analog inputs 0.1µF +VCC SHDN VREF DCLK BUSY DOUT +VCC Serial Data Serial/Conversion Clock Chip Select Serial Data
FIGURE Basic Operation ADS8341.
ADS8341
SBAS136A
REFERENCE INPUT external reference sets analog input range. ADS8341 will operate with reference range 500mV +VCC. Keep mind that analog input difference between input input shown Figure example, single-ended mode, 1.25V reference, with grounded, selected input channel (CH0 CH3) will properly digitize signal range 1.25V. connected 0.5V, input range selected channel 0.5V 1.75V. There several critical items concerning reference input wide voltage range. reference voltage reduced, analog voltage weight each digital output code also reduced. This often referred (least significant bit) size equal reference voltage divided 536. offset gain error inherent converter will appear increase, terms size, reference voltage reduced. example, offset given converter LSBs with 2.5V reference, then will typically LSBs with 0.5V reference. each case, actual offset device same, 76µV. Likewise, noise uncertainty digitized output will increase with lower size. With reference voltage 500mV, size 7.6µV. This level below internal noise device. result, digital output code will stable vary around mean value number LSBs. distribution output codes will gaussian noise reduced simply averaging consecutive conversion results applying digital filter. With lower reference voltage, care should taken provide clean layout including adequate bypassing, clean (low noise, ripple) power supply, low-noise reference, low-noise input signal. Because size lower, converter will also more sensitive nearby digital signals electromagnetic interference. voltage into VREF input buffered directly drives capacitor digital-to-analog converter (CDAC) portion ADS8341. Typically, input current 13µA with 2.5V reference. This value will vary microamps depending result conversion. reference current diminishes directly with both conversion
rate reference voltage. current from reference drawn each decision, clocking converter more quickly during given conversion period will reduce overall current drain from reference. DIGITAL INTERFACE Figure shows typical operation ADS8341's digital interface. This diagram assumes that source digital signals microcontroller digital signal processor with basic serial interface (note that digital inputs over-voltage tolerant 5.5V, regardless +VCC). Each communication between processor converter consists eight clock cycles. complete conversion accomplished with three serial communications, total clock cycles DCLK input. first eight cycles used provide control byte pin. When converter enough information about following conversion input multiplexer appropriately, enters acquisition (sample) mode. After three more clock cycles, control byte complete converter enters conversion mode. this point, input sample/hold goes into hold mode. next sixteen clock cycles accomplish actual analog-to-digital conversion. Control Byte Also shown Figure placement order control bits within control byte. Tables give detailed information about these bits. first bit, bit, must always HIGH indicates start control byte. ADS8341 will ignore inputs until start detected. next three bits select active input channel channels input multiplexer (see Tables Figure
(MSB) (LSB)
SGL/DIF
TABLE III. Order Control Bits Control Byte.
tACQ
DCLK
Idle Acquire
Conversion
Idle Acquire
Conversion
SGL/
SGL/
(START)
(START)
BUSY
DOUT
(MSB)
(LSB)
Zero Filled.
(MSB)
FIGURE Conversion Timing, 24-Clocks Conversion, 8-Bit Interface. DCLK delay required with dedicated serial port.
ADS8341
SBAS136A
NAME
DESCRIPTION Start Bit. Control byte starts with first HIGH DIN. Channel Select Bits. Along with SGL/DIF bit, these bits control setting multiplexer input detailed Tables Single-Ended/Differential Select Bit. Along with bits this controls setting multiplexer input detailed Tables Power-Down Mode Select Bits. Table details.
Description Power-down between conversions. When each conversion finished, converter enters power mode. start next conversion, device instantly powers full power. There need additional delays assure full operation very first conversion valid. Internal clock mode. Reserved future use. power-down between conversions, device always powered.
SGL/DIF
TABLE Descriptions Control Bits within Control Byte. SGL/DIF controls multiplexer input mode: either single-ended (HIGH) differential (LOW). single-ended mode, selected input channel referenced pin. differential mode, selected inputs provide differential input. Tables Figure more information. last bits (PD1 PD0) select powerdown mode shown Table both inputs HIGH, device always powered both inputs LOW, device enters power-down mode between conversions. When conversion initiated, device will resume normal operation instantly-no delay needed allow device power very first conversion will valid. Clock Modes ADS8341 used with external serial clock internal clock perform successive-approximation conversion. both clock modes, external clock shifts data device. Internal clock mode selected when HIGH. user decides switch from clock mode other, extra conversion cycle will required before ADS8341 switch mode. extra cycle
TABLE Power-Down Selection. required because control bits need written ADS8341 prior change clock modes. External Clock Mode external clock mode, external clock only shifts data ADS8341, also controls conversion steps. BUSY will HIGH clock period after last control byte shifted Successiveapproximation decisions made appear DOUT each next SCLK falling edges (see Figure Figure shows BUSY timing external clock mode. Since clock cycle serial clock consumed with BUSY going high (while decision being made), additional clocks must given clock bits data; thus, conversion takes minimum clock cycles fully read data. Since most microprocessors communicate 8-bit transfers, this means that additional transfer must made capture LSB. There ways handling this requirement. shown Figure where beginning next control byte appears same time being clocked ADS8341. This method allows maximum throughput clock cycles conversion.
tCSS tCSH
DCLK
tBDV tBTR
BUSY
DOUT
FIGURE Detailed Timing Diagram.
ADS8341
SBAS136A
other method shown Figure which uses clock cycles conversion; last seven clock cycles simply shift zeros DOUT line. BUSY DOUT into high-impedance state when goes high; after next falling edge, BUSY will LOW. Internal Clock Mode internal clock mode, ADS8341 generates conversion clock internally. This relieves microprocessor from having generate conversion clock allows conversion result read back processor's convenience, clock rate from 0MHz 2.0MHz. BUSY goes start conversion then returns HIGH when conversion complete. During conversion, BUSY will remain maximum 8µs. Also, during conversion, SCLK should remain achieve best noise performance. conversion result stored internal register; data clocked this register time after conversion complete. when BUSY goes following conversion, next falling edge external serial clock will write DOUT line. remaining bits (D14-D0) will clocked each successive clock cycle following MSB. HIGH when BUSY goes then DOUT line will remain tri-state until goes (Figure does need remain once conversion started. Note that BUSY tri-stated when goes HIGH internal clock mode. Data shifted ADS8341 clock rates exceeding 2.4MHz, provided that minimum acquisition time tACQ, kept above 1.7µs. Digital Timing Figure Tables provide detailed timing digital interface ADS8341.
tACQ
SYMBOL tACQ tCSS tCSH tBDV tBTR
DESCRIPTION Acquisition Time Valid Prior DCLK Rising Hold After DCLK HIGH DCLK Falling DOUT Valid Falling DOUT Enabled Rising DOUT Disabled Falling First DCLK Rising Rising DCLK Ignored DCLK HIGH DCLK DCLK Falling BUSY Rising Falling BUSY Enabled Rising BUSY Disabled
UNITS
TABLE Timing Specifications (+VCC +2.7V 3.6V, -40°C +85°C, CLOAD 50pF).
SYMBOL tACQ tCSS tCSH tBDV tBTR DESCRIPTION Acquisition Time Valid Prior DCLK Rising Hold After DCLK HIGH DCLK Falling DOUT Valid Falling DOUT Enabled Rising DOUT Disabled Falling First DCLK Rising Rising DCLK Ignored DCLK HIGH DCLK DCLK Falling BUSY Rising Falling BUSY Enabled Rising BUSY Disabled UNITS
TABLE VII. Timing Specifications (+VCC +4.75V +5.25V, -40°C +85°C, CLOAD 50pF).
DCLK
Idle Acquire
Conversion
Idle
SGL/
(START)
BUSY
DOUT
(MSB)
(LSB)
Zero Filled.
FIGURE External Clock Mode Clocks Conversion.
tACQ
DCLK
Idle Acquire
Conversion
SGL/
(START)
BUSY
DOUT
(MSB)
(LSB)
Zero Filled.
FIGURE Internal Clock Mode Timing.
ADS8341
SBAS136A
Data Format ADS8341 output data straight binary format shown Figure This figure shows ideal output code given input voltage does include effects offset, gain, noise.
Full-Scale Voltage VREF VREF/65,536 11.111 11.110
DCLK active while ADS8341 auto power-down mode, device will continue dissipate some power digital logic. power reduced minimum keeping HIGH. differences supply current these cases shown Figure
1000 fCLK fSAMPLE
Output Code
11.101
Supply Current (µA)
00.010 00.001 00.000
fCLK 2.4MHz 25°C +VCC +2.7V VREF +2.5V fSAMPLE (Hz) 100k
Input Voltage(1) NOTE(1):
Voltage converter input, after multiplexer: +IN-(-IN). (See Figure
FIGURE Ideal Input Voltages Output Codes. POWER DISSIPATION There three power modes ADS8341: full power (PD1 11B), auto power-down (PD1 00B), shutdown (SHDN LOW). affects these modes varies depending ADS8341 being operated. example, full conversion rate 24-clocks conversion, there very little difference between full power mode auto power-down, shutdown (SHDN LOW) will lower power dissipation When operating full-speed 24-clocks conversion shown Figure ADS8341 spends most time acquiring converting. There little time auto powerdown, assuming that this mode active. Thus, difference between full power mode auto power-down negligible. conversion rate decreased simply slowing frequency DCLK input, modes remain approximately equal. However, DCLK frequency kept maximum rate during conversion, conversion simply done less often, then difference between modes dramatic. Figure shows difference between reducing DCLK frequency ("scaling" DCLK match conversion rate) maintaining DCLK highest frequency reducing number conversion second. later case, converter spends increasing percentage time power-down mode (assuming auto power-down mode active).
FIGURE Supply Current Directly Scaling Frequency DCLK with Sample Rate Keeping DCLK Maximum Possible Frequency.
Supply Current (µA)
0.09 0.00
25°C +VCC +2.7V VREF +2.5V fCLK fSAMPLE
(GND)
HIGH (+VCC) fSAMPLE (Hz) 100k
FIGURE Supply Current State Operating ADS8341 auto power-down mode will result lowest power dissipation, there conversion time "penalty" power-up. very first conversion will valid. SHDN used force immediate power-down.
ADS8341
SBAS136A
NOISE noise floor ADS8341 itself extremely low, seen from Figures thru much lower than competing converters. ADS8341 tested both 2.7V both internal external clock modes. level input applied analog input pins converter through 5,000 conversions. digital output converter will vary output code internal noise ADS8341. This true 16-bit SAR-type converters. Using histogram plot output codes, distribution should appear bellshaped with peak bell curve representing nominal code input value. distributions will represent 68.3%, 95.5%, 99.7%, respectively, codes. transition noise calculated dividing number codes measured this will yield distribution 99.7% codes. Statistically, codes could fall outside distribution when executing 1000 conversions. ADS8341, with output codes distribution, will yield ±0.5 transition noise operation. Remember, achieve this noise performance, peak-to-peak noise input signal reference must 50µV.
3619
7FFD 7FFE 7FFF Code
8000 8001
FIGURE Histogram 5000 Conversions Input Code Transition, 2.7V operation external clock mode.
3572
4606
7FFD 7FFE 7FFF Code
8000 8001
FIGURE Histogram 5000 Conversions Input Code Center, 2.7V operation internal clock mode.
7FFC 7FFE 7FFF Code 8000 8001
FIGURE Histogram 5000 Conversions Input Code Transition, operation external clock mode.
4614
AVERAGING noise converter compensated averaging digital codes. averaging conversion results, transition noise will reduced factor 1/n, where number averages. example, averaging conversion results will reduce transition noise ±0.25 LSBs. Averaging should only used input signals with frequencies near signals, digital filter used pass filter decimate output codes. This works similar manner averaging; every decimation signalto-noise ratio will improve 3dB.
7FFC
7FFE 7FFF Code
8000
8001
FIGURE Histogram 5000 Conversions Input Code Center, operation internal clock mode.
ADS8341
SBAS136A
LAYOUT
optimum performance, care should taken with physical layout ADS8341 circuitry. This particularly true reference voltage and/or conversion rate high. basic architecture sensitive glitches sudden changes power supply, reference, ground connections, digital inputs that occur just prior latching output analog comparator. Thus, during single conversion n-bit converter, there "windows" which large external transient voltages easily affect conversion result. Such glitches might originate from switching power supplies, nearby digital logic, high power devices. degree error digital output depends reference voltage, layout, exact timing external event. error change external event changes time with respect DCLK input. With this mind, power ADS8341 should clean well bypassed. 0.1µF ceramic bypass capacitor should placed close device possible. addition, 10µF capacitor series resistor used lowpass filter noisy supply.
reference should similarly bypassed with 0.1µF capacitor. Again, series resistor large capacitor used lowpass filter reference voltage. reference voltage originates from amp, make sure that drive bypass capacitor without oscillation (the series resistor help this case). ADS8341 draws very little current from reference average, does place larger demands reference circuitry over short periods time each rising edge DCLK during conversion). ADS8341 architecture offers inherent rejection noise voltage variation regards reference input. This particular concern when reference input tied power supply. noise ripple from supply will appear directly digital results. While high frequency noise filtered discussed previous paragraph, voltage variation line frequency (50Hz 60Hz) difficult remove. should connected clean ground point. many cases, this will "analog" ground. Avoid connections which near grounding point microcontroller digital signal processor. needed, ground trace directly from converter power supply entry point. ideal layout will include analog ground plane dedicated converter associated analog circuitry.
ADS8341
SBAS136A
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