TIGER320 interface that compliant with PC99, Power Management

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TIGER320 interface that compliant with PC99, Power Management

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TIGER320
interface that compliant with PC99, Power Management
Internet Phones (VoIP), Software modems, ISDN other applications that require cost interface with mastering
Features
PCI-SIG tested approved Power Management PC99 Meets requirements WHQL Enables Windows Logo certification TDM/IOM2 Industry standard serial Flexible with many configuration options Wide range codecs supported 32bit interface SLIC support Silicon Labs Si3210 ISDN AFEs supported Siemens ISAC ISDN Siemens IECQ ISDN Analog Modem Codecs supported Silicon Labs Si3021/Si3012 (US) Silicon Labs Si3021/Si3014 (Int.) Peripheral Interface (PIB) Byte wide data address lines control lines (AUX) Read Write Reset Fully programmable Subsystem Uses resistor pull-up/downs EEPROM required Class code programmable Network device Communications device Microsoft Windows Plug Play Sample driver code available ISDN drivers Windows95 Windows98 WindowsNT Windows 2000 (beta) interface versions interface versions On-chip crystal oscillator used codec clocks external clock requirement Supports cost crystal required Tiger320 logic 3.3V power supply Supports 3.3V signaling PQFP package 0.65mm lead spacing cost Easy handle
This document contains information product. Specifications information herein subject change without notice. brand names product names appearing this document registered trademarks trademarks their respective holders.
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Tiger320
Product Overview
General Description
Tiger320 been designed enable easy implementation cost interfacing solutions general-purpose requirements. Typical examples Internet phones where Tiger320 would partnered with SLIC, software modems where Tiger320 would partnered with codec, ISDN modems (terminal adaptors) where Tiger320 would partnered with ISDN hard analog modems where Tiger320 could enable 3.3V PC99 solution. interfaces provided, (Peripheral Interface Bus) TDM/IOM2/PCM highway serial interface. consists data port, address line control signals (read, write, reset) lines that configured chip selects, interrupts etc. chip interfaced address data this interface that would used. example this would UART hard modem chip set. interface used interfacing most popular SLIC, ISDN, Analog modem DAAs audio codecs. mastering used transfer data main memory host interfaces that both meet specification work across full range systems significant design challenge. Tiger320 leverages design expertise very successful Tiger300, Tiger100APC Tiger600 chips provides interface that meets requirements Power management specifications. subsystem vendor subsystem pull up/down resistors, this provides significant cost saving comparison with expensive EEPROM approach that used other vendors. addition Tiger320 provides crystal oscillator cell that used implement clock source codecs etc. This oscillator required circuitry Tiger320.
Ordering Information
order code Tiger320 Tiger320.
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Tiger320
Product Overview
Block Diagram
Peripheral Interface TDM/IOM2
Serial data
control register
Interrupt
AUX[7:0]
Revision
Data
ha[3:0]
System control logic
CNTL
Data register D-channel logic
Address decode
B-Channel Interface Controller
Configuration register
AD[31:0] Crystal oscillator cell
CNTL
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Tiger320
Product Overview
Table Contents
FEATURES GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM TABLE CONTENTS PIN-OUT Pin-out diagram assignment number Signal assignments functional category Signal descriptions FUNCTIONAL DESCRIPTION interface Address space Subsystem Vendor Subsystem class code Configuration space Peripheral Interface (PIB) Typical connection peripheral chip Tiger320 address mapping cycle address mapping memory cycle Data mapping Read cycle Write cycle lines Setting input output Reading status lines additional functions Setting Subsystem Vendor Crystal oscillator output Second signal Power state output lines control priority Highest priority hardware reset Lowest priority Internal register 0x2b PME# INT# generation logic TDM/IOM2 serial port Serial port interface Input clock Data transfer Second signal Parallel Serial/ Serial Parallel shift direction mastering Setup operation Status register Control register register addresses Software considerations Watchdog timer Crystal Oscillator Typical circuit
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Tiger320
Product Overview
REGISTERS Tiger320 Internal Register Description Reset cycle time offset 0x00 operation offset 0x01 Port Control 0x02 Port Data 0x03 Interrupt mask 0x04 Interrupt mask register 0x05 Interrupt status 0x06 Interrupt status 0x07 registers write starting address register 0x08 0x0B write interrupt address register 0x0C 0x0F write address register 0x10 0x13 Current write address register 0x14 0x17 read starting address register 0x18 0x1B read interrupt address register 0x1C 0x1F read address register 0x20 0x23 Current read address register 0x24 0x27 control registers mask register 0x29 polarity control register 0x2A select register 0x2B Second Serial Port Registers Second Frame delay count 0x2C Serial port Control Register 0x2D Second Frame count 0x2E Frame Sync (FSC) delay count 0x2F Configuration Space Description Chip Device Vendor offset 0x00 Status command offset 0x04 Class code revision offset 0x08 Header type Latency timer offset 0x0C Base address 0x10 Memory Base address 0x14 Subsystem Subsystem vendor 0x2C Capabilities Pointer [7:0] 0x34 Interrupts 0x3C PMC-Power Management Capabilities (APC) 0x40 Data register, PMCSR(APC) 0x44 WAVEFORMS waveforms Serial waveforms A.C. CHARACTERISTICS timing Serial timing D.C. CHARACTERISTICS Absolute Maximum Ratings Operating ranges TYPICAL APPLICATION SCHEMATICS PHYSICAL DIMENSIONS LEGAL WORDS REACH TIGERJET
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Tiger320
Product Overview
Pin-out Pin-out diagram
AD[30] AD[31] REQ# GNT# RST# AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AUX[0]/CK0 AUX[1] AUX[2] INTA#
AD[8] C/BE[0]#
AD[7] AD[6] VAUX AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] READ#
AD[12] AD[11] AD[10] AD[9]
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WRITE#
C/BE[3]# IDSEL AD[23] AD[22] AD[21] AD[20] PERR# AD[19] AD[18] AD[17] AD[16] C/BE[2]# FRAME# IRDY# TRDY# DEVSEL# STOP# SERR# C/BE[1]# AD[15] AD[14] AD[13]
AUX[3] DOUT DCLK PME# AUX[4]/PST0 AUX[5]/PST1 AUX[6] AUX[7]/FSC2 HD[0] HD[1] OSC2 OSC1 HD[2] HD[3] HD[4] HD[5] HD[6] HD[7] HA[0] HA[1] HA[2] HA[3] RESET#
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Tiger320
Product Overview
assignment number
Name C/BE[3]# IDSEL AD[23] AD[22] AD[21] AS[20] PERR# AD[19] AD[18] AD[17] AD[16] C/BE[2]# FRAME# IDRY# TRDY# DEVSEL# STOP# SERR# C/BE[1]# AD[15] AD[14] AD[13] AD[12] AD[11] AD[10] AD[9] Name AD[8] C/BE[0]# AD[7] AD[6] VAUX AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] READ# WRITE# EXTRST# HA[3] HA[2] HA[1] HA[0] HD[7] HD[6] HD[5] HD[4] HD[3] HD[2] OSC1 OSC2 HD[1] Name HD[0] AUX[7]/FSC2 AUX[6] AUX[5]/PST1 AUX[4]/PST0 PME# DCLK DOUT AUX[3] AUX[2] AUX[1] AUX[0]/CKO INTA# RST# GNT# REQ# AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] AD[25] AD[24]
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Tiger320
Product Overview
Signal assignments functional category
Peripheral Interface (PIB) Name AUX[0]/CKO AUX[1] AUX[2] AUX[3] AUX[4]/PST0 AUX[5]/PST1 AUX[6] AUX[7]FSC2 EXTRST# READ# WRITE# interface Name OSC1 OSC2 CKO/AUX[0]
Control Signals Name C/BE[0]# C/BE[1]# C/BE[2]# C/BE[3]# IDSEL FRAME# IRDY# TRDY# DEVSEL# STOP# INTA# RST# GNT# REQ# PERR# SERR# VAUX PME#
Serial Ports Name DCLK DOUT FSC2/AUX[7]
Address/Data Name AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31]
Name
Power Ground
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Tiger320
Product Overview
Signal descriptions
Signal Name AD[0:31] AUX[0] AUX[1] AUX[2:3] AUX[4] AUX[5] AUX[6] AUX[7] DCLK DOUT C/BE[0:3]# DEVSEL# EXTRST# FRAME# GNT# HA[0] HA[1] HA[2:3] HD[0:7] IDSEL INTA# IRDY# PAR# PME# OSC1 OSC2 PERR# REQ# READ# RST# STOP# SERR# TRDY# WRITE# Type Description Multiplexed address data port port port bits port port port port bits clock Serial port data clock Serial port data input Serial port data output command byte enable Device detect configuration read write cycles Reset IOM2 peripherals Cycle frame indicates beginning duration access Serial port frame sync grant master request address address address data Chip select configuration read write cycles interrupt Initiator ready Even parity across AD[0:31] C/BE[3:0]# Power management input output Parity Error master request read command Reset from Indicates current target requesting master stop current transaction System Error Target ready, completion current phase receiver write command Alternate Function Crystal Clock output Subsystem Vendor Power State output Configuration register 0x44 Power State output Configuration register 0x44 Subsystem Vendor Subsystem Vendor FSC2 output
Subsystem Vendor
Subsystem Vendor Subsystem Vendor Class code, 0=Network, 1=Com. Subsystem Vendor [8:9] Subsystem Vendor [0:7]
Subsystem Vendor
Subsystem Vendor
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Tiger320
Product Overview
Functional Description interface
Tiger320 implements compliant interface implements revision power management specification. Tiger320 built 3.3V process supports both 3.3V signaling environments. specifications available from special interest group www.pcisig.com Address space Internal registers address Tiger320 accessed either memory cycles. Tiger320 address space consists memory locations, actual base addresses configuration register memory. memory cycles used interchangeably access internal registers address space. first locations from base address enable access Tiger320 internal registers. following locations enable access address space. diagram below illustrates addressing concept.
address space Tiger320 internal registers address space
Subsystem Vendor subsystem vendor I.D. pull-up pull-down resistors following pins. Subsystem Vendor I.D. bits data Subsystem Vendor I.D. bits address Subsystem Vendor I.D. external reset EXTRST# Subsystem Vendor I.D. read command READ# Subsystem Vendor I.D. write command WRITE# Subsystem Vendor I.D. AUX[7] Subsystem Vendor I.D. AUX[1] Subsystem Vendor I.D. AUX[6] reset inputs read into configuration register 2Ch, important ensure that peripheral devices connected these inputs tri-state pins connected Tiger320 reset. default value subsystem vendor 0001H. pull-up/down resistors
Offset from base memory address
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built into input pads chip establish default values. When defining different subsystem vendor resistors only required pads that have pulled opposite state. mapping follows; Subsystem Vendor
Input AUX6 AUX1 AUX7 WRITE# READ# EXTRST#
Subsystem class code Subsystem class code pull-up pull down resistors following pins. Subsystem I.D. bits address mapping follows; Subsystem
Input
addition class code card Bit17 Network device Bit17 Communication device Configuration space Tiger320 implements standard configuration space, full details please consult specification.
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Tiger320
Product Overview
Peripheral Interface (PIB)
enables "glueless" interface most popular peripheral chips. Address, data control lines fully qualified access cycle time adjusted support slow devices.
HD[7:0] HA[3:0] READ# WRITE# EXTRESET#
Data[7:0] ADO[3:0] Reset# INT# Misc control Wakeup Powerstate[1] Powerstate[0]
Tiger320
AUX[0] AUX[1] AUX[2] AUX[3] AUX[5] AUX[4]
Peripheral chip
Typical connection peripheral chip Tiger320 connection details will vary with application, diagram above shows typical application. AUX[0] used generate chip select peripheral chip, event that more that peripheral chip required system, additional lines used generate chip select signals other chips. AUX[1] used generating interrupt, AUX[3] wake-up host more information register setting handling interrupt PME#, please section PME# INT# generation logic. event that peripheral into different power states, used these. address mapping cycle diagram below illustrates address mapped address.
equal config register both equal mapped
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address mapping memory cycle diagram below illustrates address mapped address.
equal config register equal both equal
mapped
Data mapping 8bit data that mapped lowest bits bus. This means that when data read from written specific address next valid address bytes higher. read date from next valid address C4h. Read cycle When read cycle takes place provided address been qualified, READ# signal will active cycles, actual number cycles determined setting bits internal register 0x00. Data from data will latched rising edge READ# transferred data bus. address driven Tiger320 clock cycle prior falling edge READ# pulse least cycle after rising edge READ# pulse. setup hold time latching data from 3nS. Write cycle When write cycle takes place provided address been qualified, WRITE# signal will active cycles, actual number cycles determined setting bits internal register 0x00. Data address information data will valid cycle prior falling edge WRITE# line. data will remain valid until cycle prior falling edge WRITE# signal.
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lines Setting input output AUX[7:0] pins individually programmed inputs outputs. Register 0x02 determines which pins defined inputs which defined outputs. Bit0 register controls state AUX0, bit1 controls AUX1 etc. register defines line output. register location defines appropriate line input. hard reset lines float defined inputs. Reading status status pins read from register 0x07. actual value will read irrespective being input output.
Reg. 0x02 [7:0] (write) Reg. 0x03 [7:0] (write) [7:0] Reg. 0x07 [7:0] (read)
lines additional functions Setting Subsystem Vendor AUX[7] used Subsystem vendor [13], AUX[6] Subsystem vendor AUX[1] Subsystem Vendor during hardware reset. After hardware reset, these pins will revert back normal operation. important that board level design ensures these pins will driven other devices during hardware reset time states during reset controlled pull-up/down resistors either internal pads external resistors. Crystal oscillator output AUX[0] programmed function crystal clock output. Internal register 0x2b used enable this function. When AUX[0] will output crystal oscillator. Second signal AUX[7] programmed function second signal serial bus. Internal register 0x2b used enable this function. When AUX[7] will second serial signal. Please refer serial port interface definition second serial signal. Power state output AUX[5:4] programmed output power state bits[1:0] from configuration register bits[1:0]). Internal register 0x2b used enable this function When this function will enabled.
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Tiger320
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lines control priority actual state definition AUX[0:7] pins follows priorities detailed below; Highest priority hardware reset hardware reset highest priority. When occurs, AUX[6:1:7] will used Subsystem Vendor ID[15:14:13]. will also clear internal registers 0x2b which will result AUX[7:0] input mode. Lowest priority Internal register 0x2b Internal register 0x2b second priority. When register 0x2b AUX[7:6] will outputs power state bits[1:0] matter what value register 0x2. When register 0x2b AUX[1] will used FSC2 when register 0x2b AUX[0] will (Crystal Oscillator Output). PME# INT# generation logic PME# (Power Management Event) used wake-up that sleep power down mode, example this could used modem wake when phone line rings. PME# generated from lines external event either active high low. Register 0x2a used invert inputs from pins. Register 0x29 used mask register. diagram below shows logical equivalence circuitry. INT# (Interrupt) generated exactly same manner with difference that register used mask register.
PME#
Register 0x29 [7:0]
[7:0] Register 0x2a [7:0]
INT#
Register [7:0]
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Tiger320
Product Overview
TDM/IOM2 serial port
Tiger320 serial port interface provides symmetrical full-duplex communication link either ISDN front such Siemens 2091 interface) 2186 (S/T interface). addition analog modem front ends such Silicon Labs general purpose audio codecs also supported. Serial port interface interface consists data clock (DCLK), frame synchronization clock (FSC) data lines (DIN DOUT). DCLK inputs Tiger320. DCLK either same data rate twice data rate. DCLK input Tiger320 same rate data rate, internal clock doubler should turned correct operation. There software controlled switches inverting DCLK control high pulse time clock doubler different applications. This interface fully compatible with IOM2 timing. channel channel used data communication. channel data will stored transferred through Tiger320 master logic from main system memory. serial port incoming data written main memory through master read port (read form codec written RAM). outgoing data read from main system memory through master write port (read from written out). Input clock input Tiger320 should clock. Within period, first bits data transmitted received. data clocked DCLK. details serial port timing please timing diagram section A.C. characteristics.
125uS
0~32 bits 0~32 bits
DOUT
bits
DOUT open-collector, should pulled high with external pull-up resistor. Outside data transfer window, DOUT either float DOUT pins forced drive low. This option allows some peripherals activate data clock. Data transfer Data transferred from IOM2 main system memory mastering.
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Second signal FSC2 signal option support second codec. FSC2 shared with AUX[7] enabled register 0x2B timing FSC2 controlled register 0x2C bit[4:0]. value register 0x2C bit[4:0] controls starting cycle FSC2 after signal. value register 0x2E bit[4:0] controls cycle number FSC2 stay before going high. There hardware guarantee FSC2 timing stroke happens during time FSC2. Parallel Serial/ Serial Parallel shift direction serial port data serially shifted from master channel. shift direction controlled register 0x2D bits used input other used output. shift register will shift right (LSB first). shift register will shift left (MSB first). Important note that shift register bits long. software driver needs arrange byte order data before DMAed IOM2 bus.
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mastering
Tiger320 master supports bi-directional data transfer. DMA-READ referred data transfer from serial input port system memory. DMA-WRITE data transferred from system memory serial output port. Each direction registers logic. They programmed different configurations transfer. Setup operation setup operation, first start address address registers need relevant physical system memory locations. Tiger320 logic does require counter value. difference between address start address will amount data that transferred DMA. start address data transferred bytes, address will minus needed point very last location first location serial port will always transfer bits data each frame sync. Important note that start addresses must double word boundary. Status register There interrupt address register enable status checking. When reaches interrupt address, will flag Interrupt status register (Index 0x6). Reading status register writing back read value interrupt occurred) will clear flag. Please note, writing will clear flag. Control register Control register (Index 0x0) controls mode generating interrupt. level trigger, this mode interrupt will occur when event happens status will remain only long conditions that created interrupt still exist. edge trigger, this mode interrupt will occur when event happens status will remain until cleared writing status register. Control register (Index 0x0) used configure operation mode. When master self-address mode. will automatically wrap around starting address ending address reached. normal mode, will stop when address reached. major difference between self-address mode normal mode hardware will continuously transfer data without attention self-address mode. start operation, Operation register (Index 0x1) stop operation, this this register used restart operation normal mode. This used self-address mode. status transfer monitored reading current address. This register contains current address pointer. Interrupt status register (Index 0x6) status current operation. Each generate interrupt mask set. event that master logic detects abort condition, Interrupt status register (Index 0x6) will based abort condition. cleared reading status register. recover master state machine, reset register reset also enable operation setting register
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Tiger320 register addresses Index write starting address Index write interrupt address Index 0x13 0x10 write address Index 0x17 0x14 write current address Index Index Index Index 0x1B 0x18 0x1F 0x1C 0x23 0x20 0x27 0x24 read starting address read interrupt address read address read current address
Product Overview
Software considerations basic setup flow Allocate non-cacheable continuous memory. start address registers. Fill write buffer. start bit. Self-address mode most powerful feature Tiger320. hardware only requires initialized once further software setup necessary. provides status registers interrupt host processor detect current status. Also, provides almost unlimited system memory buffer data transfer. Once setup, main timer polling routine monitor current status process downstream upstream data buffer. interval time based size allocated system memory. normal mode similar control flow controller. major difference there counter register. address used instead. Also, trigger it's control register. Watchdog timer 24-bit internal free running counter used watchdog timer. counter clocked system clock free running. will reset conditions. hardware reset. internal register read access. watchdog timer enabled, register 0x2b counter will overflow about 500ms without internal register access. event overflow logic will following; Generate reset pulse master block. This will stop operation. status (bit register 0x2B. Reset control register Reset bits[2:0] selection register 0x2B 24-bit counter divided into three counters. Each counter 0xFF reduce time counter overflow. Setting register 0x2B will counter [7:0] 1's. Setting register 0x2B will counter [15:8] 1's. Setting register 0x2B will counter [23:16] 1's. watchdog counter operate, bits need
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Tiger320
Product Overview
Crystal Oscillator
crystal oscillator cell essence inverting buffer that biased into high gain amplifier with feedback resistor. series mode crystal sets frequency oscillation. ensure reliable starting reset pulse will restart oscillator. Crystals between 1MHz 20MHz used. Typical circuit
Tiger320
recommended resister value ohm, capacitors should 10pF. crystal should placed close Tiger320 good layout practice followed.
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Tiger320
Product Overview
Registers Tiger320 Internal Register Description
Reset cycle time offset 0x00
operation mode interrupt mode cycle time cycle time Reserved Reset serial port Reset master EXTRST#
Type: Default: master operation mode Self address mode (continues loop) Normal operation interrupt mode Status will only when current address equal interrupt address address. Status will until status been cleared writing cycle time cycle operation (fastest) cycle operation cycle operation (slowest) cycle operation (slowest) NOTE cycle numbers read operation, write operation will cycle less. Reset serial port Normal operation Reset serial port logic Reset logic Normal operation Reset logic EXTRST# state External reset External reset high operation offset 0x01
Reserved Reserved Reserved Reserved Reserved Reserved Restart Enable
Type: Default: Restart Hold Restart using current setup, used "normal operation" Enable Stop
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Tiger320 Port Control 0x02
AuxC7 AuxC6 AuxC5 AuxC4 AuxC3 AuxC2
Product Overview
AuxC1
AuxC0
Type: Default value: AuxC[7:0] Line configured input Line configured output Port Data 0x03
AuxD7 AuxD6 AuxD5 AuxD4 AuxD3 AuxD2 AuxD1 AuxD0
Type: Default value: AuxD[7:0] Write Sets state lines configured outputs Read Reads status lines both inputs outputs Interrupt mask 0x04
Reserved Reserved Enable target abort Enable master abort Enable read address reach buffer address Enable read address reach interrupt address Enable write address reach buffer address Enable write address reach interrupt address
Type: Default: Enable target abort interrupt generated Interrupt generated when target abort occurs Enable master abort interrupt generated Interrupt generated when master abort occurs Enable read address reach buffer address interrupt generated Interrupt generated when read address reaches buffer address Enable read address reach interrupt address interrupt generated Interrupt generated when read address reaches interrupt address Enable write address reach interrupt address interrupt generated Interrupt generated when write address reaches interrupt address Enable write address reach buffer address interrupt generated Interrupt generated when write address reaches buffer address Interrupt mask register 0x05
AuxInt7 AuxInt6 AuxInt5 AuxInt4 AuxInt3 AuxInt2 AuxInt1 AuxInt0
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Type: Default value: AuxInt[7:0] Ignore input generation interrupt Select input(s) generate interrupt Interrupt status 0x06
Reserved Reserved target abort master abort read address reach buffer address read address reach interrupt address write address reach buffer address write address reach interrupt address
Type: R/W1TC Default: default value, depending chip status Note: when reading this register, immediately write back value that been read correct operation. target abort interrupt occurred Interrupt occurred target abort master abort interrupt occurred Interrupt occurred master abort read address reach buffer address interrupt occurred Interrupt occurred read address reaching buffer address read address reach interrupt address interrupt occurred Interrupt occurred read address reaching interrupt address write address reach interrupt address interrupt occurred Interrupt occurred write address reaching interrupt address write address reach buffer address interrupt occurred Interrupt occurred write address reaching buffer address Interrupt status 0x07
AUX7 AUX6 AUX5 AUX4 AUX3 AUX2 AUX1 AUX0
Type: Default: pins current value
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registers
write starting address register 0x08 0x0B Type: Default: Undetermined. 32bit starting address read from main memory write IOM2 port write interrupt address register 0x0C 0x0F Type: Default: Undetermined. 32bit address interrupt generated during read from main memory write IOM2 port write address register 0x10 0x13 Type: Default: Undetermined. 32bit ending address read from main memory write IOM2 port Current write address register 0x14 0x17 Type: Default: Undetermined. 32bit address which write process currently read starting address register 0x18 0x1B Type: Default: Undetermined. 32bit starting address read from IOM2 port write main memory read interrupt address register 0x1C 0x1F Type: Default: Undetermined. 32bit address interrupt generated during read from IOM2 port write main memory read address register 0x20 0x23 Type: Default: Undetermined. 32bit address read from IOM2 port write main memory Current read address register 0x24 0x27 Type: Default: Undetermined. 32bit address which read process currently
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control registers
mask register 0x29 Type: Default: select input used enable PME# output. Enable external event (such ring) switch computer. polarity control register 0x2A Type: Default: invert polarity data. select register 0x2B
watchdog timer[23:16] watchdog timer[15:8] wahtchdog timer[7:0] watchdog overflow Enable watchdog timer AUX[0] function selection AUX[7] function selection AUX[5:4] function selection
Type R/W, R/W1TC Default: AUX[5:4] becomes power state (reference config register 44h[1:0]) AUX[7] becomes FSC2 AUX[0] becomes crystal clock output enable watchdog timer Watchdog timer status. when watchdog timer expires. Writing will clear this bit. will watchdog timer [7:0] 1's. will watchdog timer [15:8] 1's. will watchdog timer [23:16] 1's.
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Second Serial Port Registers
Second Frame delay count 0x2C
Reserved Reserved FSC_D5 FSC_D4 FSC_D3 FSC_D2 FSC_D1 FSC_D0
Type: Default: 5:0, FSC_D[5:0] FSC2 delay count 0x00 0x1F cycle delay from cycle delay from
Serial port Control Register 0x2D
Serial port shift-out direction Serial port shift-in direction Reserved Reserved Invert DCLK Clock width selection Clock width selection Double Serial port clock DCLK
Type Default: 2XDCLK When doubles DCLK internally. Reset during power [2:1], DCLK_width Control internal double DCLK clock width. 10ns 20ns 30ns 40ns Invert DCLK When invert DCLK(After clock doubler) serial port block. Serial port shift-in direction first first Serial port shift-out direction first first
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Second Frame count 0x2E
Reserved Reserved FSC_LD5 FSC_LD4 FSC_LD3 FSC_LD2 FSC_LD1 FSC_LD0
Type: Default: 5:0, FSC_LD[5:0] FSC2 count 0x00 0x1F cycle time cycle time
Frame Sync (FSC) delay count 0x2F
Reserved Reserved FSC_DC5 FSC_DC4 FSC_DC3 FSC_DC2 FSC_DC1 FSC_DC0
Type: Default: 5:0, FSC_DC[5:0] delay count
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Configuration Space Description
Chip Device Vendor offset 0x00
Type: 0xE159h, number 0x0001h, device Status command offset 0x04
Detected Parity Error Signaled System Error Master abort Target abort Medium device Medium device Data Parity Error Detected
Caps (APC)
SERR# enable enable
Parity Error Response
Master enable
Memory enable
Default: 0x02100000 Detected Parity Error, Type: R/W1TC Error Detect address parity error Signaled System Error, Type: R/W1TC Error Asserted SERR# Master abort, Type: R/W1TC Normal operation Transaction terminated with Master-Abort Target abort, Type: R/W1TC Normal operation Transaction terminated with Target-Abort
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Tiger320 Medium device, [26:25] Type: Medium speed assert DEVSEL# Data Parity Error Detected, Type: R/W1TC Error Detect data parity error Capabilities, Type: Support capability SERR# enable, Type: Disable SERR# generation Enable SERR# generation Capabilities, Type: Disable Parity detection response Enable Parity detection response Master enable Type: Disables mastering Enable mastering Note: (disable) reset Memory enable Type: Disables response Memory Space accesses Enables response Memory Space accesses Note: (disable) reset enable Type: Disables response Space accesses Enables response Space accesses Note: (disable) reset Class code revision offset 0x08
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Class code Type: Subsystem 028000h network device 078000h communication device
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Revision Type: revision Header type Latency timer offset 0x0C
LatTim7 LatTim6 LatTim5 LatTim4 LatTim3 LatTim2 LatTim1 LatTim0
Default: 0x00000000 Header type Type: Defines layout predefined header LatTim [0:7] Type: Sets value clocks, latency timer master. Note: reset Base address 0x10
I/Obase I/Obase I/Obase I/Osize I/Obase I/Obase I/Obase I/Osize I/Obase I/Obase I/Obase I/Osize I/Obase I/Obase I/Obase I/Osize I/Obase I/Obase I/Obase I/Osize I/Obase I/Obase I/Obase I/Osize I/Obase I/Obase I/Obase I/Osize I/Obase I/Obase I/Obase I/Ospace
Default: 0x00000001 I/Obase Type: base address which device located, BIOS Note: register access either memory I/Osize Type: 00h, sets space bytes. I/Ospace Type: requests space allocation from BIOS.
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Tiger320 Memory Base address 0x14
Mbase Mbase Mbase Msize Mbase Mbase Mbase Msize Mbase Mbase Mbase Msize Mbase Mbase Mbase Msize Mbase Mbase Msize Msize Mbase Mbase Msize Msize
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Mbase Mbase Msize Msize
Mbase Mbase Msize Mspace
Default: 0x00000000 Mbase Type: memory base address which device located, BIOS Note: register access either memory Msize Type: 00h, sets memory space bytes. Mspace Type: requests memory space allocation from BIOS.
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Subsystem Subsystem vendor 0x2C
SubSysV15 SubSysV7 SubSysV14 SubSysV6 SubSysV13 SubSysV5 SubSysV12 SubSysV4 SubSysV11 SubSysV3 SubSysV10 SubSysV2 SubSys1 SubSysV9 SubSys0 SubSysV8
SubSysV1
SubSysV0
SubSys Type: Subsystem From, {AUX[6], AUX[1:0], WRITE#, READ#, EXTRST#,HA[3:2], HD[7:0]} SubSysV Type: Subsystem Vendor From HA[1:0] Capabilities Pointer [7:0] 0x34
Type: Default value 0x40 Interrupts 0x3C
IntLn7 IntLn6 IntLn5 IntLn4 IntLn3 IntLn2 IntLn1 INTA# IntLn0
Default: 0x80010100
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Maximum Latency: Type: Value 0x80: Minimum Grant: Type Value 0x01 INTA# Type: Indicates that interrupt used INTA#. Interrupt Line Type; Used POST software interrupt line routing information.
PMC-Power Management Capabilities (APC) 0x40
support D3cold current Next Item CapID support D3hot current Next Item CapID support support support Support Support current
Device Specific Next Item CapID
clock
Version Next Item CapID
Version Next Item CapID
Version Next Item CapID
Next Item CapID
Next Item CapID
Default VAUX default value 0x6C220001, VAUX default value 0xEC620001 support, [31:27] Type: VAUX value 01101b: Support D3hot, VAUX value 11101b: Support D3cold, D3hot, Support, Type: support Support, Type: support Aux_current, [24:22] Type: VAUX value 000b. VAUX value 001b. Device Specific, Type: require device specific initialization sequence. clock, Type:
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clock PME# generation. Version, [18:16] Type: 010b: Compiles with Revision Power Management Interface Specification. Next Item, [15:8] Type: next Item Capability [7:0] Type: 01h: List item power Management registers. Data register, PMCSR(APC) 0x44
Status enable Power State
Power State
Default: 0x00000000 status, Type: R/W1TC VAUX this reset when assert PME# signal. VAUX this sticky when assert PME# signal. enable, Type: VAUX this reset VAUX this sticky bit. enable PME# generation. Power State, [1:0] Type: VAUX these bits reset VAUX these bits sticky. Current power state. Only support definition field values given below. Write with will have effect.
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Waveforms waveforms READ# WRITE# tRDS tRDH tWDH tWDS
Serial waveforms DCLK tDIS tDIH DOUT tDOS tDOH
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A.C. Characteristics timing
Symbol tRDS tRDH tWDS tWDH Parameter Address setup time Address hold time Command pulse width Read data setup time Read data hold time Write data setup time Write data hold time Min(nS) Max(nS)
Serial timing
Symbol tDIS tDIH tDOS tDOH Parameter Serial clock period Data input setup time Data input hold time Data output setup time Data output hold time Min(nS) DCLK Max(nS)
DCLK DCLK
D.C. characteristics Absolute Maximum Ratings
Symbol Vout TSTG Parameter Power Supply Input Voltage Output Voltage Storage Temperature Rating -0.3 -0.3 -0.3 Units
Stresses above those listed under Absolute Maximum Ratings cause permanent device failure. Functionality above these limits implied. Exposure Absolute Maximum Ratings extended periods affect device reliability.
Operating ranges
Symbol TOPR Symbol Parameter Power Supply Input Voltage Operating Temperature Parameter Input Voltage Input Voltage Output Voltage, IOL= Output High Voltage, Pull-up Pull-down resistors Units Units
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Typical Application Schematics
Please visit www.tjnet.com schematics.
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Physical Dimensions
Please visit www.tjnet.com 100pin pqfp package drawing.
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Legal Words
TigerJet reserves rights make changes without further notice products herein. TigerJet makes warranty, representation guarantee regarding suitability products particular purpose, does TigerJet assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters which provided TigerJet data sheets and/or specifications vary different applications actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. TigerJet does convey license under patent rights rights others. TigerJet products designed, intended, authorized components systems intended surgical implant into body, other application intended support sustain life, other application which failure TigerJet product could create situation where personal injury death occur. Should Buyer purchase TigerJet products such unintended unauthorized application, Buyer shall indemnify hold TigerJet officers, employees, subsidiaries, affiliates distributors harmless against claims, costs, damages expenses reasonable attorney fees arising directly indirectly claim personal injury death associated with such unintended unauthorized use, even such claim alleges that TigerJet negligent regarding design manufacture part. TigerJet TJNET registered trademarks TigerJet Network Inc.
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TIGER320 interface that compliant with PC99, Power Management

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