MK2048 Phase-Locked Loop (PLL) based clock synthesizer, which accepts

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MK2048 Phase-Locked Loop (PLL) based clock synthesizer, which accepts

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MK2048 Communications Frequency Generator
MK2048 Phase-Locked Loop (PLL) based clock synthesizer, which accepts 8kHz clock input reference generates frequencies. device also accept 12.288 crystal input. outputs frequency locked together input. This allows generation locked clocks backplane clock, simplifying clock distribution communications systems. MicroClock customize this device many other different frequencies. Contact your MicroClock representative more details.
Features
Packaged narrow (150 mil) SOIC Accepts multiple inputs: 8kHz backplane clock, 12.288 crystal, Loop Timing frequencies Exact ratios stored device eliminate need external dividers Patented design give zero synthesis error output clocks. Output clock rates include ±10% operation
Block Diagram
FS3:0 Clock Synthesis Control Circuitry
Divider
Clock Input
External/ Loop Timing
Output Buffer
CLK1
Crystal/ Clock Select
Crystal Oscillator
Output Buffer
CLK2
12.288 crystal
CAP1
CAP2
Revision 022598 Printed 11/15/00 MicroClock Division Parkmoor
2048-01
MK2048 Communications Frequency Generator
Assignment
CAP1 CAP2 ICLK CLK2 CLK1 Output Clocks Decoding Table-Loop Timing (MHz)
Input 2.048 1.544 34.368 44.736 19.44 CLK1 2.048 1.544 17.184 22.368 9.72 CLK2 4.096 3.088 34.368 44.736 19.44
Output Clocks Decoding Table-External Mode (MHz)
Input 12.288 12.288 12.288 12.288 CLK1 2.048 1.544 17.184 22.368 38.88 38.88 9.72 2.048 1.544 17.184 22.368 CLK2 4.096 3.088 34.368 44.736 2.43 77.76 19.44 4.096 3.088 34.368 44.736
(150 mil) SOIC
connect directly ground, connect directly VDD. 12.288 input crystal applied pins other inputs applied
Descriptions
Number Name CAP1 CAP2 CLK1 CLK2 ICLK Type Description Crystal connection. Connect 12.288 crystal. Connect +5V. Connect +5V. Connect ceramic capacitor resistor series between this CAP2. Connect ground. Connect ceramic capacitor resistor series between this CAP1. Connect ground. Frequency Select Determines input/outputs table above. Frequency Select Determines input/outputs table above. Clock output determined status FS3:0 table above. Clock output determined status FS3:0 table above. Frequency Select Determines input/outputs table above. Input clock connection. Connect backplane other Loop Timing clock. Frequency Select Determines input/outputs table above. Connect. Nothing connected internally this pin. Crystal conection. Connect 12.288 crystal.
CLK1
CLK2
Type: Input, output, power supply connection, loop filter connection Revision 022598 Printed 11/15/00 MicroClock Division Parkmoor
2048-01
MK2048 Communications Frequency Generator
External Components/Crystal Selection
MK2048 requires minimum number external components proper operation. network should connected between CAP1 CAP2 close chip possible. high quality ceramic capacitor recommended, leave provisions sizes 10µF. decoupling capacitor 0.1µF must connected between pins (pins close chip, terminating resistors used clock outputs with traces longer than inch.
Electrical Specifications
Parameter Supply Voltage, Inputs Clock Outputs Ambient Operating Temperature Soldering Temperature Storage Temperature Operating Voltage, Input High Voltage, Input Voltage, Output High Voltage Output High Voltage Output Voltage Operating Supply Current, Short Circuit Current Input Capacitance, FS3:0 Conditions Referenced -0.5 seconds IOH=-4mA IOH=-25mA IOL=25mA Load, VDD=5.0V Each output VDD-0.4 ±100 Minimum Typical Maximum VDD+0.5 Units
ABSOLUTE MAXIMUM RATINGS (Note
CHARACTERISTICS (VDD unless noted)
CHARACTERISTICS (VDD unless noted)
Input Frequency ICLK 8.0000 Input Frequency 12.2880 Output Clock Rise Time 2.0V Output Clock Fall Time 0.8V Output Clock Duty Cycle, High Time VDD/2 Absolute Clock Period Jitter Actual mean frequency error versus target clock selection Notes: Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage device. Prolonged exposure levels above operating limits below Absolute Maximums affect device reliability.
Revision 022598 Printed 11/15/00 MicroClock Division Parkmoor
2048-01
MK2048 Communications Frequency Generator
Board Layout Loop Bandwidth critical successful proper board layout Loop Filter Component Selection
MK2048. particular, CAP1 CAP1 CAP2 (pins determine dynamic =connect series connected capacitor resistor between CAP2 pins areof thesensitive noise leakage very phase-locked loop. capacitor must have very leakage,14 characteristics therefore high quality (CAP1 capacitor most sensitive). Traces =connect ceramic recommended. type polarized electrolytic capacitor. values must asnetwork determine bandwidth PLL. short possible capacitor resistor must mounted next device resist. shown jitter ICLK input attenuation right. capacitor connected improves with decreasing values increasing values between point reached where startup until apins power supply time becomes unacceptably long. good starting point decoupling optimum values should determined spectral characteristics ICLK capacitor. jitter. high frequency output clocks pins benefit from series resistor print connected close gives theshown). this page. bandwidth needs (not approximate loop equation following formula modified MK2048 dividers.for MK2048: this when gets time. clk1 5/23/97
where:
loop bandwidth Hertz clk1 frequency CLK1 Hertz value capacitor Farads
example, CLK1 running 24MHz C=0.1 then
24x10 1x10-7
minimum absolute jitter required, network should replaced single capacitor with value between 0.01µF 2µF. Larger values will cause start more slowly. example, C=2µF, loop take several seconds start.
Revision 022598 Printed 11/15/00 MicroClock Division Parkmoor
2048-01
MK2048 Communications Frequency Generator
Package Outline Package Dimensions
SOIC narrow
Symbol Inches 0.055 0.070 0.013 0.019 0.007 0.010 0.385 0.400 0.150 0.160 0.225 0.245 .050 0.016 0.004 0.01 Millimeters 1.397 1.778 0.330 0.483 0.191 0.254 9.779 10.160 3.810 4.064 5.715 6.223 1.27 0.406 0.102 0.254
Ordering Information
Part/Order Number MK2048-01S MK2048-01STR Marking MK2048-01S MK2048-01S Package narrow SOIC Tape Reel Temperature 0-70°C 0-70°C
While information presented herein been checked both accuracy reliability, MicroClock Incorporated assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing MicroClock. MicroClock reserves right change circuitry specifications without notice. MicroClock does authorize warrant MicroClock product life support devices critical medical instruments.
CHANGE HISTORY Version Date first published 4/16/97 2/25/98
Comments Original Added layout diagram, updated logo
©1997 MicroClock Incorporated
Revision 022598 Printed 11/15/00 MicroClock Division Parkmoor
2048-01

MK2048 Phase-Locked Loop (PLL) based clock synthesizer, which accepts

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