Skew Output Buffer ICS9112 high performance, skew, jitter clock d

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Skew Output Buffer ICS9112 high performance, skew, jitter clock d

Datasheet Thumbnail

Top Searches for this datasheet

ICS9112-06/07
Skew Output Buffer
ICS9112 high performance, skew, jitter clock driver. uses phase lock loop (PLL) technology align, both phase frequency, input with CLKOUT signal. designed distribute high speed clocks systems operating speeds from 90mHz operation). ICS9112 zero delay buffer that provides synchronization between input output. synchronization established CLKOUT feed back input PLL. Since skew between input output less than +/350 part acts zero delay buffer. ICS9112 comes with different options; dash dash dash available SOIC package. banks four outputs controlled address lines. Depending selected address line, bank both banks tri-state mode. this mode, still running only output buffers high impedance mode. test mode shuts connects input directly output buffers (see table below functionality). dash eight SOIC package. five output clocks. absence input, both ICS9112-06 will power down mode. this mode, turned output buffers pulled low. Power down mode provides lowest power consumption standby condition.
Features
Zero input output delay Frequency range (3.3V), 30-90MHz (5.0V) Less than Jitter between outputs Skew controlled outputs Skew less than between outputs Available versions, SOIC packages 3.3V ±10%, 5.0V±10% operation
Configuration
SOIC
Block Diagram
SOIC
Functionality (-07)
CLKA Tristate Driven Test Mode Driven CLKB Tristate Tristate Test Mode Driven CLKOUT Driven Driven Test Mode Driven Output Source Shutdown
9112-06 9112-07 1/22/99
reserves right make changes device data identified this publication without further notice. advises customers obtain latest version device data verify that information being relied upon customer current accurate.
ICS9112-06/07
Descriptions
NUMBER NAME REF2 CLKA23 CLKA13 CLKB1 CLKB2
TYPE
DESCRIPTION Input reference frequency. tolerant input Buffered clock output, Bank Buffered clock output, Bank 3.3V supply Ground Buffered clock output. Bank Buffered clock output. Bank Select input, Select input, Buffered clock output. Bank Buffered clock output. Bank Buffered clock output, Bank Buffered clock output, Bank Buffered clock output, internal feedback this
CLKB3 CLKB4
CLKA2 CLKA3
CLKOUT
NUMBER
NAME REF2 CLK23 CLK33 CLK3 CLK4
TYPE
DESCRIPTION Input reference frequency. tolarant input Buffered clock output Buffered clock output Ground Buffered clock output 3.3v Supply Buffered clock output Buffered clock output. Internal feedback this
CLK6 (CLKOUT)3
Notes: Guaranteed design characterization. subject 100% test. Weak pull-down Weak pull-down outputs Weak pull-ups these inputs
ICS9112-06/07
Absolute Maximum Ratings
Supply Voltage Logic Inputs -0.5 +0.5 Ambient Operating Temperature +70°C Storage Temperature -65°C +150°C Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only functional operation device these other conditions above those listed operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
Electrical Characteristics 3.3V
unless otherwise stated
Characteristics PARAMETER Input Voltage Input High Voltage Input Current Input High Current Output Voltage1 SYMBOL VIN=0V VIN=VDD Unloaded oututs 66.66 inputs 0.10 0.25 37.0 16.0 75.0 40.0 50.0 100.0 TEST CONDITIONS UNITS
Output High Voltage1 Power Down Supply Current Supply Current
Notes: Guaranteed design characterization. subject 100% test. Skew specifications mesured with transmission line, load teminated with 1.4V. Duty cycle measured 1.4V. Skew measured 1.4V rising edges. Loading must equal outputs.
ICS9112-06/07
Switching Characteristics (3.3V Continued)
PARAMETER Output period Output period Duty Cycle1 Rise Time1 Rise Time1 Fall Time1 Fall Time1 Delay, Rising Edge CLKOUT Rising Edge1, Output Output Skew1 Device Device Skew1 Cycle Cycle Jitter1 Lock Time1 Jitter; Absolute Jitter1 Jitter; Sigma1 SYMBOL Tskew Tdsk-Tdsk Tcyc-Tcyc tLOCK Tjabs Tj1s CONDITION With CL=30pF With CL=20pF Measured 1.4V; CL=30pF Measured between 0.8V 2.0V: CL=30pF Measured between 0.8V 2.0V: CL=20pF Measured between 2.0V 0.8V; CL=30pF Measured between 2.0V 0.8V; CL=20pF Measured VDD/2 outputs equally loaded, CL=20pF Measured VDD/2 CLKOUT pins devices Measured 66.66 MHz, loaded outputs Stable power supply, valid clock presented 10,000 cycles CL=30pF F=20 50MHz 10,000 cycles CL=30pF F=20 50MHz -100 40.00 (25) 40.00 (25) 40.0 49.1 1.70 1.50 20.00 (50) 13.33 (75) 60.0 2.50 2.50 ±350 UNITS (MHz) (MHz)
Notes: Guaranteed design characterization. subject 100% test. input threshold voltage VDD/2 parameters expected with loaded outputs
ICS9112-06/07
Electrical Characteristics 5.0V
unless otherwise stated
Characteristics PARAMETER Input Voltage Input High Voltage Input Current Input High Current Output Voltage1 SYMBOL VIN=0V VIN=VDD 10mA 10mA Unloaded oututs 66.66 inputs -100 0.10 0.25 100.0 TEST CONDITIONS UNITS
Output High Voltage1 Power Down Supply Current Supply Current
Notes: Guaranteed design characterization. subject 100% test. Skew specifications mesured with transmission line, load teminated with 1.4V. Duty cycle measured 1.4V. Skew measured 1.4V rising edges. Loading must equal outputs.
ICS9112-06/07
Switching Characteristics (5.0V Continued)
PARAMETER Output period Output period Duty Cycle1 Rise Time1 Rise Time1 Fall Time1 Fall Time1 Delay, Rising Edge CLKOUT Rising Edge1, Output Output Skew1 Device Device Skew1 Cycle Cycle Jitter1 Lock Time1 Jitter; Absolute Jitter1 Jitter; Sigma1 SYMBOL Tskew Tdsk-Tdsk Tcyc-Tcyc tLOCK Tjabs Tj1s CONDITION With CL=30pF With CL=20pF Measured 1.4V; CL=30pF Measured between 0.8V 2.0V: CL=30pF Measured between 0.8V 2.0V: CL=20pF Measured between 2.0V 0.8V; CL=30pF Measured between 2.0V 0.8V; CL=20pF Measured VDD/2 outputs equally loaded, CL=20pF Measured VDD/2 CLKOUT pins devices Measured 66.66 MHz, loaded outputs Stable power supply, valid clock presented 10,000 cycles CL=30pF F=20 50MHz 10,000 cycles CL=30pF F=20 50MHz -200 -400 60.00 (30) 60.00 (30) 40.0 49.1 20.00 (50) 16.11 (90) +400 UNITS (MHz) (MHz)
Notes: Guaranteed design characterization. subject 100% test. input threshold voltage VDD/2 parameters expected with loaded outputs
ICS9112-06/07
Application Suggestion:
ICS9112 mixed analog/digital product. analog portion very sensitive random noise generated charging discharging internal external capacitor power supply pins. This type noise will cause excess jitter outputs ICS9112. Below recommended alleviate addition noise. Figure below depicts only ICS911207, similar techniques could used dash additional information layout, please refer AN07. capacitors should connected close possible power pins 13). Isolated power plane with capacitor ground will enhance power line stability.
ICS9112-06/07
SOIC Package
16-Pin SOIC Package
Ordering Information
ICS9112M-06 ICS9112M-07
Example:
XXXX
Pattern Number digit number parts with code patterns) Package Type M=SOIC Device Type (consists digit numbers) Prefix ICS, Standard Device
reserves right make changes device data identified this publication without further notice. advises customers obtain latest version device data verify that information being relied upon customer current accurate.

Skew Output Buffer ICS9112 high performance, skew, jitter clock d

Top Searches for this datasheet

Other recent searches