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74HC74 74HCT74 Dual D-type flip-flop with set and reset positive-edge trigger

Product specification Supersedes data of 1998 Feb 23 2003 Jul 10

INTEGRATED CIRCUITS
DATA SHEET
74HC74 74HCT74 Dual D-type flip-flop with set and reset positive-edge trigger
Product specification Supersedes data of 1998 Feb 23 2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
FEATURES · Wide supply voltage range from 2.0 to 6.0 V · Symmetrical output impedance · High noise immunity · Low power dissipation · Balanced propagation delays · ESD protection: HBM EIA / JESD22-A114-A exceeds 2000 V MM EIA / JESD22-A115-A exceeds 200 V.
74HC74 74HCT74
GENERAL DESCRIPTION The 74HC / HCT74 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC / HCT74 are dual positive-edge triggered, D-type flip-flops with individual data (D) inputs, clock (CP) inputs, set (SD) and reset (RD) inputs also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
OUTPUT Qn+1 L H Qn+1 H L
MATERIAL plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic
CODE SOT27-1 SOT27-1 SOT108-1 SOT108-1 SOT337-1 SOT337-1 SOT402-1 SOT402-1 SOT762-1 SOT762-1
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SYMBOL 1RD 1D 1CP 1SD 1Q 1Q GND 2Q 2Q 2SD 2CP 2D 2RD VCC data input clock input (LOW-to-HIGH, edge-triggered) asynchronous set-direct input (active LOW) true flip-flop output complement flip-flop output ground (0 V) complement flip-flop output true flip-flop output asynchronous set-direct input (active LOW) clock input (LOW-to-HIGH, edge-triggered) data input asynchronous reset-direct input (active LOW) positive supply voltage DESCRIPTION asynchronous reset-direct input (active LOW)
74HC74 74HCT74
handbook, halfpage handbook, halfpage
VCC 14 13 12 2RD 2D 2CP 2SD 2Q
1RD 1D 1CP 1SD 1Q 1Q GND
MNA417
14 VCC 13 2RD 12 2D
1D 1CP 1SD 1Q
11 2CP 10 2SD
GND(1)
MNB038
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig.1
Pin configuration DIP14, SO14 and (T)SSOP14.
Fig.2 Pin configuration DHVQFN14.
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
handbook, halfpage
MNA418
handbook, halfpage
MNA419
Fig.3 Logic symbol.
Fig.4 IEC logic symbol.
handbook, halfpage
1D 1CP
2D 2CP
MNA420
Fig.5 Functional diagram.
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
handbook, full pagewidth
MNA421
Fig.6 Logic diagram (one flip-flop).
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
74HCT74 UNIT MIN. 4.5 0 0 -40 - - - TYP. 5.0 - - +25 - 6.0 - MAX. 5.5 VCC VCC +125 500 500 500 V V V °C ns ns ns
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
additional quiescent supply current per input
74HC74 74HCT74
MIN. VCC (V)
4.5 to 5.5
4.5 to 5.5 -
additional quiescent supply current per input
4.5 to 5.5
4.5 to 5.5 -
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
ns ns ns ns ns ns ns ns ns MHz
clock pulse width HIGH see Fig.7 or LOW set or reset pulse width see Fig.8 LOW
trem tsu th fmax
removal time set or reset set-up time nD to nCP hold time nCP to nD maximum clock pulse frequency
see Fig.8 see Fig.7 see Fig.7 see Fig.7
clock pulse width HIGH see Fig.7 or LOW set or reset pulse width see Fig.8 LOW
trem tsu th fmax
removal time set or reset set-up time nD to nCP hold time nCP to nD maximum clock pulse frequency
see Fig.8 see Fig.7 see Fig.7 see Fig.7
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
AC WAVEFORMS
74HC74 74HCT74
handbook, full pagewidth
VI nD input GND th t su 1 / fmax VI nCP input GND tW t PHL VOH nQ output VOL VOH nQ output VOL t PLH t PHL VM
MNA422
Fig.7
The clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse frequency.
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
handbook, full pagewidth
VI nCP input GND t rem VI nSD input GND tW VI nRD input GND t PLH VOH nQ output VOL VOH nQ output VOL t PHL t PLH VM
MNA423
Fig.8
The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths and the nRD, nRD to nCP removal time.
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL
MNA183
VCC open GND
TEST tPZH tPZL tPHZ tPLZ VCC
S1 GND GND VCC
Fig.9 Load circuitry for switching times.
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
PACKAGE OUTLINES DIP14: plastic dual in-line package 14 leads (300 mil)
74HC74 74HCT74
SOT27-1
D seating plane
pin 1 index E
5 scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT27-1 REFERENCES IEC 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.13 0.068 0.044 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 2.2 0.087
ISSUE DATE 99-12-27 03-02-13
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
SO14: plastic small outline package 14 leads body width 3.9 mm
SOT108-1
2.5 scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 8.75 8.55 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 0.028 0.024 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
inches 0.069
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
SSOP14: plastic shrink small outline package 14 leads body width 5.3 mm
SOT337-1
2.5 scale
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.4 0.9 8 0o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT337-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
TSSOP14: plastic thin shrink small outline package 14 leads body width 4.4 mm
SOT402-1
w M detail X
2.5 scale
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.72 0.38 8 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
74HC74 74HCT74
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package no leads SOT762-1 14 terminals body 2.5 x 3 x 0.85 mm
terminal 1 index area
detail X
terminal 1 index area e 2 L
9 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.1 2.9 Dh 1.65 1.35 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT762-1 REFERENCES IEC -JEDEC MO-241 JEITA -EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
2003 Jul 10
Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset positive-edge trigger
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
74HC74 74HCT74
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product / Process Change Notification (CPCN).
Preliminary data Qualification
Product data
Production
2003 Jul 10
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508 / 03 / pp22
Date of release: 2003
Jul 10
Document order number: