74HC74; 74HCT74 Dual D-type flip-flop with reset; positive-edge trigge

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74HC74; 74HCT74 Dual D-type flip-flop with reset; positive-edge trigge

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74HC74; 74HCT74 Dual D-type flip-flop with reset; positive-edge trigger
Product specification Supersedes data 1998 2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
FEATURES Wide supply voltage range from Symmetrical output impedance High noise immunity power dissipation Balanced propagation delays protection: EIA/JESD22-A114-A exceeds 2000 EIA/JESD22-A115-A exceeds
74HC74; 74HCT74
GENERAL DESCRIPTION 74HC/HCT74 high-speed Si-gate CMOS device compatible with power Schottky (LSTTL). They specified compliance with JEDEC standard 74HC/HCT74 dual positive-edge triggered, D-type flip-flops with individual data inputs, clock (CP) inputs, (SD) reset (RD) inputs; also complementary outputs. reset asynchronous active inputs operate independently clock input. Information data input transferred output LOW-to-HIGH transition clock pulse. inputs must stable set-up time prior LOW-to-HIGH clock transition predictable operation. Schmitt-trigger action clock input makes circuit highly tolerant slower clock rise fall times.
QUICK REFERENCE DATA Tamb TYPICAL SYMBOL tPHL/tPLH PARAMETER propagation delay fmax Notes used determine dynamic power dissipation µW). VCC2 VCC2 where: input frequency MHz; output frequency MHz; output load capacitance supply voltage Volts; total load switching outputs; VCC2 outputs. 74HC74 condition VCC. 74HCT74 condition maximum clock frequency input capacitance power dissipation capacitance flip-flop notes CONDITIONS UNIT
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
FUNCTION TABLES Table note INPUT Table note INPUT Note HIGH voltage level; voltage level; don't care; LOW-to-HIGH transition; Qn+1 state after next LOW-to-HIGH transition. ORDERING INFORMATION PACKAGE TYPE NUMBER 74HC74N 74HCT74N 74HC74D 74HCT74D 74HC74DB 74HCT74DB 74HC74PW 74HCT74PW 74HC74BQ 74HCT74BQ TEMPERATURE RANGE +125 +125 +125 +125 +125 +125 +125 +125 +125 +125 PINS PACKAGE DIP14 DIP14 SO14 SO14 SSOP14 SSOP14 TSSOP14 TSSOP14 DHVQFN14 DHVQFN14
74HC74; 74HCT74
OUTPUT
OUTPUT Qn+1 Qn+1
MATERIAL plastic plastic plastic plastic plastic plastic plastic plastic plastic plastic
CODE SOT27-1 SOT27-1 SOT108-1 SOT108-1 SOT337-1 SOT337-1 SOT402-1 SOT402-1 SOT762-1 SOT762-1
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
PINNING SYMBOL data input clock input (LOW-to-HIGH, edge-triggered) asynchronous set-direct input (active LOW) true flip-flop output complement flip-flop output ground complement flip-flop output true flip-flop output asynchronous set-direct input (active LOW) clock input (LOW-to-HIGH, edge-triggered) data input asynchronous reset-direct input (active LOW) positive supply voltage DESCRIPTION asynchronous reset-direct input (active LOW)
74HC74; 74HCT74
handbook, halfpage handbook, halfpage
MNA417
view
GND(1)
MNB038
substrate attached this using conductive attach material. used supply input.
Fig.1
configuration DIP14, SO14 (T)SSOP14.
Fig.2 configuration DHVQFN14.
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
74HC74; 74HCT74
handbook, halfpage
MNA418
handbook, halfpage
MNA419
Fig.3 Logic symbol.
Fig.4 logic symbol.
handbook, halfpage
MNA420
Fig.5 Functional diagram.
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
74HC74; 74HCT74
handbook, full pagewidth
MNA421
Fig.6 Logic diagram (one flip-flop).
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
RECOMMENDED OPERATING CONDITIONS 74HC74 SYMBOL Tamb PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise fall times CONDITIONS MIN. TYP. MAX. +125 1000
74HC74; 74HCT74
74HCT74 UNIT MIN. TYP. MAX. +125
LIMITING VALUES accordance with Absolute Maximum Rating System (IEC 60134); voltages referenced (ground SYMBOL ICC, IGND Tstg Ptot Notes input output voltage ratings exceeded input output current ratings observed. SO14 packages: above derate linearly with mW/K. SSOP14 TSSOP14 packages: above derate linearly with mW/K. DHVQFN14 packages: above derate linearly with mW/K. DIP14 packages: above derate linearly with mW/K. PARAMETER supply voltage input diode current output diode current output source sink current current storage temperature power dissipation Tamb +125 note -0.5 note -0.5 note CONDITIONS MIN. -0.5 MAX. +7.0 ±100 +150 UNIT
-0.5 note
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
CHARACTERISTICS Family 74HC recommended operating conditions; voltages referenced (ground TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb note HIGH-level input voltage LOW-level input voltage HIGH-level output voltage -4.0 -5.2 LOW-level output voltage input leakage current quiescent supply current GND; 3.84 5.34 3.15 MIN.
74HC74; 74HCT74
TYP.
MAX.
UNIT
4.32 5.81 0.15 0.16
1.35 0.33 0.33 ±1.0
Tamb +125 HIGH-level input voltage LOW-level input voltage HIGH-level output voltage -4.0 -5.2 LOW-level output voltage Note typical values measured Tamb input leakage current quiescent supply current GND; ±1.0 3.15 1.35
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
Family 74HCT recommended operating conditions; voltages referenced (ground TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb note HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current quiescent supply current
additional quiescent supply current input
74HC74; 74HCT74
MIN.
TYP.
MAX.
UNIT
4.32 0.15
±1.0
VIL; -4.0 VIL; GND; -2.1 other inputs GND; 3.84 0.33
Tamb +125 HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage input leakage current quiescent supply current
additional quiescent supply current input
±1.0
VIL; -4.0 VIL; GND; -2.1 other inputs GND;
Note typical values measured Tamb Remark types value additional quiescent supply current (ICC) unit load given here. determine input, multiply this value unit load coefficient shown table. INPUT UNIT LOAD COEFFICIENT 0.70 0.70 0.80 0.80
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
CHARACTERISTICS Family 74HC TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb tPHL/tPLH propagation delay Fig.7 propagation delay Fig.8 propagation delay Fig.8 tTHL/tTLH output transition time Fig.7 clock pulse width HIGH Fig.7 reset pulse width Fig.8 trem removal time reset Fig.8 set-up time Fig.7 hold time Fig.7 fmax maximum clock pulse frequency Fig.7 MIN.
74HC74; 74HCT74
TYP.
MAX.
UNIT
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb +125 tPHL/tPLH propagation delay Fig.7 propagation delay Fig.8 propagation delay Fig.8 tTHL/tTLH output transition time Fig.7 clock pulse width HIGH Fig.7 reset pulse width Fig.8 trem removal time reset Fig.8 set-up time Fig.7 hold time Fig.7 fmax maximum clock pulse frequency Fig.7 MIN.
74HC74; 74HCT74
TYP.
MAX.
UNIT
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
Family 74HCT TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb tPHL/tPLH propagation delay propagation delay propagation delay tTHL/tTLH output transition time Fig.7 Fig.8 Fig.8 Fig.7 MIN.
74HC74; 74HCT74
TYP.
MAX.
UNIT
clock pulse width HIGH Fig.7 reset pulse width Fig.8
trem fmax
removal time reset set-up time hold time maximum clock pulse frequency
Fig.8 Fig.7 Fig.7 Fig.7
Tamb +125 tPHL/tPLH propagation delay propagation delay propagation delay tTHL/tTLH output transition time Fig.7 Fig.8 Fig.8 Fig.7
clock pulse width HIGH Fig.7 reset pulse width Fig.8
trem fmax
removal time reset set-up time hold time maximum clock pulse frequency
Fig.8 Fig.7 Fig.7 Fig.7
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
WAVEFORMS
74HC74; 74HCT74
handbook, full pagewidth
input 1/fmax input output output
MNA422
shaded areas indicate when input permitted change predictable output performance. 74HC74: 50%; VCC. 74HCT74:
Fig.7
clock (nCP) output (nQ, propagation delays, clock pulse width, set-up, hold times, output transition times maximum clock pulse frequency.
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
74HC74; 74HCT74
handbook, full pagewidth
input input input output output
MNA423
74HC74: 50%; VCC. 74HCT74:
Fig.8
(nSD) reset (nRD) input output (nQ, propagation delays, reset pulse widths nRD, removal time.
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
74HC74; 74HCT74
handbook, full pagewidth
PULSE GENERATOR D.U.T.
MNA183
open
TEST tPZH tPZL tPHZ tPLZ
Definitions test circuit: Load resistor. Load capacitance including probe capacitance. Termination resistance should equal output impedance pulse generator.
Fig.9 Load circuitry switching times.
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
PACKAGE OUTLINES DIP14: plastic dual in-line package; leads (300 mil)
74HC74; 74HCT74
SOT27-1
seating plane
index
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT inches Note Plastic metal protrusions 0.25 (0.01 inch) maximum side included. OUTLINE VERSION SOT27-1 REFERENCES 050G04 JEDEC MO-001 JEITA SC-501-14 EUROPEAN PROJECTION max. 0.17 min. 0.51 0.02 max. 0.13 1.73 1.13 0.068 0.044 0.53 0.38 0.021 0.015 0.36 0.23 0.014 0.009 19.50 18.55 0.77 0.73 6.48 6.20 0.26 0.24 2.54 7.62 3.60 3.05 0.14 0.12 8.25 7.80 0.32 0.31 10.0 0.39 0.33 0.254 0.01 max. 0.087
ISSUE DATE 99-12-27 03-02-13
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
74HC74; 74HCT74
SO14: plastic small outline package; leads; body width
SOT108-1
index detail
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT max. 1.75 0.25 0.10 1.45 1.25 0.25 0.01 0.49 0.36 0.25 0.19 8.75 8.55 0.16 0.15 1.27 0.05 1.05 0.028 0.024 0.25 0.01 0.25 0.01 0.004 0.028 0.012
inches 0.069
0.010 0.057 0.004 0.049
0.019 0.0100 0.35 0.014 0.0075 0.34
0.244 0.039 0.041 0.228 0.016
Note Plastic metal protrusions 0.15 (0.006 inch) maximum side included. OUTLINE VERSION SOT108-1 REFERENCES 076E06 JEDEC MS-012 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
74HC74; 74HCT74
SSOP14: plastic shrink small outline package; leads; body width
SOT337-1
index detail
scale
DIMENSIONS original dimensions) UNIT max. 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 0.65 1.25 1.03 0.63 0.13
Note Plastic metal protrusions 0.25 maximum side included. OUTLINE VERSION SOT337-1 REFERENCES JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
74HC74; 74HCT74
TSSOP14: plastic thin shrink small outline package; leads; body width
SOT402-1
index
detail
scale
DIMENSIONS original dimensions) UNIT max. 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13 0.72 0.38
Notes Plastic metal protrusions 0.15 maximum side included. Plastic interlead protrusions 0.25 maximum side included. OUTLINE VERSION SOT402-1 REFERENCES JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
74HC74; 74HCT74
DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; leads; SOT762-1 terminals; body 0.85
terminal index area
detail
terminal index area
scale
DIMENSIONS original dimensions) UNIT A(1) max. 0.05 0.00 0.30 0.18 1.65 1.35 1.15 0.85 0.05 0.05
Note Plastic metal protrusions 0.075 maximum side included. OUTLINE VERSION SOT762-1 REFERENCES -JEDEC MO-241 JEITA -EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
2003
Philips Semiconductors
Product specification
Dual D-type flip-flop with reset; positive-edge trigger
DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
74HC74; 74HCT74
DEFINITION This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Relevant changes will communicated Customer Product/Process Change Notification (CPCN).
Preliminary data Qualification
Product data
Production
Notes Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet data sheets describing multiple type numbers, highest-level product status determines data sheet status. DEFINITIONS Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification. DISCLAIMERS Life support applications These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes products including circuits, standard cells, and/or software described contained herein order improve design and/or performance. When product full production (status `Production'), relevant changes will communicated Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes responsibility liability these products, conveys licence title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
2003
Philips Semiconductors worldwide company
Contact information additional information please visit Fax: 24825 sales offices addresses send e-mail
Koninklijke Philips Electronics N.V. 2003
SCA75
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights.
Printed Netherlands
613508/03/pp22
Date release: 2003
Document order number:
9397 11259

74HC74; 74HCT74 Dual D-type flip-flop with reset; positive-edge trigge

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