Features High Capacity Single-Chip ASIC Alternative Automotive Ap

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40MX 42MX Automotive FPGA Families
Features High Capacity
Single-Chip ASIC Alternative Automotive Applications 3,000 54,000 System Gates kbits Configurable Dual-Port SRAM Fast Wide-Decode Circuitry User-Programmable Pins
Ease Integration
100% Resource Utilization 100% Locking Deterministic, User-Controllable Timing Unique In-System Diagnostic Verification Capability with Silicon Explorer Power Consumption IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
Product Profile
Device Capacity System Gates SRAM Bits Logic Modules Sequential Combinatorial Decode SRAM Modules (64x4 32x8) Dedicated Flip-Flops Maximum Flip-Flops Clocks Maximum User I/Os Boundary Scan Test (BST) Packages count) PLCC PQFP VQFP TQFP A40MX02 3,000 A40MX04 6,000 A42MX09 14,000 100, A42MX16 24,000 A42MX24 36,000 1,410 160, A42MX36 54,000 2,560 1,230 1,184 1,230 1,822 208,
Note: While automotive-grade devices offered standard speed grade only, family also offered commercial, industrial military temperature grades with Std, speed grades. Refer 40MX 42MX Family FPGAs datasheet more details.
2006 2006 Actel Corporation
Actel website (www.actel.com) latest version this datasheet.
40MX 42MX Automotive FPGA Families
Ordering Information
A42MX16
Application (Temperature Range) Automotive (-40 +125°C) Package Lead Count Package Type Plastic Leaded Chip Carrier Plastic Quad Flat Pack Thin Quad Flat Pack (1.4 Very Thin Quad Flat Pack (1.0 Speed Grade (Blank Standard) Part Number A40MX02 3,000 System Gates A40MX04 6,000 System Gates A42MX09 14,000 System Gates A42MX16 24,000 System Gates A42MX24 36,000 System Gates A42MX36 54,000 System Gates Note: Automotive grade parts grade) devices tested room temperature specifications that have been guard banded based characterization across recommended operating conditions. A-grade parts tested extended temperatures. testing ensure guaranteed operation extended temperatures required, please contact your local Actel Sales office discuss testing options available.
Plastic Device Resources
Device A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 PLCC 68-Pin PLCC 84-Pin PQFP 100-Pin PQFP 160-Pin User I/Os PQFP 208-Pin PQFP 240-Pin VQFP 80-Pin VQFP 100-Pin TQFP 176-Pin
Note: Package Definitions PLCC Plastic Leaded Chip Carrier, PQFP Plastic Quad Flat Pack, TQFP Thin Quad Flat Pack, VQFP Very Thin Quad Flat Pack
Speed Grade Temperature Grade Matrix
Note: Refer 40MX 42MX Family FPGAs datasheet details commercial-, industrial- military-grade offerings.
Contact your local Actel representative device availability.
40MX 42MX Automotive FPGA Families
Table Contents
40MX 42MX Automotive FPGA Families
General Description Architectural Overview Other Architectural Features Development Tool Support 1-11 Related Documents 1-11 5.0V Operating Conditions 1-12 Power Dissipation 1-13 Junction Temperature 1-15 Package Thermal Characteristics 1-15 Timing Information 1-16 Parameter Measurement 1-19 Sequential Timing Characteristics 1-20 Decode Module Timing 1-22 Dual-Port SRAM Timing Waveforms 1-23 Predictable Performance: Tight Delay Distributions 1-25 Temperature Voltage Derating Factors 1-26 Timing Characteristics 1-28 Descriptions 1-45
Package Assignments
68-Pin PLCC 84-Pin PLCC 100-Pin PQFP 160-Pin PQFP 80-Pin VQFP 2-11 208-Pin PQFP 2-13 240-Pin PQFP 2-17 100-Pin VQFP 2-20 176-Pin TQFP 2-23
Datasheet Information
List Changes Datasheet Categories
40MX 42MX Automotive FPGA Families
40MX 42MX Automotive FPGA Families
General Description
Actels' automotive-grade families provide highperformance, single-chip solution shortening system design development cycle, offering costeffective alternative ASICs in-cabin telematics automobile interconnect applications. 40MX 42MX devices excellent choices integrating logic that currently implemented multiple PALs, CPLDs, FPGAs. device architecture based Actel's patented antifuse technology implemented 0.45µm triplemetal CMOS process. With capacities ranging from 3,000 54,000 system gates, devices live power-up have one-fifth standby power consumption comparable FPGAs. Actel's FPGAs provide user I/Os available wide variety packages speed grades. automotive-grade 42MX24 42MX36 include system-level features such IEEE Standard 1149.1 (JTAG) Boundary Scan Testing fast wide-decode modules. addition, A42MX36 device offers dual-port SRAM implementing fast FIFOs, LIFOs, temporary data storage. storage elements efficiently address applications requiring wide datapath manipulation. flops constructed from logic modules whenever required application. 42MX devices contain three types logic modules: combinatorial (C-modules), sequential (S-modules) decode (D-modules). Figure illustrates combinatorial logic module. S-module, shown Figure page 1-2, implements same combinatorial logic function C-module while adding sequential element. sequential element configured either D-flip-flop transparent latch. S-module register bypassed that implements purely combinatorial logic. A42MX24 A42MX36 devices contain D-modules, which arranged around periphery device. D-modules contain wide-decode circuitry, providing fast, wide-input function similar that found CPLD architectures (Figure page 1-2). Dmodule allows A42MX24 A42MX36 devices perform wide-decode functions speeds comparable CPLDs PALs. output D-module programmable inverter active HIGH assertion. D-module output hardwired output pin, also back into array incorporated into other logic.
Architectural Overview
devices composed fine-grained building blocks that enable fast, efficient logic designs. devices within these families composed logic modules, modules, routing resources clock networks, which building blocks fast logic designs. addition, A42MX36 device contains embedded dual-port SRAM modules, which optimized high-speed datapath functions such FIFOs, LIFOs scratchpad memory. A42MX24 A42MX36 also contain widedecode modules.
Figure 40MX Logic Module
Logic Modules
40MX logic module eight-input, one-output logic circuit designed implement wide range logic functions with efficient interconnect routing resources (Figure 1-1). logic module implement four basic logic functions (NAND, AND, NOR) gates two, three, four inputs. logic module also implement variety D-latches, exclusivity functions, AND-ORs OR-ANDs. dedicated hardwired latches flip-flops required array; latches flip
Figure 42MX C-Module Implementation
40MX 42MX Automotive FPGA Families
GATE
7-Input Function Plus D-Type Flip-Flop with Clear
7-Input Function Plus Latch
GATE
4-Input Function Plus Latch with Clear
8-Input Function (Same C-Module)
Figure 42MX S-Module Implementation
Inputs Hard-Wire Programmable Inverter Feedback Array
Figure A42MX24 A42MX36 D-Module Implementation
Dual-Port SRAM Modules
A42MX36 device contains dual-port SRAM modules, which arranged 256-bit blocks configured 32x8 64x4. SRAM modules cascaded together form memory spaces userdefinable width depth. block diagram A42MX36 dual-port SRAM block shown Figure page 1-3. A42MX36 SRAM modules true dual-port structures containing independent read write ports. Each SRAM module contains bits read write addressing (RDAD[5:0] WRAD[5:0], respectively) 64x4-bit blocks. When configured byte mode, highest order address bits (RDAD5 WRAD5) used. read write ports SRAM block contain independent clocks (RCLK WCLK) with programmable polarities offering active HIGH implementation. SRAM block contains eight data inputs (WD[7:0]) eight outputs (RD[7:0]), which connected segmented vertical routing tracks. A42MX36 dual-port SRAM blocks provide optimal solution high-speed buffered applications requiring FIFO LIFO queues. ACTgen Macro Builder within Actel's Designer software provides capability quickly design memory functions with SRAM blocks.
40MX 42MX Automotive FPGA Families
WD[7:0]
Latches [7:0]
WRAD[5:0]
[5:0] Latches
Write Port Logic
SRAM Module (256 Bits)
[5:0] Read Port Logic
Latches Read Logic
RDAD[5:0]
RCLK
MODE BLKEN WCLK
Write Logic
RD[7:0]
Routing Tracks
Figure A42MX36 Dual-Port SRAM Block
Routing Structure
architecture uses vertical horizontal routing tracks interconnect various logic modules. These routing tracks metal interconnects that continuous split into segments. Varying segment lengths allow interconnect over design tracks occur with only antifuse connections. Segments joined together ends using antifuses increase their lengths full length track. interconnects accomplished with maximum four antifuses.
above below), except near bottom array, where edge effects occur. Long vertical tracks contain either segments. example vertical routing tracks segments shown Figure 1-6.
Segmented Horizontal Routing
Logic Modules
Horizontal Routing
Horizontal routing tracks span whole length divided into multiple segments located between rows modules. segment that spans more than one-third length considered long horizontal segment. typical channel shown Figure 1-6. Within horizontal routing, dedicated routing tracks used global clock networks power ground tie-off tracks. Non-dedicated tracks used signal nets.
Antifuses
Vertical Routing Tracks
Figure Routing Structure
Antifuse Structures
antifuse "normally open" structure. antifuses implement programmable logic device results highly testable structures well efficient programming algorithms. There pre-existing connections; temporary connections made using pass transistors. These temporary connections isolate individual antifuses programmed individual circuit structures tested, which done before after programming. instance, metal tracks tested continuity shorts between adjacent tracks, functionality logic modules verified.
Vertical Routing
Another routing tracks vertically through module. There three types vertical tracks: input, output, long. Long tracks span column length module, divided into multiple segments. Each segment input track dedicated input particular module; each segment output track dedicated output particular module. Long segments uncommitted assigned during routing. Each output segment spans four channels (two
40MX 42MX Automotive FPGA Families
Clock Networks
40MX devices have global clock distribution network (CLK). signal network being routed through CLKBUF buffer. 42MX devices, there low-skew, high-fanout clock distribution networks, referred CLKA CLKB. Each network clock module (CLKMOD) that select source clock signal from following (Figure 1-7): Externally from CLKA pad, using CLKBUF buffer Externally from CLKB pad, using CLKBUF buffer Internally from CLKINTA input, using CLKINT buffer
CLKB CLKA From Pads
Internally from CLKINTB input, using CLKINT buffer
clock modules located modules. Clock drivers dedicated horizontal clock track located each horizontal routing channel. Clock input pads both 40MX 42MX devices also used normal I/Os, bypassing clock networks. A42MX36 device four additional register control resources, called quadrant clock networks (Figure 1-8). Each quadrant clock provides local, high-fanout resource contiguous logic modules within quadrant device. Quadrant clock signals originate from specific pins from internal array used secondary register clock, register clear, output enable.
CLKINB CLKINA
CLKMOD
Internal Signal CLKO(17)
Clock Drivers
CLKO(16) CLKO(15)
CLKO(2) CLKO(1)
Clock Tracks
Figure Clock Networks 42MX Devices
QCLKA Quad Clock Modul QCLK1 QCLK3 Quad Clock Modul QCLKC QCLKD *QCLK3IN
QCLKB *QCLK1IN
Quad Clock Modul *QCLK2IN
QCLK2
QCLK4
Quad Clock Modul *QCLK4IN
Note: *QCLK1IN, QCLK2IN, QCLK3IN, QCLK4IN internally-generated signals. Figure Quadrant Clock Network A42MX36 Devices
40MX 42MX Automotive FPGA Families
Modules
modules provide interface between device pins logic array. Figure block diagram 42MX module. variety user functions, determined library macro selection, implemented module. (Refer Antifuse Macro Library Guide more information.) 42MX modules contain tristate buffers, with input output latches that configured input, output, bidirectional operation. 42MX devices contain flexible structures, where each output dedicated output-enable control (Figure 1-9). module used latch input output data, both, providing fast setup time. addition, Actel Designer software tools build Dtype flip-flop using C-module combined with module register input output signals. Refer Antifuse Macro Library Guide more details. Actel's Designer software development tools provide design library macro functions that implement configurations supported FPGAs.
there Security Fuse which, when programmed, both disables probing circuitry prohibits further programming device. Look this symbol ensure your valuable secure.
Figure 1-10 Fuselock
more information, refer Actel's Implementation Security Actel Antifuse FPGAs application note.
Programming
Device programming supported through Silicon Sculptor series programmers. Silicon Sculptor compact, robust, single-site multi-site device programmer With standalone software, Silicon Sculptor designed allow concurrent programming multiple units from same Silicon Sculptor programs devices independently achieve fastest programming times possible. After being programmed, each fuse verified insure that been programmed correctly. Furthermore, programming, there integrity tests that ensure extra fuses have been programmed. only does test fuses (both programmed nonprogrammed), Silicon Sculptor also allows self-test verify hardware extensively. procedure programming device using Silicon Sculptor follows: Load .AFM file Select device programmed Begin programming When design ready production, Actel offers device volume-programming services either through distribution partners In-House Programming from factory. more details programming devices, please refer Programming Antifuse Devices Silicon Sculptor user's guides.
From Array
G/CLK* Array
G/CLK*
Note: *Can configured Latch Flip-Flop (Using C-Module) Figure 42MX Module
Other Architectural Features
User Security
Actel FuseLock provides robust security against design theft. Special security fuses hidden fabric device prevent unauthorized users from accessing programming and/or probe interfaces. virtually impossible identify bypass these fuses without damaging device, making Actel antifuse FPGAs immune both invasive noninvasive attacks. Special security fuses 40MX devices include Probe Fuse Program Fuse. former disables probing circuitry while latter prohibits further programming fuses, including Probe Fuse. 42MX devices,
40MX 42MX Automotive FPGA Families
Power Supply
Automotive devices designed operate 5.0V environments. Table describes voltage settings automotive devices.
Table Voltage Support Automotive-Grade Devices Device 40MX 42MX 5.0V VCCA 5.0V VCCI 5.0V Maximum Input Tolerance 5.25V 5.25V Nominal Output Voltage 5.0V 5.0V
Power-Up/Down
When powering devices, VCCA must greater than equal VCCI throughout power-up sequence. VCCI exceeds VCCA during power-up, either input protection junction I/Os will forwardbiased I/Os will logical High, rises high levels. During power-down, VCCA must smaller than equal VCCI.
Silicon Explorer used control MODE, DCLK, pins devices select desired nets debugging. user simply assigns selected internal nets Silicon Explorer software PRA/PRB output pins observation. Probing functionality activated when MODE held HIGH. Figure 1-11 page illustrates interconnection between Silicon Explorer 40MX devices, while Figure 1-12 page illustrates interconnection between Silicon Explorer 42MX devices allow probing capabilities, security fuses must programmed. (Refer "User Security" section page security fuses 40MX 42MX devices). Table page summarizes possible device configurations probing. pins dual-purpose pins. When "Reserve Probe Pin" checked Designer software, pins reserved dedicated outputs probing. pins required user I/Os achieve successful layout "Reserve Probe Pin" checked, layout tool will override option place user I/Os pins.
Test Circuitry Silicon Explorer Probe
devices contain probing circuitry that provides builtin access every node design, Silicon Explorer Silicon Explorer integrated hardware software solution that, conjunction with Designer software, allow users examine internal nodes device while operating prototyping production system. user probe device without changing placement routing design without using additional resources. Silicon Explorer II's noninvasive method does alter timing loading effects, thus shortening debug cycle providing true representation device under actual functional situations. Silicon Explorer samples data (asynchronous) (synchronous). Silicon Explorer attaches PC's standard serial port, turning into fully functional 18-channel logic analyzer. Silicon Explorer allows designers complete design verification process their desks reduces verification time from several hours cycle seconds.
40MX 42MX Automotive FPGA Families
Logic Analyzer Channels
Serial Connection Windows
40MX Silicon Explorer MODE DCLK
Figure 1-11 Silicon Explorer Setup with 40MX
Logic Analyzer Channels
Serial Connection Windows
42MX Silicon Explorer MODE DCLK
Figure 1-12 Silicon Explorer Setup with 42MX Table Device Configuration Options Probe Capability Security Fuse(s) Programmed Notes: Avoid using SDI, SDO, DCLK, PRA, pins input bidirectional ports. Since these pins active during probing, input signals will pass through these pins cause contention. user signal assigned these pins, they will behave unused I/Os this mode. "Pin Descriptions" section page 1-45 information unused pins. MODE HIGH PRA, PRB1 User I/Os2 Probe Circuit Outputs Probe Circuit Secured SDI, SDO, DCLK1 User I/Os2 Probe Circuit Inputs Probe Circuit Secured
40MX 42MX Automotive FPGA Families
Design Consideration
recommended series termination resistor every probe connector (SDI, SDO, MODE, DCLK, PRB). series termination used prevent data transmission corruption during probing reading back checksum.
controller four-bit state machine. '1's '0's represent values that must present rising edge given state transition occur. indicate that instruction register data register operating that state. controller receives control inputs (TMS TCK) generates control clock signals rest test logic architecture. power-up, controller enters Test-Logic-Reset state. guarantee reset controller from possible states, must remain high five cycles. Automotive-grade 42MX24 42MX36 devices support three types test data registers: bypass, device identification, boundary scan. bypass register selected when other register needs accessed device. This speeds test data transfer other devices test data path. 32-bit device identification register shift register with four fields (lowest significant byte (LSB), number, part number version). boundary-scan register observes controls state each pin. Each cell three boundary-scan register cells, each with serial-in, serial-out, parallel-in, parallel-out pin. serial pins used serially connect boundary-scan register cells device into boundaryscan register chain, which starts ends pin. parallel ports connected internal core logic tile input, output control ports buffer capture load data into register control observe logic state each I/O.
IEEE Standard 1149.1 Boundary Scan Test (BST) Circuitry
Automotive-grade 42MX24 42MX36 devices compatible with IEEE Standard 1149.1 (informally known Joint Testing Action Group Standard JTAG), which defines hardware architecture mechanisms cost-effective, board-level testing. basic boundary-scan logic circuit composed (test access port), controller, test data registers instruction register (Figure 1-13). This circuit supports mandatory IEEE 1149.1 instructions (EXTEST, SAMPLE/ PRELOAD BYPASS) some optional instructions. Table page describes ports that control JTAG testing, while Table page describes test instructions supported these devices. Each test section accessed through TAP, which four associated pins: (test clock input), (test data input output), (test mode selector).
Boundary Scan Register Bypass Register Control Logic JTAG JTAG Instruction Register Controller Instruction Decode
Output
Figure 1-13 42MX IEEE 1149.1 Boundary Scan Circuitry
40MX 42MX Automotive FPGA Families
Table Test Access Port Descriptions Port (Test Select) Description Mode Serial input test logic control bits. Data captured rising edge test logic clock (TCK)
(Test Clock Input) Dedicated test logic clock used serially shift test instruction, test data, control inputs rising edge clock, serially shift output data falling edge clock. maximum clock frequency (Test Data Input) (Test Output) Serial input instruction test data. Data captured rising edge test logic clock
Data Serial output test instruction data from test logic. Inactive Drive state (high impedance) when data scanning progress
Table Supported Public Instructions Instruction EXTEST Code [2:0] Instruction Type Mandatory Description Allows external circuitry board-level interconnections tested forcing test pattern output pins capturing test results input pins Allows snapshot signals device pins captured examined during operation Tristates I/Os allow external signals drive pins. Please refer IEEE Standard 1149.1 specification details Allows state signals driven from component pins determined from Boundary-Scan Register. Please refer IEEE Standard 1149.1 specification details Enables bypass register between pins. test data passes through selected device adjacent devices test chain
SAMPLE/PRELOAD HIGH CLAMP
Mandatory Optional Optional
BYPASS
Mandatory
40MX 42MX Automotive FPGA Families
JTAG Mode Activation
JTAG test logic circuit activated Designer software selecting Tools then Device Selection. This brings Device Selection dialog shown Figure 1-14. JTAG test logic circuit enabled clicking "Reserve JTAG Pins" check box. Table explains pins' behavior either mode.
Figure 1-14 Device Selection Wizard Table Boundary Scan Configuration Functionality Reserve JTAG TDI, Checked input; must terminated logical HIGH avoid floating input; float tied HIGH. tied another device output; float connected another device Unchecked User User User
TRST Controller Reset
active reset (TRST) supported; however, devices contain power-on circuitry that resets boundary-scan circuitry upon power-up. Also, equipped with internal pull-up resistor. This allows controller remain return Test-Logic-Reset state when there input when logical pin. reset controller, must HIGH least five cycles.
Boundary Scan Description Language (BSDL) File
Conforming IEEE Standard 1149.1 requires that operation various JTAG components documented. BSDL file provides standard format describe JTAG components that used automatic test equipment software. file includes instructions that supported, instruction-bit pattern, boundary-scan chain order. in-depth discussion BSDL files, please refer Actel BSDL Files Format Description application note. Actel BSDL files grouped into categories- generic device-specific. generic files assign user I/Os inouts. Device-specific files assign user I/Os inputs, outputs, inouts. Generic files devices available Actel's website
40MX 42MX Automotive FPGA Families
Development Tool Support
automotive-grade family FPGAs fully supported both Actel's LiberoIntegrated Design Environment (IDE) Designer FPGA Development software. Actel Libero design management environment, seamlessly integrating design tools while guiding user through design flow, managing design files, passing necessary design data among tools. Libero allows users integrate both schematic synthesis into single flow verify entire design single environment. Libero includes Synplify® Actel from Synplicity®, ViewDraw Actel from Mentor Graphics, ModelSimHDL Simulator from Mentor Graphics®, WaveFormer Litefrom SynaptiCADTM, Designer software from Actel. Refer Libero flow (located Actel's website) diagram more information. Actel's Designer software place-and-route tool provides comprehensive suite backend support tools FPGA development. Designer software includes timing-driven place-and-route, world-class integrated static timing analyzer constraints editor. With Designer software, user select lock package pins while only minimally impacting results place-and-route. Additionally, back-annotation flow compatible with major simulators simulation results cross-probed with Silicon Explorer Actel's integrated verification logic analysis tool. Another tool included Designer software ACTgen macro builder, which easily creates popular commonly used logic functions implementation into your schematic design. Actel's Designer software compatible with most popular FPGA design entry verification tools from companies such Mentor Graphics, Synplicity, Synopsys, Cadence Design Systems. Designer software available both Windows UNIX operating systems.
Related Documents
Application Notes
Actel BSDL Files Format Description Programming Antifuse Devices http://www.actel.com/documents/ AntifuseProgram_AN.pdf Actel's Implementation Security Actel Antifuse FPGAs
User's Guides Manuals
Antifuse Macro Library Guide Silicon Sculptor
Miscellaneous
Libero Flow Diagram
1-11
40MX 42MX Automotive FPGA Families
5.0V Operating Conditions
Absolute Maximum Ratings*
Free Temperature Range
Symbol Parameter Limits -0.5 +6.5 -0.5 +0.5 -0.5 +0.5 +150 Units
Recommended Operating Conditions
Parameter Temperature Range VCCI VCCA Notes: Automotive grade parts grade) devices tested room temperature specifications that have been guard banded based characterization across recommended operating conditions. A-grade parts tested extended temperatures. testing ensure guaranteed operation extended temperatures required, please contact your local Actel Sales office discuss testing options available. Ambient temperature (TA)
Automotive1 +125 4.75 5.25 4.75 5.25 4.75 5.25
Units
VCC/VCCA/VCCI Supply Voltage TSTG Input Voltage Output Voltage Storage Temperature
Note: *Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. Exposure absolute maximum rated conditions extended periods affect device reliability. Devices should operated outside Recommended Operating Conditions.
Electrical Specifications
Automotive Symbol VOH1 VOL1 IIL, ICC2 Notes: Only output tested time. VCC/VCCI min. outputs unloaded. inputs VCC/VCCI GND. Parameter Output High Voltage Output Voltage Input Voltage Input High Voltage Input Leakage Current Tristate Output Leakage Current Input Transition Time Capacitance Standby Current source sink current Conditions (IOH (IOL Min. Max. Units
derived from IBIS model
40MX 42MX Automotive FPGA Families
Power Dissipation
General Power Equation
[ICCstandby ICCactive] VCCI IOL* VOL* (VCCI VOH) where: ICCstandby current flowing when inputs outputs changing. ICCactive current flowing CMOS switching. IOL, sink/source currents. VOL, level output voltages. equals number outputs driving loads VOL. equals number outputs driving loads VOH. Accurate values difficult determine because they depend family type, design details, system I/O. power divided into components: static active.
Active Power Component
Power dissipation CMOS devices usually dominated active (dynamic) power dissipation. This component frequency-dependent function logic external I/O. Active power dissipation results from charging internal chip capacitances interconnect, unprogrammed antifuses, module inputs, module outputs, plus external capacitance board traces load device inputs. additional component active power dissipation totem pole current CMOS transistor pairs. effect associated with equivalent capacitance that combined with frequency voltage represent active power dissipation. power dissipated CMOS circuit expressed equation: Power (µW) VCCA2
where:
Equivalent capacitance picofarads (pF) Power supply volts
expressed
VCCA
Static Power Component
Actel FPGAs have small static power components that result power dissipation lower than PALs CPLDs. integrating multiple PALs/CPLDs into FPGA, even greater reduction board-level power dissipation achieved. power standby current typically small component overall power. static power dissipation loads depends number outputs driving HIGH LOW, load current. Again, this number typically small. instance, 32-bit sinking 0.33V will generate with outputs driving LOW, with outputs driving HIGH. actual dissipation will average somewhere between, I/Os switch states with time.
Switching frequency megahertz (MHz)
Equivalent Capacitance
Equivalent capacitance calculated measuring ICCactive specified frequency voltage each circuit component interest. Measurements have been made over range frequencies fixed value VCC. Equivalent capacitance frequency-independent, results used over wide range operating conditions. Equivalent capacitance values shown following page.
1-13
40MX 42MX Automotive FPGA Families
Values Actel FPGAs
Modules (CEQM)
Input Buffers (CEQI) Output Buffers (CEQO) 18.2
Fixed Capacitance Values FPGAs (pF)
Device Type A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 routed_Clk1 41.4 68.6 routed_Clk2
Routed Array Clock Buffer Loads (CEQCR)
calculate active power dissipated from complete design, switching frequency each part logic must known. equation below shows piece-wise linear summation over components. Power VCCA2 CEQM fm)Modules CEQI fn)Inputs (CEQO fp)outputs CEQCR fq1)routed_Clk1 fq1)routed_Clk1 CEQCR fq2)routed_Clk2 fq2)routed_Clk2
Determining Average Switching Frequency
determine switching frequency design, data input values circuit must clearly understood. following guidelines represent worstcase scenarios; these used generally predict upper limits power dissipation.
Logic Modules Combinatorial Modules Inputs/4 Outputs/4 Sequential Modules Sequential Modules F/10 F/10
where:
CEQM CEQI CEQO Number logic modules switching frequency Number input buffers switching frequency Number output buffers switching frequency Number clock loads first routed array clock
Number clock loads second routed array clock Fixed capacitance first routed array clock Fixed capacitance second routed array clock
Inputs Switching Outputs Switching First Routed Array Clock Loads (q1)
Equivalent capacitance logic modules Equivalent capacitance input buffers Equivalent capacitance output buffers Equivalent capacitance routed array clock Output load capacitance
Second Routed Array Clock Loads (q2) Load Capacitance (CL)
CEQCR
Average Logic Module Switching Rate (fm) Average Input Switching Rate (fn) Average Output Switching Rate (fp)
Average logic module switching rate Average input buffer switching rate Average output buffer switching rate Average first routed array clock rate Average second routed array clock rate
Average First Routed Array Clock Rate (fq1) Average Second Routed Array Clock Rate (fq2)
40MX 42MX Automotive FPGA Families
Junction Temperature
temperature variable Designer software refers junction temperature, ambient temperature. This important distinction because heat generated from dynamic power consumption usually hotter than ambient temperature. used calculate junction temperature. Junction Temperature
Power Junction ambient package. numbers located "Package Thermal Characteristics" section.
Package Thermal Characteristics
device junction-to-case thermal characteristic junction-to-ambient characteristic thermal characteristics shown with different flow rates. Maximum junction temperature 150°C. sample calculation absolute maximum power dissipation allowed PQFP 160-pin package automotive temperature follows:
Where: Ambient Temperature Temperature gradient between junction (silicon) ambient
Max. junction temp. (°C) Max. automotive temp. 150°C 125°C 0.95 (°C/W) 26.2 °C/W
Table Package Thermal Characteristics
Plastic Packages Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Quad Flat Pack Plastic Leaded Chip Carrier Plastic Leaded Chip Carrier Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Very Thin Plastic Quad Flat Pack Count
12.0 10.0 13.0 12.0 11.0 12.0 10.0
Still 27.8 26.2 26.1 25.6 25.0 22.5 24.7 38.2 35.3
ft./min. 23.4 22.8 22.5 22.3 21.0 18.9 19.9 31.9 29.4
ft./min. 21.2 21.1 20.8 20.8 19.4 17.6 18.0 29.4 27.1
Units °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W
1-15
40MX 42MX Automotive FPGA Families
Timing Information
Input Delay Module INYL Internal Delays Predicted Routing Delays Output Delay Module tIRD2 Logic Module IRD1 IRD4 IRD8 10.2 tENHZ 14.1
Array Clock
tCKH
Note: Values shown 40MX worst-case 5.0V automotive conditions. Figure 1-15 40MX Timing Model*
Input Delays Module INYL tIRD1
Internal Delays
Predicted Routing Delays
Output Delays Module
Combinatorial Logic Module tINH tINSU tINGL Sequential Logic Module Combinatorial Logic included tRD4
Module DLH=
tENHZ
Array Clocks
tOUTH 0.00 tOUTSU tGLH
FMAX
(light loads, pad-to-pad)
Notes: *Values shown A42MX09 worst-case 5.0V automotive conditions. Input module predicted routing delay Figure 1-16 42MX Timing Model*
40MX 42MX Automotive FPGA Families
Input Delays Module tINPY IRD1
Internal Delays
Predicted Routing Delays
Output Delays Module
Combinatorial Module tINH tINSU tINGO Decode Module tPDD tRD1 tRD2 tRD4
DLH=
tRDD
Sequential Logic Module Combinatorial Logic included tSUD Quadrant Clocks tCKH tRD1=
Module tDLH
tENHZ
tLSU tGHL
FMAX
Notes: Values shown A42MX36 worst-case 5.0V automotive conditions. Load-dependent Figure 1-17 A42MX36 Timing Model (Logic Functions using Quadrant Clocks)*
1-17
40MX 42MX Automotive FPGA Families
Input Delays Module INPY
IRD1
INSU INGO
Predicted Routing Delays [7:0] WRAD [5:0] BLKEN WCLK tADSU tADH WENSU BENS [7:0] RDAD [5:0] RCLK tADSU tADH tRENSU tRD1
Module tDLH
Array Clocks FMAX
tGHL tLSU
Note: *Values shown A42MX36 worst-case 5.0V automotive conditions. Figure 1-18 A42MX36 Timing Model (SRAM Functions)*
40MX 42MX Automotive FPGA Families
Parameter Measurement
TRIBUFF test loads (shown below)
1.5V 1.5V tDHL tDLH
VCCI 1.5V tENZL tENLZ
1.5V tENHZ tENZH
Figure 1-19 Output Buffer Delays
Load (Used measure propagation delay) output under test
Load (Used measure rising/falling edges) VCCI
output under test
VCCI tPLZ
Figure 1-20 Test Loads
1-19
40MX 42MX Automotive FPGA Families
Sequential Timing Characteristics
INBUF
1.5V 1.5V VCCI INYH
tINYL
tPHL
tPLH
Figure 1-21 Input Buffer Delays
Figure 1-22 Module Delays
(Positive Edge-Triggered) SUENA HENA PRE, WASYN
Note: represents data functions involving multiplexed flip-flops. Figure 1-23 Flip-Flops Latches
WCLKA WCLKI
40MX 42MX Automotive FPGA Families
OBDLHS
tOUTSU tOUTH
Figure 1-25 Output Buffer Latches
DATA
IBDL
DATA tINH tINSU
Figure 1-24 Input Buffer Latches
1-21
40MX 42MX Automotive FPGA Families
Decode Module Timing
A-G,
tPHL tPLH
Figure 1-26 Decode Module Timing
Write Port WRAD [5:0] BLKEN WCLK [7:0] Array 64x4 Bits) Read Port RDAD [5:0] RCLK [7:0]
Figure 1-27 SRAM Timing Characteristics
40MX 42MX Automotive FPGA Families
Dual-Port SRAM Timing Waveforms
RCKHL WCLK tADSU WD[7:0] WRAD[5:0] Valid WENSU BENSU BLKEN
Note: Identical timing falling edge clock. Figure 1-28 42MX SRAM Write Operation
RCKHL
tADH
WENH
tBENH
Valid
CKHL RCLK
RCKHL
tRENSU tADSU RDAD[5:0] Valid tDOH RD[7:0]
Note: Identical timing falling edge clock. Figure 1-29 42MX SRAM Synchronous Read Operation
tRENH
tADH
tRCO Data
Data
1-23
40MX 42MX Automotive FPGA Families
(Read Address Controlled) RDADV RDAD[5:0] ADDR1 RD[7:0] Data ADDR2 Data
Figure 1-30 42MX SRAM Asynchronous Read Operation-Type
(Write Address Controlled)
WENSU
WENH
WD[7:0] WRAD[5:0] BLKEN
Valid tADSU tADH tRPD tDOH
WCLK
RD[7:0]
Data
Data
Figure 1-31 42MX SRAM Asynchronous Read Operation-Type
40MX 42MX Automotive FPGA Families
Predictable Performance: Tight Delay Distributions
Propagation delay between logic modules depends resistive capacitive loading routing tracks, interconnect elements, module inputs being driven. Propagation delay increases length routing tracks, number interconnect elements, number inputs increases. From design perspective, propagation delay statistically correlated modeled fanout (number loads) driven module. Higher fanout usually requires some paths have longer routing tracks. FPGAs deliver tight fanout delay distribution, which achieved ways: decreasing delay interconnect elements decreasing number interconnect elements path. Actel's patented antifuse offers very resistive/ capacitive interconnect. antifuses, fabricated 0.45 lithography, offer nominal levels resistance femtofarad (fF) capacitance antifuse. fanout distribution also tight number antifuses required each interconnect path. proprietary architecture limits number antifuses path maximum four, with percent interconnects using only antifuses.
Critical Nets Typical Nets
Propagation delays this datasheet apply typical nets, which used initial design performance evaluation. Critical delays then applied most timing critical paths. Critical nets determined property assignment Actel's Designer software prior placement routing. nets design designated critical.
Long Tracks
Some nets design long tracks, which special routing resources that span multiple rows, columns, modules. Long tracks employ three sometimes four antifuse connections, which increase capacitance resistance, resulting longer delays macros connected long tracks. Typically, percent nets fully utilized device require long tracks. Long tracks approximately delay, which represented statistically higher fanout (FO=8) routing delays datasheet specifications section beginning page 1-16.
Timing Derating
devices manufactured with CMOS process. Therefore, device performance varies according temperature, voltage process changes. Minimum timing parameters reflect maximum operating voltage, minimum operating temperature best-case processing. Maximum timing parameters reflect minimum operating voltage, maximum operating temperature worst-case processing.
Timing Characteristics
Device timing characteristics fall into three categories: family-dependent, device-dependent, designdependent. input output buffer characteristics common devices. Internal routing delays device-dependent. Design dependency means actual delays determined until after place-and-route user's design complete. Delay values then determined using Timer tool Designer software performing simulation with postlayout delays.
1-25
40MX 42MX Automotive FPGA Families
Temperature Voltage Derating Factors
Table 42MX Temperature Voltage Derating Factors (Normalized 125°C, VCCA/VCCI 4.75V) 42MX Voltage 4.75 5.00 5.25 Temperature -55°C 0.66 0.64 0.62 -40°C 0.67 0.65 0.64 0.74 0.72 0.70 25°C 0.78 0.75 0.73 70°C 0.89 0.87 0.84 85°C 0.91 0.89 0.86 125°C 1.00 0.97 0.94
42MX Derating Factor (Normalized 125°C, VCCA /VCCI =4.75V)
1.10 1.00 Derating Factor 0.90 0.80 0.70 0.60 0.50 0.40 4.75 5.00 Voltage
Note: This derating factor applies routing propagation delays. Figure 1-32 42MX Junction Temperature Voltage Derating Curves (Normalized 125°C, VCCA/VCCI 4.75V)
-55°C -40°C 25°C 70°C 85°C 125°C
5.25
40MX 42MX Automotive FPGA Families
Table 40MX Temperature Voltage Derating Factors (Normalized 125°C, 4.75V) 40MX Voltage 4.75 5.00 5.25 Temperature -55°C -40°C 25°C 70°C 85°C 125°C
0.62 0.60 0.58
0.64 0.62 0.60
0.71 0.69 0.67
0.75 0.73 0.71
0.86 0.84 0.82
0.90 0.88 0.85
1.00 0.97 0.94
40MX Derating Factor (Normalized 125°C, 4.75V)
1.10 1.00 Derating Factor 0.90 0.80 0.70 0.60 0.50 0.40 4.75 5.00 Voltage 5.25
-55°C -40°C 25°C 70°C 85°C 125°C
Note: This derating factor applies routing propagation delays. Figure 1-33 40MX Junction Temperature Voltage Derating Curves (Normalized 125°C, 4.75V)
1-27
40MX 42MX Automotive FPGA Families
Timing Characteristics
timing numbers datasheet represent sample timing characteristics devices. Refer Timer tool Designer software design-specific timing information.
Table A40MX02 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, 4.75V, 125°C Std. Speed Parameter Logic Module Propagation Delays tPD1 tPD2 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tHD3 tSUENA tHENA tWCLKA tWASYN fMAX tINYH tINYL tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Setup times assume fanout Further testing information obtained from Timer tool. hold time DFME1A macro greater than Timer tool Designer check hold time this macro. Delays based loading. Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
Description
Min.
Max.
Units
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Flip-Flop (Latch) Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency Pad-to-Y HIGH Pad-to-Y
10.2
Input Module Propagation Delays
Input Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
40MX 42MX Automotive FPGA Families
Table A40MX02 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, 4.75V, 125°C (Continued) Std. Speed Parameter Global Clock Networks tCKH tCKL tPWH tPWL tCKSW fMAX Input HIGH Input High Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Minimum Period Maximum Frequency Output Module Timing4 tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes: Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Setup times assume fanout Further testing information obtained from Timer tool. hold time DFME1A macro greater than Timer tool Designer check hold time this macro. Delays based loading. Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH 14.1 10.4 0.03 0.05 ns/pF ns/pF Description Min. Max. Units
1-29
40MX 42MX Automotive FPGA Families
Table 1-10 A40MX04 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, 4.75V, 125°C Std. Speed Parameter Logic Module Propagation Delays tPD1 tPD2 Single Module Dual-Module Macros Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays1
Description
Min.
Max.
Units
Logic Module Predicted Routing tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential tSUD tHD3 tSUENA tHENA tWCLKA tWASYN fMAX
Timing2
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Flip-Flop (Latch) Flip-Flop Clock Input Period Flip-Flop (Latch) Clock Frequency
Input Module Propagation Delays tINYH tINYL Pad-to-Y HIGH Pad-to-Y Delays1 10.2
Input Module Predicted Routing tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes: FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Setup times assume fanout Further testing information obtained from Timer tool. hold time DFME1A macro greater than Timer tool Designer check hold time this macro. Delays based loading.
40MX 42MX Automotive FPGA Families
Table 1-10 A40MX04 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, 4.75V, 125°C Std. Speed Parameter Global Clock Network tCKH Input HIGH tCKL Input High tPWH Minimum Pulse Width HIGH tPWL Minimum Pulse Width tCKSW Maximum Skew Minimum Period fMAX Maximum Frequency
Description
Min.
Max.
Units
Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ dTLH dTHL Notes:
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable Delta HIGH Delta HIGH
14.1 10.4 0.03 0.05
ns/pF ns/pF
Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Setup times assume fanout Further testing information obtained from Timer tool. hold time DFME1A macro greater than Timer tool Designer check hold time this macro. Delays based loading.
1-31
40MX 42MX Automotive FPGA Families
Table 1-11 A42MX09 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA 4.75V, 125°C Std. Speed Parameter Logic Module Propagation tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX tINYH tINYL tINGH tINGL Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Delays1
Description
Min.
Max.
Units
Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q
Logic Module Predicted Routing Delays FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Timing3,
Logic Module Sequential
Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency
Input Module Propagation Delays Pad-to-Y HIGH Pad-to-Y HIGH
40MX 42MX Automotive FPGA Families
Table 1-11 A42MX09 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA 4.75V, 125°C Std. Speed Parameter Input Module Predicted Routing Delays tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Description
Min.
Max.
Units
Global Clock Network Input HIGH Input High Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency Timing5 Output Module tDLH tDHL tENZH Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
Data-to-Pad HIGH Data-to-Pad Enable HIGH
1-33
40MX 42MX Automotive FPGA Families
Table 1-11 A42MX09 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA 4.75V, 125°C Std. Speed Parameter tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH 12.2 0.04 0.06 Description Min. Max. Units ns/pF ns/pF
40MX 42MX Automotive FPGA Families
Table 1-12 A42MX16 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA 4.75V, 125°C Std. Speed Parameter Logic Module Propagation Delays1 tPD1 tRD1 tRD2 tRD3 tRD4 tRD8 tSUD tSUENA tHENA tWCLKA tWASYN tINH tINSU tOUTH tOUTSU fMAX tINYH tINYL tINGH tINGL Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, point position whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Single Module Sequential Clock-to-Q Latch G-to-Q Flip-Flop (Latch) Reset-to-Q Delays2 Description Min. Max. Units
Logic Module Predicted Routing FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3,4 Flip-Flop (Latch) Data Input Set-Up Flip-Flop (Latch) Data Input Hold Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width Flip-Flop Clock Input Period Input Buffer Latch Hold Input Buffer Latch Set-Up Output Buffer Latch Hold Output Buffer Latch Set-Up Flip-Flop (Latch) Clock Frequency 11.3
Input Module Propagation Delays Pad-to-Y HIGH Pad-to-Y HIGH
1-35
40MX 42MX Automotive FPGA Families
Table 1-12 A42MX16 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA 4.75V, 125°C Std. Speed Parameter Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 tCKH tCKL tPWH tPWL tCKSW tSUEXT tHEXT fMAX FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Description Min. Max. Units
Global Clock Network Input HIGH Input High Minimum Pulse Width HIGH Minimum Pulse Width Maximum Skew Input Latch External Setup Input Latch External Hold Minimum Period Maximum Frequency Timing5 Output Module tDLH tDHL tENZH Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, point position whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
Data-to-Pad HIGH Data-to-Pad Enable HIGH
40MX 42MX Automotive FPGA Families
Table 1-12 A42MX16 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA 4.75V, 125°C Std. Speed Parameter tENZL tENHZ tENLZ tGLH tGHL tLCO tACO dTLH dTHL Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, point position whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters input buffer latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH Description Min. Max. 13.3 0.04 0.06 Units ns/pF ns/pF
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40MX 42MX Automotive FPGA Families
Table 1-13 A42MX24 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA 4.75V, 125°C Std. Speed Parameter Logic Module Combinatorial Functions1 tPDD Internal Array Module Delay Internal Decode Module Delay Description Min. Max. Units
Logic Module Predicted Routing Delays2 tRD1 tRD2 tRD3 tRD4 tRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Logic Module Sequential Timing3, tSUD tSUENA tHENA tWCLKA tWASYN Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width
40MX 42MX Automotive FPGA Families
Table 1-13 A42MX24 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA 4.75V, 125°C Std. Speed Parameter Input Module Predicted Routing Delays2 tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay Description Min. Max. Units
Global Clock Network tCKH Input HIGH tCKL Input High tPWH Minimum Pulse Width HIGH tPWL Minimum Pulse Width tCKSW Maximum Skew tSUEXT Input Latch External Setup tHEXT Input Latch External Hold Minimum Period fMAX Maximum Frequency Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
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40MX 42MX Automotive FPGA Families
Table 1-13 A42MX24 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, VCCA 4.75V, 125°C Std. Speed Parameter Output Module Timing5 tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH tGHL tLSU tLCO tACO dTLH dTHL Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Clock Loading Array Clock-to-Out (Pad-to-Pad), Clock Loading Capacity Loading, HIGH Capacity Loading, HIGH 17.8 0.06 0.05 ns/pF ns/pF Description Min. Max. Units
40MX 42MX Automotive FPGA Families
Table 1-14 A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, 4.75V, 125°C Std. Speed Parameter Logic Module Combinatorial Functions tPDD
Description
Min.
Max.
Units
Internal Array Module Delay Internal Decode Module Delay
Logic Module Predicted Routing Delays tRD1 tRD2 tRD3 tRD4 tRD8 tRDD FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
Decode-to-Output Routing Delay
Logic Module Sequential Timing tSUD tSUENA tHENA tWCLKA tWASYN
Flip-Flop Clock-to-Output Latch Gate-to-Output Flip-Flop (Latch) Set-Up Time Flip-Flop (Latch) Hold Time Flip-Flop (Latch) Reset-to-Output Flip-Flop (Latch) Enable Set-Up Flip-Flop (Latch) Enable Hold Flip-Flop (Latch) Clock Active Pulse Width Flip-Flop (Latch) Asynchronous Pulse Width
Synchronous SRAM Operations tRCKHL tRCO tADSU tADH Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Read Cycle Time Write Cycle Time Clock HIGH/LOW Time Data Valid After Clock HIGH/LOW Address/Data Set-Up Time Address/Data Hold Time 11.3 11.3
1-41
40MX 42MX Automotive FPGA Families
Table 1-14 A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, 4.75V, 125°C (Continued) Std. Speed Parameter tRENSU tRENH tWENSU tWENH tBENS tBENH Read Enable Set-Up Read Enable Hold Write Enable Set-Up Write Enable Hold Block Enable Set-Up Block Enable Hold Description Min. Max. Units
Asynchronous SRAM Operations tRPD tRDADV tADSU tADH tRENSUA tRENHA tWENSU tWENH tDOH Asynchronous Access Time Read Address Valid Address/Data Set-Up Time Address/Data Hold Time Read Enable Set-Up Address Valid Read Enable Hold Write Enable Set-Up Write Enable Hold Data Hold Time 14.7 13.6
Input Module Propagation Delays tINPY tINGO tINH tINSU tILA tIRD1 tIRD2 tIRD3 tIRD4 tIRD8 Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. Input Data Pad-to-Y Input Latch Gate-to-Output Input Latch Hold Input Latch Set-Up Latch Active Pulse Width
Input Module Predicted Routing Delays2 FO=1 Routing Delay FO=2 Routing Delay FO=3 Routing Delay FO=4 Routing Delay FO=8 Routing Delay
40MX 42MX Automotive FPGA Families
Table 1-14 A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, 4.75V, 125°C (Continued) Std. Speed Parameter Global Clock Network tCKH Input HIGH tCKL Input High tPWH Minimum Pulse Width HIGH tPWL Minimum Pulse Width tCKSW Maximum Skew tSUEXT Input Latch External Setup tHEXT Input Latch External Hold Minimum Period fMAX Maximum Frequency Output Module Timing tDLH tDHL tENZH tENZL tENHZ tENLZ tGLH Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading.
Description
Min.
Max.
Units
Data-to-Pad HIGH Data-to-Pad Enable HIGH Enable Enable HIGH Enable G-to-Pad HIGH
1-43
40MX 42MX Automotive FPGA Families
Table 1-14 A42MX36 Timing Characteristics (Nominal 5.0V Operation) Worst-Case Automotive Conditions, 4.75V, 125°C (Continued) Std. Speed Parameter tGHL tLSU tLCO tACO dTLH dTHL Notes: dual-module macros, tPD1 tRD1 tPDn, tRD1 tPDn, tPD1 tRD1 tSUD, whichever appropriate. Routing delays typical designs across worst-case operating conditions. These parameters should used estimating device performance. Post-route timing analysis simulation required determine actual performance. Data applies macros based S-module. Timing parameters sequential macros constructed from C-modules obtained from Timer tool. Setup hold timing parameters Input Buffer Latch defined with respect input. External setup/ hold timing parameters must account delay from external signal inputs. Delay from external signal input subtracts (adds) internal setup (hold) time. Delays based loading. G-to-Pad Latch Set-Up Latch Hold Latch Clock-to-Out (Pad-to-Pad), Array Clock-to-Out (Pad-to-Pad), Capacity Loading, HIGH Capacity Loading, HIGH 13.0 0.11 0.11 Description Min. Max. Units ns/pF ns/pF
40MX 42MX Automotive FPGA Families
Descriptions
CLK/A/B, Global Clock PRA/B, Probe
Clock inputs clock distribution networks. 40MX while CLKA CLKB 42MX devices. clock input buffered prior clocking logic modules. This also used I/O.
DCLK, Diagnostic Clock
clock input diagnostic probe device programming. DCLK active when MODE HIGH. This functions when MODE LOW.
Ground
Probe used output data from userdefined design node within device. Each diagnostic used conjunction with other probe allow real-time diagnostic output signal path within device. Probe used userdefined when verification been completed. pin's probe capabilities permanently disabled protect programmed design confidentiality. Probe accessible when MODE High. This functions when MODE Low.
QCLKA,B,C,D, Quadrant Clock
Input supply voltage.
Input/Output
Input, output, tristate, bidirectional buffer. Input output levels compatible with standard specifications. Unused pins configured Designer software shown Table 1-15.
Table 1-15 Configuration Unused I/Os Device A40MX02, A40MX04 A42MX09, A42MX16 A42MX24, A42MX36 Configuration Pulled Pulled Tristated
Quadrant clock inputs A42MX36 devices. When used register control signal, these pins function general-purpose I/Os.
SDI, Serial Data Input
Serial data input diagnostic probe device programming. active when MODE High. This functions when MODE Low.
SDO, TDO, Serial Data Output
Serial data output diagnostic probe device programming. active when MODE High. This functions when MODE Low. available 42MX devices only. When Silicon Explorer being used, will output while "checksum" run. will return user when "checksum" complete.
TCK, Test Clock
cases, recommended unused pins board. This applies dual-purpose pins when configured I/Os well.
MODE Mode
Controls multifunction pins (DCLK, PRA, PRB, SDI, TDO). provide verification capability, MODE should held HIGH. facilitate this, MODE should tied through resistor that MODE pulled HIGH when required.
Connection
Clock signal shift Boundary Scan Test (BST) data into device. This functions when "Reserve JTAG" checked Designer software. pins only available A42MX24 A42MX36 devices.
TDI, Test Data
This connected circuitry within device. These pins driven voltage left floating with effect operation device.
Serial data input instructions data. Data shifted rising edge TCK. This functions when "Reserve JTAG" checked Designer software. pins only available A42MX24 A42MX36 devices.
1-45
40MX 42MX Automotive FPGA Families TDO, Test Data Supply Voltage
Serial data output instructions test data. This functions when "Reserve JTAG" checked Designer software. pins only available A42MX24 A42MX36 devices.
TMS, Test Mode Select
Supply voltage 40MX devices.
VCCA Supply Voltage
Supply voltage array 42MX devices.
VCCI Supply Voltage
controls IEEE 1149.1 Boundary Scan pins (TCK, TDI, TDO). flexible mode when LOW, TCK, pins boundary-scan pins. Once boundary scan pins test mode, they will remain that mode until internal boundary scan state machine reaches "logic reset" state. this point, boundary scan pins will released will function regular pins. "logic reset" state reached five cycles after High. dedicated test mode, functions specified IEEE 1149.1 specifications. IEEE JTAG specification recommends pull-up resistor pin. pins only available A42MX24 A42MX36 devices.
Supply voltage I/Os 42MX devices.
Wide Decode Output
When wide decode module used A42MX24 A42MX36 device, this used dedicated output from wide decode module. This direct connection eliminates additional interconnect delays associated with regular logic modules. implement direct connection, connect output buffer type output wide decode macro place this output reserved pins. When wide decode module used, this functions regular pin.
40MX 42MX Automotive FPGA Families
Package Assignments
68-Pin PLCC
68-Pin PLCC
Figure 68-Pin PLCC
Note
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40MX 42MX Automotive FPGA Families
68-Pin PLCC Number A40MX02 Function VCCy Number
68-Pin PLCC A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB,
40MX 42MX Automotive FPGA Families
84-Pin PLCC
84-Pin PLCC
Figure 84-Pin PLCC
Note
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40MX 42MX Automotive FPGA Families
84-Pin PLCC Number A40MX04 Function A42MX09 Function CLKB, PRB, DCLK, MODE VCCA VCCI Number
84-Pin PLCC A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB, A42MX09 Function VCCA SDO, VCCA VCCI SDI, PRA, CLKA, VCCA
40MX 42MX Automotive FPGA Families
100-Pin PQFP
100-Pin PQFP
Figure 100-Pin PQFP (Top View)
Note
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40MX 42MX Automotive FPGA Families
100-Pin PQFP Number A40MX02 Function PRB, A40MX04 Function PRB, A42MX09 Function DCLK, MODE VCCA VCCI Number
100-Pin PQFP A40MX02 Function A40MX04 Function A42MX09 Function VCCA SDO, VCCA VCCI VCCA
40MX 42MX Automotive FPGA Families
100-Pin PQFP Number A40MX02 Function CLK, MODE SDI, DCLK, PRA, A40MX04 Function CLK, MODE SDI, DCLK, PRA, A42MX09 Function SDI, PRA, CLKA, VCCA CLKB, PRB,
40MX 42MX Automotive FPGA Families
160-Pin PQFP
160-Pin PQFP
Figure PQFP (Top View)
Note
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40MX 42MX Automotive FPGA Families
160-Pin PQFP Number A42MX09 Function DCLK, PRB, CLKB, VCCA CLKA, PRA, SDI, A42MX24 Function DCLK, VCCI PRB, CLKB, VCCA CLKA, PRA, VCCI SDI, Number
160-Pin PQFP A42MX09 Function VCCA VCCI VCCA A42MX24 Function VCCA VCCA VCCI VCCA TCK,
40MX 42MX Automotive FPGA Families
160-Pin PQFP Number A42MX09 Function SDO, VCCA A42MX24 Function SDO, TDO, VCCI VCCA VCCI TDI, TMS, Number
160-Pin PQFP A42MX09 Function VCCI MODE A42MX24 Function VCCA VCCA VCCI VCCA MODE
40MX 42MX Automotive FPGA Families
80-Pin VQFP
80-Pin VQFP
Figure 80-Pin VQFP
Note
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2-11
40MX 42MX Automotive FPGA Families
80-Pin VQFP Number A40MX02 Function A40MX04 Function Number
80-Pin VQFP A40MX02 Function CLK, MODE SDI, DCLK, PRA, PRB, A40MX04 Function CLK, MODE SDI, DCLK, PRA, PRB,
40MX 42MX Automotive FPGA Families
208-Pin PQFP
208-Pin PQFP
Figure 208-Pin PQFP (Top View)
Note
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2-13
40MX 42MX Automotive FPGA Families
208-Pin PQFP Number A42MX16 Function MODE VCCA VCCI VCCA VCCA A42MX24 Function VCCA MODE VCCA VCCI VCCA VCCA A42MX36 Function VCCA MODE VCCA VCCI VCCA VCCA Number
208-Pin PQFP A42MX16 Function VCCI A42MX24 Function TMS, TDI, VCCI A42MX36 Function TMS, TDI, VCCI QCLKA,
40MX 42MX Automotive FPGA Families
208-Pin PQFP Number A42MX16 Function VCCA VCCI SDO, A42MX24 Function VCCA VCCI VCCI A42MX36 Function VCCA VCCI QCLKB, VCCI Number
208-Pin PQFP A42MX16 Function VCCA VCCI VCCA VCCA A42MX24 Function VCCA TCK, VCCA VCCI VCCA VCCA A42MX36 Function VCCA TCK, VCCA VCCI VCCA VCCA
SDO, TDO, SDO, TDO,
2-15
40MX 42MX Automotive FPGA Families
208-Pin PQFP Number A42MX16 Function SDI, VCCI A42MX24 Function SDI, VCCI A42MX36 Function SDI, VCCI QCLKD, Number
208-Pin PQFP A42MX16 Function PRA, CLKA, VCCA CLKB, PRB, VCCI DCLK, A42MX24 Function PRA, CLKA, VCCI VCCA CLKB, PRB, VCCI DCLK, A42MX36 Function PRA, CLKA, VCCI VCCA CLKB, PRB, QCLKC, VCCI DCLK,
40MX 42MX Automotive FPGA Families
240-Pin PQFP
240-Pin PQFP
Figure 240-Pin PQFP (Top View)
Note
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2-17
40MX 42MX Automotive FPGA Families
240-Pin PQFP Number A42MX36 Function DCLK, VCCI QCLKC, PRB, CLKB, VCCA VCCI CLKA, PRA,
240-Pin PQFP Number A42MX36 Function QCLKD, VCCI SDI, VCCA VCCI
240-Pin PQFP Number A42MX36 Function VCCA VCCA VCCI VCCA TCK, VCCI VCCA
40MX 42MX Automotive FPGA Families
240-Pin PQFP Number A42MX36 Function SDO, TDO, VCCI QCLKB, VCCI VCCA
240-Pin PQFP Number A42MX36 Function QCLKA, VCCI TDI, TMS, VCCA VCCI
240-Pin PQFP Number A42MX36 Function VCCA VCCA VCCI VCCA VCCI MODE VCCA
2-19
40MX 42MX Automotive FPGA Families
100-Pin VQFP
100-Pin VQFP
Figure 100-Pin VQFP (Top View)
Note
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40MX 42MX Automotive FPGA Families
100-Pin VQFP Number A42MX09 Function MODE VCCA VCCI A42MX16 Function MODE VCCI Number
100-Pin VQFP A42MX09 Function VCCA SDO, VCCA VCCI VCCA A42MX16 Function VCCA SDO, VCCA VCCI VCCA
2-21
40MX 42MX Automotive FPGA Families
100-Pin VQFP Number A42MX09 Function SDI, PRA, CLKA, VCCA CLKB, PRB, DCLK, A42MX16 Function SDI, PRA, CLKA, VCCA CLKB, PRB, DCLK,
40MX 42MX Automotive FPGA Families
176-Pin TQFP
176-Pin TQFP
Figure 176-Pin TQFP (Top View)
Note
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2-23
40MX 42MX Automotive FPGA Families
176-Pin TQFP Number A42MX09 Function MODE VCCA VCCI A42MX16 Function MODE VCCA VCCI VCCA VCCA A42MX24 Function MODE VCCA VCCI VCCA VCCA Number
176-Pin TQFP A42MX09 Function VCCA A42MX16 Function VCCI VCCA A42MX24 Function TMS, TDI, VCCI VCCA
40MX 42MX Automotive FPGA Families
176-Pin TQFP Number A42MX09 Function SDO, A42MX16 Function VCCI SDO, A42MX24 Function VCCI SDO, TDO, Number
176-Pin TQFP A42MX09 Function VCCA VCCI VCCA SDI, A42MX16 Function VCCA VCCI VCCA VCCA SDI, VCCI A42MX24 Function TCK, VCCA VCCI VCCA VCCA SDI, VCCI
2-25
40MX 42MX Automotive FPGA Families
176-Pin TQFP Number A42MX09 Function PRA, CLKA, VCCA CLKB, A42MX16 Function PRA, CLKA, VCCA CLKB, A42MX24 Function PRA, CLKA, VCCA CLKB, Number
176-Pin TQFP A42MX09 Function PRB, DCLK, A42MX16 Function PRB, VCCI DCLK, A42MX24 Function PRB, VCCI DCLK,
40MX 42MX Automotive FPGA Families
Datasheet Information
List Changes
following table lists critical changes that were made current version document.
Previous Version v3.0 April 2004 v2.0 Changes Current Version v3.1 note added "Ordering Information". Note added "Recommended Operating Conditions". "Speed Grade Temperature Grade Matrix" table new. "Clock Networks" section updated. "I/O Modules" section updated. "Other Architectural Features" section "Development Tool Support" section updated. "Electrical Specifications" table updated. "Junction Temperature" section updated. Table updated. Figure 1-15 Figure 1-16 were updated. Figure 1-17 updated. Figure 1-18 updated. "Critical Nets Typical Nets" section updated. "Timing Derating" section new. Table Figure 1-32 were updated. Table Figure 1-33 were updated. timing numbers contained Table through Table 1-14 were updated. "Pin Descriptions" section updated. Page 1-12 page 1-ii page page page page 1-11 page 1-12 page 1-15 page 1-15 page 1-16 page 1-17 page 1-18 page 1-25 page 1-25 page 1-26 page 1-27 page 1-28 page 1-41 page 1-45
Datasheet Categories
order provide latest information designers, some datasheets published before data been fully characterized. Datasheets designated "Product Brief," "Advanced," "Production," "Web-only." definition these categories follows:
Product Brief
product brief summarized version advanced datasheet (advanced production) containing general product information. This brief gives overview specific device family information.
Advanced
This datasheet version contains initial estimated information based simulation, other products, devices, speed grades. This information used estimates, production.
Datasheet Supplement
datasheet supplement gives specific device information derivative family that differs from general family datasheet. supplement used conjunction with datasheet obtain more detailed information specifications that differ between families.
Unmarked (production)
This datasheet version contains information that considered final.
v3.1
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