8500-0019 User's Guide Rev. June 2000 This Page Intenti
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bc635VME/bc350VXI Time Frequency Processor
8500-0019
User's Guide
Rev. June 2000
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Declaration Conformity
Application Council Directive(s) Standard(s) which Conformity Declared
89/336/EEC 50081-1, 50082-1
Manufacturer's Address 6781 Oro, Jose, 95119-1360 Importer's Name Importer's Address Type Equipment Model Serial
Electronics
bc635VME/350VXI Year Manufacture
1997
undersigned, hereby declare that equipment specified above conforms Directive(s) Standard(s).
Place
Datum, Inc.
(Signature)
Date
October 1997
Ronald Holm
(Full Name)
Engineering Manager
(Position)
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bc635VME/bc350VXI TIME FREQUENCY PROCESSOR TABLE CONTENTS SECTION CHAPTER INTRODUCTION General. Features Physical Overview. Specifications. 1.3.1 Time Code Reader. 1.3.2 Time Code Generator 1.3.3 Characteristics. 1.3.4 Digital Inputs. 1.3.5 External 10MHz Input/Output 1.3.6 Digital Outputs. 1.3.7 Oscillator Control Output Environmental Specifications. Functional Overview 1.5.1 Time 1.5.1.1 Time Sync Mode 1.5.1.2 Time Format 1.5.1.3 Time 1.5.1.4 Year 1.5.1.5 Local Offset. 1.5.1.6 Propogation Delay 1.5.1.7 Days 1.5.2 Time Code. 1.5.2.1 Decode. 1.5.2.2 Generate. 1.5.3 Signals 1.5.3.1 Heartbeat (Periodic) Output 1.5.3.2 Strobe Output 1.5.3.3 Event Input 1.5.3.4 Frequency Output 1.5.4 Interrupts 1.5.5 Oscillator Parameters 1.5.6 Sync Time External Time 1.5.7 Board Reset. PAGE
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bc635VME/bc350VXI Time Frequency Processor (Rev.
TABLE CONTENTS
CHAPTER INSTALLATION SETUP VME/VXI Compatibility Switches. VMEbus Base Address Selection. bc350VXI Logical Address Selection. Jumpers Installation. CHAPTER THREE INTERFACES General. Data Input Output. CHAPTER FOUR FIFO DATA PACKETS General. Writing Data Packets 4.1.1 Packet Select Operational Mode. 4.1.2 Packet Major Time. 4.1.3 Packet Command Input 4.1.4 Packet Load Converter. 4.1.5 Packet Heartbeat (Periodic) Control 4.1.6 Packet Offset Control. 4.1.7 Packet Time Code Format Mode 4-10 4.1.8 Packet Clock Source Select. 4-10 4.1.9 Packet Send Data Receiver. 4-10 4.1.10 Packet Select Generator Code 4-11 4.1.11 Packet Real Time Clock 4-11 4.1.12 Packet Local Time Offset Select (GPS Modes Only) 4-12 4.1.13 Packet Request Data From TFP. 4-13 4.1.14 Packet Path Selection 4-15 4.1.14.1 Descriptions. 4-15 4.1.14.2 Upper Nibble Descriptions. 4-16 4.1.15 Packet Disciplining Gain. 4-17 4.1.16 Packet Year 4-17
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CHAPTER FIVE PROGRAMMING EXAMPLES General. Reading Time Demand External Event Time Capture. Program Periodic Frequency 1000 Mode Major Time Select Mode (IRIGB)and Advance Milliseconds. CHAPTER INPUTS OUTPUTS Inputs Outputs.
CHAPTER SEVEN ADJUSTMENTS General. CHAPTER EIGHT REVISION HISTORY General. CHAPTER NINE DRAWING General.
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CHAPTER INTRODUCTION GENERAL bc635VME/bc350VXI Time Frequency Processor User's Guide provides following information: Introduction feature description. Installation setup. Detailed operation programming interfaces. Input output signals. Programming examples. Drawing set.
FEATURES Time Frequency Processor (TFP) been designed with following features: Time demand (days through microseconds) with zero latency. This feature implemented with hardware registers which latch current time upon host request. Event logging (days through microseconds). This feature implemented with second hardware registers. Time captured positive negative input edge. operational modes supported. Modes distinguished reference source. Mode Source Synchronization Timecode IRIGA IRIGB 2137 NASA36 Free running board VCXO used reference. accepts input pulse second. uses battery backed board real time clock (optional) double wide configuration including receiver. (obsolete) (optional) uses receiver/antenna (receiver antenna).
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Provides output clock synchronized selected reference; programmable 10MHz TTL. modes operation supplemented flywheel operation. example, synchronization source lost, will continue function last known reference rate. Generates synchronized IRIG timecode. Modulated level shift formats produced simultaneously. Also generates IRIG level shift. Programmable frequency output (periodics) provided. output frequency 10,000,000 n2). 1<n1<65536 1<n2<65536. time coincidence strobe output provided. Programmable from hours through milliseconds. This strobe also each second mode programmable milliseconds. Five maskable interrupt sources supported. levels through seven programmable. Int. Source Interrupt External event input occurred. Periodic output occurred. Time coincidence strobe occurred. second epoch (1pps output) occurred. Output data packet available.
Time-of-day, hours, minutes, seconds displayed front panel LED's. Most inputs outputs accessible connector.
PHYSICAL OVERVIEW size module mm). Operation controlled block thirty-two registers written read host VMEbus (A16 D16). available versions. bc635VME intended VMEbus system with most signals available rows connector. bc350VXI intended VXIbus system, shipped without connector. switch used select compatibility. VMEbus systems register block located byte boundary. VXIbus systems register block located logical addresses (A15 must high). logical address returned during interrupt acknowledge cycle.
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INTRODUCTION
SPECIFICATIONS 1.3.1 TIMECODE READER Format Carrier Range Modulation Ratio Input Amplitude Input Impedance Format DCLS Carrier Range Input Amplitude Input Impedance IRIG 2137 NASA 50ppm. 6:1. volts peak peak. coupled. IRIG IRIG NASA 50ppm. TTL/CMOS Compatible coupled.
1.3.2 TIMECODE GENERATOR Format Modulation Ratio Output Amplitude Format DCLS Level Shift IRIG 3:1. volts peak peak, adjusted VR1, into IRIG IRIG TTL/CMOS compatible, into
1.3.3 CHARACTERISTICS Address Space Data Transfer Interrupter Power 1.3.4 DIGITAL INPUTS Event Capture TTL/CMOS positive negative edge triggered. nanoseconds minimum width nanoseconds minimum period. Input impedance TTL/CMOS positive edge time. Twenty nanoseconds minimum width. Input impedance A16, codes $2D, bytes. D16. D08(0), I(1-7), ROAK. 1.5amps milliamp milliamp
External 1pps
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1.3.5 EXTERNAL 10MHz INPUT/OUTPUT 10MHz Input TTL/CMOS Duty Cycle. Volts Peak-To-Peak, coupled 2.5KHz impedance.
Note: When ovenized onboard oscillator used, external 10MHz input feature disabled. Instead output ovenized oscillator appears this pin. only drive single high impedance load. 1.3.6 DIGITAL OUTPUTS 1pps Periodics Strobe 10MHz Clock TTL/CMOS positive edge time, 200mS positive pulse, into TTL/CMOS positive edge time, into (See section 4.1.5) TTL/CMOS positive edge time, positive pulse, into TTL/CMOS positive edge time, 10MHz square wave, 1MHz 80/20 duty cycle, into
1.3.7 OSCILLATOR CONTROL OUTPUT Control Range Transfer Coefficient Positive
ENVIRONMENTAL SPECIFICATIONS Temperature Relative Humidity Altitude Operating Non-Operating Operating Operating centigrade. +85o centigrade. 1000 hours. -400 18,000 meters MSL.
FUNCTIONAL OVERVIEW This section describes functions provided bc635VME/bc350VXI Time Frequency Processor (TFP). 1.5.1 TIME This function controls card acquires maintains time data. These functions allow user select where obtain time data, whether manipulate time data present time data user system.
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INTRODUCTION
1.5.1.1 TIME SYNC MODE This allows user select operating mode (time source) device. Available modes Time Code Decoding, Freerunning, External 1PPS, (Optional). 1.5.1.2 TIME FORMAT event time capture time registers default decimal time format. major time registers divided into fields each decimal digit days, hours minutes seconds. mode only, time registers operate binary format where major time represented seconds since epoch. 1.5.1.3 TIME This function allows user time device. Decimal time values entered into time registers. This function typically used when operating either Freerunning External 1PPS modes. While function used when operating Time code modes, subsequent time data received from selected reference source will overwrite loaded time. 1.5.1.4 YEAR This nction allows user year data. Typically, this function used when board operating time code decoding mode. Many time code formats (including standard IRIG include year information data. Using this function will allow device extract time year data from time code source while using year information provided user. board will decode year roll over days leap year (365-366-001) non-leap year (365-001). supported range 1990 2037. board will follow input time source input rollover sequence does match board rollover sequence defined programmed year. 1.5.1.5 LOCAL OFFSET This function allows user program local offset 1-hour increments into device. local offset value nonzero, device will adjust reference timing information order maintain local time clock. this function only affects time data TIME registers described paragraph 3.1. 1.5.1.6 PROPAGATION DELAY This function allows user command device compensate propagation delays introduced currently selected reference source. example, when unit operating Time code decoding mode, long cable could result input time code having propagation delay. delay value programmable units 100ns allowed range from -9999999 through +9999999.
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1.5.1.7 DAYS When time source signal present board power board will begin counting 000. operated count days modes. default Invalid Mode, will accept input 000. Table shows possible combinations input source data current board state left side, result rollover right side. Note that table includes such combinations where board non-leap year, source leap year.
Table Invalid Mode Combination number 1.1.1 1.1.2 1.1.3 1.2.1 1.2.2 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 Board year Input mode Timecode Timecode Timecode Freerun Freerun Timecode Timecode Timecode Freerun Freerun Source Year Source Board year Board Freerun Notes lost track
Note went about second, then went
optional Accept Mode, will accept input source with input 000. Table shows possible combinations this mode.
Table Accept Mode Combination number 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2.1 3.2.2 3.2.3 3.2.4 4.1.1 4.1.2 4.1.3 4.1.4 4.2.1 4.2.2 4.2.3 Board year Input mode Timecode Timecode Timecode Timecode Timecode Freerun Freerun Freerun Freerun Timecode Timecode Timecode Timecode Freerun Freerun Freerun Input Year Input Board year Board Notes
Note went about second, then went
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INTRODUCTION
1.5.2 TIME CODE This function group provides access functions controlling card operation while decoding time code. These functions allow user control both time code decoding time code generating circuits device. 1.5.2.1 DECODE This function allows user select format modulation types associated with input timing signal. These values control device attempts decode input time code. These values regardless mode will only used time code decoding mode. format defines type time code data. modulation defines envelope signal which input signal will extracted from. default format IRIG default modulation envelope (amplitude modulated). 1.5.2.2 GENERATE This function allows user select format time code that will generated device. time code generator supports IRIG IRIG DCLS. 1.5.3 SIGNALS This group provides access functions that control various hardware timing signals either decoded generated card. 1.5.3.1 HEARTBEAT (PERIODIC) OUTPUT This function allows user command produce clock signal specified frequency. heartbeat signal, also referred periodic, either synchronous asynchronous internal 1PPS epoch device. This functionality implemented hardware device Intel 82C54 counter timer chip. heartbeat circuit divisors, which clocked counter. output first divisor provides clock second divisor, manipulating divisor values results various duty cycles. output this circuitry capable creating interrupt. Section 4.1.5 description program heartbeat output. 1.5.3.2 STROBE OUTPUT This function allows user command produce hardware signal particular time, particular point during second interval. When major/minor mode selected, hardware signal will produced when internal time device matches values entered major minor strobe registers. major time hours, minutes seconds supplied addition milliseconds loaded minor strobe register. When minor mode selected, strobe signal
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produced every second when internal millisecond count device matches value entered minor strobe register. output this circuitry capable creating interrupt. 1.5.3.3 EVENT INPUT This function allows user command device monitor hardware timing signal. source signal either External Event input device output Heartbeat (Periodic) mentioned earlier this chapter. External Event signal capture occur either rising falling edge. Heartbeat signal capture always rising edge. When signal occurs selected format, time which signal occurred loaded into event time registers. capture lockout checkbox used control whether subsequent signals will overwrite data event time registers. output this circuitry capable creating interrupt. 1.5.3.4 FREQUENCY OUTPUT This function allows user control frequency signal output device. available frequencies MHz. default state this output 10MHz. 1.5.4 INTERRUPTS This function allows user control generation interrupts device. latch event time function enabled, will latch time event time registers when interrupt detected. user query event time registers when particular event occurred. latch event time function should enabled when external events selected these already latch time event registers. Three control registers provided control interrupts. 1.5.5 OSCILLATOR PARAMETERS This group allows user select external oscillator board oscillator, addition enabling/disabling disciplining jamsyncing. disciplining jamsyncing disabled, oscillator control programmed hold oscillator control voltage specific value. When synchronized input time source, oscillator will disciplined input source signal. 1.5.6 SYNC TIME EXTERNAL TIME This function allows user force Real Time Clock (RTC) time board time. 1.5.7 BOARD RESET This function allows user reset device. This command useful when starting test case that unexpected behavior observed from card. This function used during normal operation.
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CHAPTER INSTALLATION SETUP VME/VXI COMPATIBILITY SWITCHES designed both VMEbus VXIbus compatibility. Switches SW2-3 SW2-4 used select protocol. select VXIbus compatibility SW2-3 SW2-4 OPEN position. select VMEbus compatibility SW2-3 SW2-4 CLOSED position. Location Revision Through Revision Location Revision
Figure Address Switches Switch SW2-3 controls register block addressing within address space. With this switch position, address bits must selection. Switch then used select logical address module. With SW2-3 position, module mapped byte block address space. SW2-1 SW2-2 address bits, used through address bits. Switch SW2-4 controls status/ID byte returned during interrupt acknowledge cycles. With SW2-4 position, Status/ID byte returned during interrupt acknowledge cycles logical address with SW1. When SW2-4 position, Status/ID byte returned during interrupt acknowledge cycles user programmable vector loaded into VECTOR register (discussed Chapter Three).
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VMEbus BASE ADDRESS SELECTION Base address selection VMEbus requires setting switch through A13) (A14 A15). bc635VME occupies bytes address space freely located byte boundary. correspondence switch positions address bits illustrated Table 2-1. Table Address Bits Switch Positions
Address Switch Number
Example switch settings SW2. OPEN CLOSED
address range used. (The BASE address left side.) 0x0000 0x003F
0x0040 0x007F 0x0080 0x00BF 0x00C0 0x00FF 0x0100 0x013F 0xEFC0 0xFEFF 0xFF00 0xFF3F 0xFF40 0xFF74
select base address, each switches logical zero (CLOSED logical (OPEN OFF) state. bc350VXI LOGICAL ADDRESS SELECTION Logical address selection VXIbus requires setting switch through A13). bc350VXI occupies bytes address space located logical addresses within VXIbus. correspondence between switch positions address bits, logical state corresponding switch setting follows description provided Section
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JUMPERS (DEFAULT SETTING BOLD TYPE) jumper locations Rev. through Rev. versions shown Figure 2-2. Rev. along with P100004 version jumpers shown Figure 2-3. jumper blocks drawn scale order make numbers more visible. helpful refer schematic diagrams obtain clearer idea function each jumper option. With jumper position configured level shift input timecode. open position configured modulated timecode. (GPS Option) position configured single ended 1pps input. position configured differential 1pps input. (GPS Option) position configured ACUTIME Smart Antenna SV-6 sensor. position configured TANS sensor. ACUTIME, SV-6, TANS sensor options that available from Datum, Inc. This jumper present P100004 model boards. jumpers group designed moved pair. Positions define configuration, positions define second configuration. default configuration configured with auxiliary RS-422 output. second configuration configured daisy-chain mode (the RS-422 input jumpered RS-422 output). This jumper intended used digital synchronization mode. present time this mode been implemented. This jumper present P100004 model boards. position this jumper places "100" load between RS-422 input lines. position "100" load bypassed. When terminal device RS-422 daisy chain load should used. When chain load should omitted. position this jumper places GROUND C12. position 10MHz clock driven C12. model P100004 boards, this jumper implemented block. shunt pins enables 10MHz output C12. shunt pins disables output grounding C12.
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Jumper Location Revision Revision
Jumper Location Revision Through Revision
Figure Jumper Locations
Jumper Location Revision Jumper Location P100004 Models
Figure Jumper Locations
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INSTALLATION SETUP
INSTALLATION install into computer chassis follow steps below. Remove IACKIN*/IACKOUT* back plane jumper slot. This step should performed even interrupts used. bc635VME users must verify that signals rows connector used other purposes. provides signal rows that produce conflict. conflict does exist, solution obtain bc635VME with connector removed. Verify that power insert into chassis, securing slot tightening front panel screws.
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CHAPTER THREE INTERFACES GENERAL occupies bytes VMEbus/VXIbus, address space. Refer Section details VMEbus Base Address selection, Section VXIbus logical address selection. data transfers with exception packet which allows D08(0) transfers. glossary terms commonly used discussion timing operation provided below. Epoch reference time event. Epoch often refers pulse second event. Flywheel Maintain time frequency accuracy well local resources when time frequency reference been lost removed. Periodic programmable frequency which obtained dividing reference frequency. Periodics sometimes referred "heartbeats." Periodics optionally synchronous with 1pps epoch period expressible ratio integers. Major Time Units time larger than equal seconds. hr:min:sec format usually implied. Minor Time Subsecond time whatever resolution supported. Packet group bytes conforming defined structure. Packets usually used serial byte serial data transmission allow framing transmitted data. DATA INPUT OUTPUT Communication with performed using memory mapped registers. These registers read only (R), write only (W), read/write (R/W). some cases read/write register structured support dissimilar data read write directions. Table summarizes type register located each hexadecimal offset, provides brief description register function. data format detailed descriptions each register provided next section.
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Offset 6-08 30-3E
Type
Table Register Summary Label Function Read/Write Register. VXIbus Register Device. VXIbus Device Type Register Status/Control. VXIbus Status Control Registers Reserved TIMEREQ Time Request (Time Latching Strobe) TIME0 Requested Time (includes status byte) TIME1 Requested Time TIME2 Requested Time TIME3 Requested Time TIME4 Requested Time EVENT0 Event Time EVENT1 STROBE1 Event Time/Strobe Time EVENT2 STROBE2 Event Time/Strobe Time EVENT3 STROBE3 Event Time/Strobe Time EVENT4 Event Time UNLOCK Release Lockout/Capture Time Acknowledge Register Command Register FIFO FIFO Input/Output (D16 D08[O]) MASK Interrupt Mask INTSTAT Interrupt Status VECTOR Interrupt Vector LEVEL Interrupt Level Reserved
Offset 0x00 REGISTER Reset Value 0xXef4 This register implemented satisfy VXIbus Specification. assignments follows. Table Field Meaning 15-14 Device Class Register Based 13-12 Addressing Modes Only 11-0 Manufacturer's 0xef4
Bits 12-15 driven high during read Register. most cases they will float high during read cycle.
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Offset 0x02 DEVICE Reset Value 0xX350 This register simply contains case only device) manufacturer's card Bits 12-15 driven high during read Device Register. most cases they will float high during read cycle. Offset 0x04 STATUS Reset Value 0xffff does support VXIbus initialization diagnostic features. reset value always returned. Offset 0x04 CONTROL Reset Value 0xfffe Writing this register with will deassert pending interrupts will clear used bits offsets 0x20 through 0x2E (except FIFO offset 0x28). Writing this register with zero cleared effect. other bits ignored during write. Offset 0x0A TIMEREQ Reset Value Reading this register latches current time status into offsets 0x0C through 0x14. value read indeterminate.
WARNING Many compilers will optimize existence assignment made local variable that variable used. example, following code snippet read offset 0x0A.
timeptr (short *)(BASE 0x0A) local_dummy *timeptr++ read_time(timeptr)
initialize pointer latch time read time
following form recommended. global prevents optimizing out. timeptr (short (BASE 0x0A) global_dummy *timeptr++ read_time(timeptr) Offset 0X0C Offset 0X0E Offset 0X10 Offset 0X12 Offset 0X14 TIME0 TIME1 TIME2 TIME3 TIME4 Reset Value Reset Value Reset Value Reset Value Reset Value initialize pointer latch time read time
clarity above offsets have been grouped.
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TIME0 Field TIME1 Field TIME2 Field TIME3 Field TIME4 Field Offset 0x16 Offset 0x18 Offset 0x1A Offset 0x1C Offset 0x1E
15-12 Defined Days Tens Minutes Tens 10E-1 Seconds 10E-5 Seconds EVENT0 EVENT1 EVENT2 EVENT3 EVENT4
Table 11-8 Defined Days Units Minutes Units 10E-2 Seconds 10E-6 Seconds Reset Value Reset Value Reset Value Reset Value Reset Value
Status (Note Hours Tens Seconds Tens 10E-3 Seconds 10E-7 Seconds
Days Hundreds Hours Units Seconds Units 10E-4 Seconds Defined
clarity above offsets have been grouped. Table 11-8 Defined Days Units Minutes Units 10E-2 Seconds 10E-6 Seconds
EVENT0 Field EVENT1 Field EVENT2 Field EVENT3 Field EVENT4 Field Note: Offset 0x18 Offset 0x1A Offset 0x1C
15-12 Defined Days Tens Minutes Tens 10E-1 Seconds 10E-5 Seconds
Status (Note Hours Tens Seconds Tens 10E-3 Seconds 10E-7 Seconds
Days Hundreds Hours Units Seconds Units 10E-4 Seconds Defined
frequency offset Mode frequency offset time offset microseconds mode flywheeling (not locked) STROBE1 STROBE2 STROBE3
frequency offset Mode frequency offset time offset microseconds more other modes) locked selected reference
Reset Value 0xXX00 Reset Value 0x0000 Reset Value 0x0000
clarity above offsets have been grouped.
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INTERFACES
STROBE1 Field STROBE2 Field STROBE3 Field
15-12 Defined Minutes Tens 10E-1 Seconds
Table 11-8 Defined Minutes Units 10E-2 Seconds
Hours Tens Seconds Tens 10E-3 Seconds
Hours Units Seconds Units Defined
Offset 0x20 UNLOCK Reset Value read this register releases time capture lockout function been enabled. "CMD OFFSET 0x24" additional details. data read from this offset meaningless. write UNLOCK register acts secondary time latching strobe. Time latched EVENT0 EVENT4. This feature allows host capture times independently. Offset 0x22 Reset Value 0xXX00
Control HOST HOST
Table Function (SET High Voltage, CLEAR Voltage) SETS acknowledge receipt valid input packet from host CLEARS writing this register with SET. Reserved SETS when output FIFO contains data packet. CLEARS writing this register with SET. This generate interrupt. (see OFFSET 0x2A INTSTAT). Reserved SETS output FIFO contains data. CLEARS output FIFO empty. CLEARS output FIFO writing this register with four SET. Reserved Reserved Must write this register with seven cause take action data packet previously written input FIFO. Reserved
8-15
HOST
HOST
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Offset 0x24
Reset Value 0xXX00
This register used command perform specific functions. Table Name LOCKEN Function Event capture lockout disable lockout enable lockout). Prevents event from overwriting previous event until UNLOCK performed (see OFFSET 0x20 UNLOCK). Enable periodic time capture disable enable). When enabled periodic output logically OR'ED with event input, time periodic read EVENT0 EVENT4. Event capture sense select rising edge falling edge). Event capture enable disable enable). Time coincidence output strobe enable disable enable). Strobe mode major minor time minor time only). mode output strobe produced each second. Reserved
HBEN
8-15
EVSENSE EVENTEN STREN STRMODE FREQSEL0 FREQSEL1
Offset 0x26 FIFO Reset Value Reads take data from output FIFO. Writes place data into input FIFO. Both input FIFO output FIFO also accessed D08(O) offset 0x27. Each FIFO depth bytes. Data must written read from FIFO following data packet format. byte byte byte byte byte byte 0x01 through data data data 0x17 header byte (ASCII SOH) idbyte (defined Chapter Four) always ASCII i.e. 0x30 number data bytes varies tail byte (ASCII ETB)
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INTERFACES
Offset 0x28
MASK
Reset Value 0xXX00
5-15
Table Source Interrupt External event input occurred. Periodic pulse output occurred. Time coincidence strobe occurred. pulse second (1pps) output occurred. data packet available output FIFO. Reserved
interrupt source enabled writing mask corresponding that source. interrupt source disabled writing zero mask corresponding that source. Offset 0x2A INTSTAT Reset Value 0xXX00 INTSTAT register same basic structure MASK register. sets bits zero through four this register depending upon which interrupt source generated interrupt. INTSTAT register bits regardless state mask bits. This feature allows host poll occurrence interrupt sources. INTSTAT bits cleared writing INTSTAT register with corresponding bit(s) set.
WARNING transition INTSTAT from zero that causes interrupt generated (assuming that corresponding MASK set). INTSTAT register cleared host possible generate second interrupt. good programming practice clear INTSTAT register immediately after interrupts have been enabled.
Offset 0x2C VECTOR Reset Value 0xXX00 VECTOR register holds eight Status/ID byte that will return during interrupt acknowledge cycles VMEbus applications.
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Offset 0x2E LEVEL Reset Value 0xXX00 LEVEL register selects level which interrupt will generated. Only bits zero through used. These bits encoded follows: Level Disabled IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
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CHAPTER FOUR FIFO DATA PACKETS GENERAL Communication with performed using byte serial data packet protocol. packet bytes read from, written TFP, using D08(O) transfers offset 0x27 transfers offset 0x26. case transfer, only order byte used. packet structure defined Chapter Three, "OFFSET 0x26." WRITING DATA PACKETS following steps should followed when loading data packets TFP. Failure perform more these steps correctly common reason customer support calls. Write packet input FIFO. Clear register writing 0x01 register. Inform that input packet available writing 0x80 register. will register when packet processed.
When host sets seven register interrupt generated. service routine performs minimalist packet integrity checking. checks that first packet byte 0x01 (ASCII SOH). found, loads FIFO data into input buffer until byte value 0x17 (ASCII ETB) found. packet then processed accordance with idbyte value. When processing complete, sets zero register, clears input FIFO, resumes previous task. first packet byte, more than bytes read before encountering ETB, idbyte value invalid, then clears FIFO, clears zero register, resumes previous task.
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4.1.1 PACKET SELECT OPERATIONAL MODE This packet contains single data byte (zero through seven) which defines operational mode. mode saved battery backed RAM. modes enumerated below. Mode (Zero) Time Code Decoding Mode uses input timecode timing reference. packet time codes supported. Both modulated carrier level shift formats supported level shift supported 2137 codes). locks crystal oscillator input code rate. oscillator control range ±30PPM standard version, ±2PPM optional oven version. input code outside these limits, will exhibit periodic slips reference deviates from input source more than millisecond, forced jamsync performed). input code lost removed, will continue "flywheel" last known code rate. Typical accuracy five parts (two milliseconds drift hour). Mode Free Running Mode This mode virtually same Mode Without 1pps input runs last known oscillator frequency. Major time with packet. timebase adjusted with packet "D." Mode External Mode synchronizes signal 1pps input. Major time loaded with packet. acquisition range same described mode zero. Mode Real Time Clock Mode synchronizes onboard real time clock (RTC) major time also derived from clock battery backed. This mode recommended when using oven oscillator because accuracy high enough ensure that oven will able track with slippages. Mode (zero) description. Mode Digital Sync Mode This mode implemented. Mode Mode with Receiver Onboard (Obsolete) only supports this mode bc635VME/bc357VXI configuration. currently available only double wide form factor. Mode Mode with Receiver Located Antenna This optional mode available with bc637VME/bc357VXI configuration. described separate User's Guide.
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FIFO DATA PACKETS
Mode Diagnostic Default Setting Mode Initially this mode provided allow photographed. display loaded with static time 12:34:56. more battery backed parameters were added became useful this mode means setting battery backed data standard defaults. This data default values established mode seven follows, Table 4-1. Table Mode Default Values Description Operational Mode Reference Time Code Expected Modulated Time Code Expected Generates IRIG Path Selection Variable (See Packet) Local Time Offset (GPS Modes Only) VCXO Value (Nominally Centered) Leap Second Correction (Only Used Modes)
Variable Mode Time Code Format Gencode Path Local Accum Leapsec
Default Note IRIG Modulated IRIG 32000
diagnostic utility this mode resides fact that operator immediately determine host program communicating properly with simply observing display. borrow from classic K&R, make 12:34:56 appear "you have able create program text, compile find where your output went. With these mechanical details mastered, everything else comparatively easy." Note: bc635 defaults Mode (zero). bc637 defaults Mode
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4.1.2 PACKET MAJOR TIME Mode Mode only major time using this packet. likely that this packet would used other mode since other modes derive major time from timing reference signal. packet format follows: byte byte byte byte byte byte byte byte byte byte byte byte days hundreds days tens *days units (Jan defined 001) hours tens hours units minutes tens minutes units seconds tens seconds units
Note: data fields must ASCII format. *Day invalid time code IRIG time codes. desired, "Packet Path Selection." time loaded packet will used until second epoch following load. increments time before loading output buffer registers. time incremented approximately milliseconds into current frame, buffer registers loaded milliseconds into current frame. buffer registers transferred holding registers synchronously with 1pps output. time loaded packet should input well advance millisecond point frame, should reference current frame.
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FIFO DATA PACKETS
4.1.3 PACKET COMMAND INPUT This packet single data byte used direct take specific actions below. byte byte byte byte
(Definitions Below)
Used (Warm Start Early Software Versions) Software Reset vectors Power Reset Point Jamsynch Force Minor Time Zero Next 1pps Input Used (Jamsynch Lockout Early Software Versions) Load Current Time Real Time Clock Variables Dumps Battery Backed FIFO (Factory Only)
4.1.4 PACKET LOAD CONVERTER reference crystal oscillator voltage controlled using buffered output converter controlling voltage. Packet allows user directly load value converter. This feature would allow user fine tune time base free running mode. aware other this packet normal operation. Since this voltage routed connector allow external oscillators disciplined, would provide means devise frequency control algorithm independent TFP. format shown below. (See also path byte loaded packet.) byte byte byte byte byte byte byte
bits 12-15 bits 08-11 bits 04-07 bits 01-03
Note: data fields must ASCII format.
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4.1.5 PACKET HEARTBEAT (PERIODIC) CONTROL This packet establishes frequency output periodics. number output pulses defined following equation. 10,000,000 where output pulses second programmable number range 65535 programmable number range 65535 packet establishes value There byte qualifier associated with packet. This qualifier allows periodics asynchronous synchronous with respect 1pps epoch. synchronous format chosen must selected such that integer. duty cycle output waveform dependent particular values selected. Divider physically follows divider following example serves illustration. output frequency 500kHz. selected selected square wave output since last divider divide two. selected selected output waveform pulse train with tenth duty cycle. packet format follows: byte byte byte byte byte byte byte byte byte byte byte byte asynchronous synchronous bits 12-15 bits 08-11 bits 04-07 bits 00-03 bits 12-15 bits 08-11 bits 04-07 bits 00-03
(asynchronous) qualifier used then values same packet values five (synchronous) qualifier used, then values equal packet values m1+1 m2+1 respectively. example, synchronous 500KHz square wave desired then qualifier byte five, Additional insight into operation counter gained reading Intel documentation 82C54 integrated circuit. five qualifiers correspond Intel defined Modes
bc635VME/bc350VXI Time Frequency Processor (Rev.
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FIFO DATA PACKETS
periodic engine bc635/637VME consists sections INTEL 82C54 programmable interval timer connected serial configuration driven reference. Glue logic logic cell arrays supports both synchronous (with 1pps epoch) asynchronous operation. helpful (although essential) read INTEL data sheet 82C54. Packet allows user complete access serial counters using standard INTEL loading protocols. counter modes supported; 1pps synchronous asynchronous. responsibility user select appropriate mode. error checking performed bc635/637VME firmware. synchronous mode should only selected number output counts second integer. number counts second integer then asynchronous mode should used. number counts second always following form: (10,000,000) where: counts second Counter divide Counter divide range values Counter mode dependent follows. Asynchronous Mode: 65535 Synchronous Mode: 65535 WARNING Periodic heartbeat pulse/interrupt generation guaranteed synchronous mode when counter divide values used. modes operation accessed using standard INTEL mode identifiers. synchronous operation mode byte must ASCII "5." asynchronous operation mode byte must ASCII "2." packet format follows: byte byte byte byte byte byte byte byte byte SOH. "F." ASCII (asynch) (synch). ASCII bits 2-15). ASCII bits 8-11). ASCII bits 4-7). ASCII bits 0-3). ASCII bits 12-15). ASCII bits 8-11).
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byte byte byte
ASCII bits 4-7). ASCII bits 0-3). ETB.
IMPORTANT When Mode used, value produced 82C54 hardware n1+1 n2+1. This result INTEL designed 82C54, unrelated design. Example: desired implement 10000 counts second synchronous with 1pps. mode (synchronous) n1+1 n2+1 (10,000,000) 100) 10000 byte byte byte byte byte byte byte byte byte byte byte byte SOH. "F." (mode). "0." "0." "0." "0." "0." "6." 0x63). ETB.
Other values (n1+1) (n2+1) could have been used. example, (n1+1) (n2+1)
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FIFO DATA PACKETS
4.1.6 PACKET PROPOGATION OFFSET CONTROL frequently desired program offset into basic timekeeping functions relative reference input. example, reference input IRIG timecode, there significant cable delay between IRIG generator location. Packet allows this time difference removed inserting known amount offset between IRIG reference locations. offset programmable units hundred nanoseconds, positive negative. format shown below. byte byte byte byte byte byte byte byte byte byte byte advance retard millisecond hundreds millisecond tens millisecond units microsecond hundreds microsecond tens microsecond units nanosecond hundreds
IRIG scenario described above, positive offset should used.
WARNING offsets larger than microseconds used, then jamsynch feature must turned using packet "P." reason this requirement that under normal operation difference between reference time time detected greater than millisecond timbers "jammed" reference time that lengthy steering process avoided.
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4.1.7 PACKET TIMECODE FORMAT MODE Packet allows host select timecode format modulation type. packet format follows. timecode format modulation values maintained battery backed RAM. byte byte byte byte byte format modulation
Format Choices IRIG IRIG 2137 (XR3 with 100Hz symbol rate) NASA (25Hz symbol rate) Modulation Choices amplitude modulated sine wave Modulated supported IRIG pulse code modulation level shift) level shift supported 2137 codes. 4.1.8 PACKET CLOCK SOURCE SELECT Packet used select clock source TFP. uses frequency 10MHz timing functions. derived from VCXO supplied from external oscillator #C22. packet format follows. byte byte byte byte External Internal
power always defaults internal oscillator selection. This packet effect boards with Oven Oscillators 4.1.9 PACKET SEND DATA RECEIVER format content variations discussed separate User's Guide.
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FIFO DATA PACKETS
4.1.10 PACKET SELECT GENERATOR CODE timecode generated selected packet "K." Only options available described below. generator code type maintained battery backed RAM. byte byte byte byte code
Code Options generate IRIG amplitude modulated level shift generate IRIG level shift only 4.1.11 PACKET REAL TIME CLOCK This packet loads battery backed real time clock which used source major time 1pps epoch when mode three selected. format shown below. byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte years tens years units months tens months units (January month day-of-month tens day-of-month units hours tens hours units minutes tens minutes units seconds tens seconds units
data fields must ASCII format. need mode three when packet downloaded.
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4.1.12 PACKET LOCAL TIME OFFSET SELECT (GPS MODES ONLY) This packet allows time displayed with hour offset. This situation usually arises when source time (Universal Time Coordinated) format local time desired displayed. offset only applies hour's digits. This offset maintained battery backed RAM. format follows. byte byte byte byte byte byte sign hours tens hours units
hours range, from +12. positive sign used from prime meridian heading East, negative sign used from prime meridian heading West. example, Eastern Standard Time would relative UTC.
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FIFO DATA PACKETS
4.1.13 PACKET REQUEST DATA FROM This packet used request data from which available register interfaces. added "catch all" packet universal data transfer. This packet been created with very extensive format, additional data will made available customer needs suggestions addressed. primary purpose this packet allow user verify integrity programmed setup data. Note: user advised that repetitively issuing Packet cause excessive overhead disrupt time keeping. Currently three different data packets requested using packet. formats follows: Request Format byte byte byte byte Response Format Request Time (See Packet "L") byte byte (lower case letter) byte (zero) byte years tens byte years units byte months tens byte months units byte day-of-month tens byte day-of-month units byte hours tens byte hours units byte minutes tens byte minutes units byte seconds tens byte seconds units byte
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Response Format Request Current Value byte byte (lower case letter) byte byte bits 12-15 byte bits 08-11 byte bits 04-07 byte bits 00-03 byte Response Format Request Leap Seconds (Currently Specific) byte byte (lower case letter) byte byte leap second tens byte leap second units byte Response Format Request Year byte byte (lower case letter) byte byte years tens byte year units byte Response Format Request Year byte byte (lower case letter) byte byte years tens byte year units byte signals packet ready condition setting register. responsibility host clear this writing register with set.
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FIFO DATA PACKETS
4.1.14 PACKET PATH SELECTION path selection might better called switch branch selector. purpose this packet allow user exercise control over certain processes. path packet used download single byte. Each byte toggling action relative function. format described below. byte byte byte byte byte path upper nibble path lower nibble
Upper Nibble Definitions normal time format broadcast leap seconds FIFO echo Lower Nibble Definitions enable disciplining enable jamsynch leap year Accept
long second format (See Note.) broadcast packet each second ignore leap seconds FIFO echo
disable discipline disable jamsynch leap year invalid (default setting)
Note: Time through TIME4 contain atomic seconds since January 1980. only Mode. (See Table 4-2.) 4.1.14.1 LOWER NIBBLE DESCRIPTIONS Time Code mode (Mode sometimes desired 000. This invalid code IRIG time codes clearing this overrides normal checking allows board lock this otherwise invalid code. Chapter Three description TIME fields (offset 0x0C). Note: always January IRIG specifications. allow only those people that want this capability, testing purposes (many time-code generators start with 000), bothered extra year roll over.
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CHAPTER FOUR
During leap years this path must enable different counts which represent leap years. Note: Software versions later than 9501128 packet year then calculates leap year. this software leap year effect. Jamsynch method employed match output 1pps signal input time mark. change modes operation warmed unit want rush re-synchronizing enable jamsynch, then Packet force jamsynch unit, which will cause 1pps signal reset time-mark time. There disadvantages using this method. strobe scheduled time between flywheeling time jamsynch will missed jump time. There also break lock couple seconds. Jamsynchs ineffective cold unit that oscillator changing frequency high rate during warm Oscillator disciplining might disabled were using external clock source that requires different disciplining routine using on-board disciplining through Packet "D." 4.1.14.2 UPPER NIBBLE DESCRIPTIONS When enabled, packets written INPUT FIFO will automatically echoed OUTPUT FIFO. This used when want report time instead time. change that leap seconds added time derive UTC. When enabled, data automatically inserted into OUT-FIFO every second. This could useful have system that maintaining different times such local time. mode (Mode want report time seconds from start epoch (seconds from start January 1980). Some systems find easier deal with time strictly seconds. table below reflects that fields TIME1 TIME2 contain contiguous binary number representing Epoch seconds. minor time remains decimal sub-seconds reflected Table 4-2.
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FIFO DATA PACKETS
TIME0 Field TIME1 Field TIME2 Field TIME3 Field TIME4 Field
Table Time1 Time2 Fields 15-12 11-8 Defined. Defined. Status. Seconds. Seconds. Seconds. Seconds. Seconds. Seconds. 10E-1 Seconds. 10E-2 Seconds. 10E-3 Seconds. 10E-5 Seconds. 10E-6 Seconds. 10E-7 Seconds.
Unused. Seconds. Seconds. 10E-4 Seconds. Defined.
4.1.15 PACKET DISCIPLINING GAIN This packet allows gain sense disciplining process host bus. Originally this feature used Datum developmental purposes, would also indispensable anyone attempting discipline external oscillator using TFP. format follows. byte byte byte byte byte byte least significant nibble most significant nibble sense: positive, negative
4.1.16 PACKET YEAR This packet allows users year Modes This necessary leap year calculator function these modes. After writing year must wait least full second before reading back using packet. byte byte byte byte byte years tens years units
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CHAPTER FIVE PROGRAMMING EXAMPLES GENERAL example code fragments this chapter written programming language. examples have been tested Datum, should transportable most programming environments. system dependent base address defined below where "YYYY" indicates kbyte page memory used data "SSSS" indicates switch settings. #define BASE 0xYYYYSSSS
following definitions pertain FIFO data transfer. #define #define #define FIFO 0x01 0x17 (short*)(BASE+0x27)
following global variables also declared used throughout this chapter. short dummy, *readptr, time[5] long READING TIME DEMAND following example reads time from registers TIME0 through TIME4 loads this data into array time[ time latched reading TIMEREQ register, register assigned global variable. most cases assignment global avoids possibility that dummy read operation will removed optimizing compiler (beware). readptr (short*)(BASE 0x0A) dummy *readptr++ for(i=0 i++) time[i] *readptr++ initialize pointer latch time increment pointer read time registers
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EXTERNAL EVENT TIME CAPTURE This example sets event capture occur rising edge generate interrupt. time capture lockout mechanism also used. #define EVENT0 #define #define VECTOR #define MASK (short*) #define INTSTAT #define LEVEL #define UNLOCK INITIALIZE EVENT HARDWARE *CMD 0x09 *VECTOR 0x40 *LEVEL 0x03 *INSTAT 0x01 *MASK 0x01 enable event lockout interrupt vector interrupt level clear INSTAT enable interrupt (short*)(BASE+0x16) (short*)(BASE+0x24) (short*)(BASE+0x2C) (BASE+0x28) (short*)(BASE+0x2A) (short*)(BASE+0X2E) (short*)(BASE+0x20
INTERRUPT SERVICE ROUTINE FRAGMENT readptr EVENT0 for(i=0 i++) time[i] *readptr++; dummy *UNLOCK release capture lockout *INTSTAT 0x01 clear INSTAT
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PROGRAMMING EXAMPLES
PROGRAM PERIODIC FREQUENCY 1,000 This example uses generalized send_packet( function program 1,000 output periodic synchronized 1pps epoch. #define (short*)(BASE+0x22)
void send_packet(char *charptr) *FIFO while(*charptr) *FIFO *charptr++ load body packet *FIFO *ACK 0x81 command clear while(!(*ACK 0x01)) wait acknowledge CODE FRAGMENT WHICH SETS PERIODIC send_packet("F500630063") MODE MAJOR TIME This example selects free running mode sets major time, using packet. send_packet("A1") *INSTAT 0x08 while(!(*INSTAT 0x08) send_packet("B123112233") select mode clear INSTAT 1pps wait 1pps days through seconds 0x0063 (100-1)
SELECT MODE (IRIGB) ADVANCE MILLISECONDS following code fragment selects mode, timecode, offset. last packet used disable jamsynchs since required offset larger than microseconds. packet description additional details jamsynch function. send_packet("A0") send_packet("HB") send_packet("G+0025000") send_packet("P04") select mode select IRIGB timecode advance milliseconds disable jamsynchs
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CHAPTER INPUTS OUTPUTS INPUTS OUTPUTS front panel bc635VME bc350VXI (B-size) consists time status display, timecode input, timecode output, plug, socket. current time hr:min:sec displayed using seven segment digits. flywheeling, digit decimal points also illuminated. time display incremented milliseconds into current frame. (One customer measured radix point with photo diode reported that indeed early!) Timecode input using connector J1-7. Input amplitudes from volts peak peak accommodated. Timecode output connector J1-5. output amplitude adjustable using turn potentiometer located just below accessible with place. signals socket plug summarized Table following page.
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Table Socket Plug Signals Signals "DS" Signals "DP" Signal Signal *External 10MHz Input Ovenized RS-422 Rx(+) Oscillator Output Ground RS-422 Rx(-) Strobe Output RS-422 Tx(+) Output RS-422 Tx(-) Time Code Output (AM) Ground External Event Input Used Time Code Input 1pps Time Code Return RS-422 1pps+ Oscillator Control Output RS-422 1ppsNot Used Ground Time Code Output (DCLS) RS-422 Tx(-) Ground RS-422 Tx(+) 1,5,10 Output Used External 1pps Input Ground Periodics Output
output when optional ovenized oscillator installed.
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INPUTS OUTPUTS
Table Signals Connector Signals VMEbus Signal Time Code Input Time Code Return Time Code Output (DCLS) Time Code Output (AM) External Event Input Strobe Output Periodic Output External 1pps Input 1pps Output 1,5,10MHz Output (Note 10MHz Input Oscillator Control Output RS-422 Tx(+) Rx(+) RS-422 Tx(-) Rx(-) RS-422 Rx(-) (Note RS-422 Rx(+) (Note 1pps (Note Note: Hardware Rev. later.
Note Hardware Rev. later JP6.
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CHAPTER SEVEN ADJUSTMENTS GENERAL There only adjustments module, VR2. (See figure location these potentiometers.) TIME CODE PHASE LOCK LOOP ADJUSTMENT adjusts center frequency VCO, which locks carrier modulated input time code. This adjustment made factory rarely needs adjustment customer. This adjustment verified adjusted correctly using dual trace oscilloscope time code input. Mode (Packet "A") select appropriate time code format modulation type (Packet "H"). Connect channel oscilloscope (XR2212). Connect channel oscilloscope modulated input time code. Trigger oscilloscope channel input. Adjust that positive transition signal input channel centered positive crest input sine wave. negative transition should centered most negative part input sine wave. Figure below. Figure Phase Lock Loop Adjustment
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TIME CODE OUTPUT AMPLITUDE ADJUSTMENT adjusts amplitude modulated IRIG output time code. value volt common three volts peak-to-peak high cycles. Adjust this value suit equipment being driven. range zero twenty-four volts peak-to-peak.
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CHAPTER EIGHT REVISION HISTORY GENERAL This chapter summarizes hardware revisions compatibility issues. Part Number 11603 Revision This original hardware release. wiring error between data Maxim 7218C display driver data lines were inverted high order order sense. problem fixed rearranging bits firmware before downloading Maxim Revision Fixed wiring error Rev. Revision plug connector added allow Acutime antenna used. RJ11 connectors were removed. reference designators silk screen were reordered this time. Revision filter capacitors were added. These capacitors were parallel with other components previous revisions. Revision oven oscillator option added transformer coupling option removed. Additional signals were routed connector. pull down resistor added INTACK line prevent indeterminate state before LCA's loaded. board stiffener added. Revision Compliance testing prototype. Added filtering drivers pins 3,11,15. Revision wiring error. added remove 10Mhz signal from back plane. When properly terminated, this signal will radiate excess noise. Revision Replaced AD569JP with Exar MP7626JP.
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Part Number P100004 Revision Ruggedized board upgrade. Removed sockets U10, U15, U21, U23, U26, U28, U38. Changed layout that U12, U13, U22, U24, U25, U31, PLCC devices soldered board. Changed connectors from panel mount with leads mount. Deleted provisions TANS module. Added provisions that jumpers used instead switches SW2. Used surface mount devices where practical. Added provisions fixed resistors IRIG output amplitude instead VR1. Board D0-D7 data registers wired reverse. Installed special firmware version DT100015 reverse bits. Modified boards T8064 wiring layout problems. Revision Implemented T8064 wiring layout changes. Fixed D0-D7 data registers wired reverse problem. Board uses original 9501287 firmware. jumper block instead 1x3.
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CHAPTER NINE DRAWING GENERAL This chapter contains Schematic Diagram, Assembly Drawing, Parts List bc635VME/bc350VXI Time Frequency Processor.
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