CY7C373 UltraLogic64-Macrocell Flash CPLD Features macr

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CY7C373 UltraLogic64-Macrocell Flash CPLD Features macr

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CY7C373
UltraLogic64-Macrocell Flash CPLD
Features
macrocells four logic blocks pins dedicated inputs including clock pins Hold capabilities I/Os dedicated inputs hidden delays High speed fMAX Electrically alterable Flash technology Available 84-pin PLCC 100-pin TQFP packages compatible with CY7C374
Functional Description
CY7C373 Flash erasable Complex Programmable Logic Device (CPLD) part LASH370family high-density, high-speed CPLDs. Like members FLASH370 family, CY7C373 designed bring ease high performance 22V10 high-density CPLDs. macrocells CY7C373 divided between four logic blocks. Each logic block includes macrocells, product term array, intelligent product term allocator. logic blocks FLASH370 architecture connected with extremely fast predictable routing resource-the Programmable Interconnect Matrix (PIM). brings flexibility, routability, speed, uniform delay interconnect.
Logic Block Diagram
CLOCK INPUTS INPUTS
INPUT MACROCELLS I/Os I/O0-I/O15
INPUT/CLOCK MACROCELLS I/Os I/O48-I/O63
LOGIC BLOCK
LOGIC BLOCK
I/Os I/O16-I/O31
LOGIC BLOCK
LOGIC BLOCK
I/Os I/O32-I/O47
7C373-1
Selection Guide
7C373-125 Maximum Propagation Delay (ns) Minimum Set-up, (ns) Maximum Clock Output, (ns) Maximum Supply Commercial Current, (mA) Industrial
Shaded area contains preliminary information.
7C373-100
7C373-83
7C373-66
7C373L-66
Cypress Semiconductor Corporation
3901 North First Street
Jose
95134 408-943-2600 June 1992 Revised April 1998

CY7C373 UltraLogic64-Macrocell Flash CPLD Features macr

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