September 1998 WINCHIP 2PROCESSOR DATA SHEET This Version WinChip
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September 1998 WINCHIP 2PROCESSOR DATA SHEET
This Version WinChip Processor data sheet. latest versions this data sheet obtained from www.winchip.com
1998 Integrated Device Technology, Inc. Rights Reserved
Integrated Device Technology, Inc. reserves right make changes products without notice order improve design performance characteristics. This publication neither states implies representations warranties kind, including limited implied warranty merchantability fitness particular purpose. license, express implied, intellectual property rights granted this document. Centaur Technology, Inc. makes representations warranties with respect accuracy completeness contents this publication information contained herein, reserves right make changes time, without notice. Centaur Technology, Inc. disclaims responsibility consequences resulting from information included herein.
LIFE SUPPORT POLICY
Integrated Device Technology's products authorized components life support other medical devices systems (hereinafter life support devices) unless specific written agreement pertaining such intended executed between manufacturer officer IDT.
Life support devices devices which intended surgical implant into body support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. failure perform cause failure life support device system, affect safety effectiveness.
This policy covers component life support device system whose
WinChip, WinChip WinChip CentaurHauls trademarks Integrated Device Technology Corporation. AMD, K6-2 trademarks Advanced Micro Devices, Inc. Microsoft Windows registered trademarks Microsoft Corporation. Intel trademarks Intel Corporation. Pentium registered trademark Intel Corporation. Cyrix registered trademark Cyrix 6X86MX trademark Cyrix Corporation. Other product names used this publication identification purposes only trademarks their respective companies.
September 1998 WINCHIP 2PROCESSOR DATA SHEET
REVISION HISTORY
DATE VERSION REVISION
10/1998
Initial release
September 1998 WINCHIP PROCESSOR DATA SHEET
CONTENTS
REVISION HISTORY CONTENTS INTRODUCTION .1-1 Basic Features .1-1 Processor Versions .1-2 Competitive Comparisons .1-3 Compatibility .1-5 Data Sheet Assumptions.1-6
WINCHIP ARCHITECTURE .2-1 Introduction .2-1 Concepts.2-2 Component Summary.2-3 2.3.1 General Architecture .2-3 2.3.2 I-Cache .2-5 2.3.3 Translator Unit.2-5 2.3.4 Branch Prediction Unit.2-7 2.3.5 Execution Unit .2-7 2.3.6 D-Cache .2-8 2.3.7 Fetch Unit.2-8 2.3.8 Unit .2-9 2.3.9 Units .2-9 2.3.10 3DNow! Units .2-10 2.3.11 Unit .2-10
PROGRAMMING INTERFACE.3-1 General .3-1 Additional Functions.3-3 Machine-Specific Functions .3-3 3.3.1 General.3-3 3.3.2 Standard CPUID Instruction Functions.3-4 3.3.3 Extended CPUID Instruction Functions .3-7 3.3.4 Processor Identification .3-9 3.3.5 Value After Reset. .3-10 3.3.6 .3-11 3.3.7 Machine-Specific Registers.3-1
September 1998 WINCHIP PROCESSOR DATA SHEET
Omitted Functions .3-12 3.4.1 Pentium Appendix Enhancements .3-12 3.4.2 Other Functions.3-13
HARDWARE INTERFACE .4-1 Interface .4-1 4.1.1 Differences .4-1 4.1.2 Clarifications.4-3 4.1.3 Omissions.4-3 Signal Summary .4-4 Power Management .4-7 4.3.1 Static Power Management.4-7 4.3.2 Dynamic Power Management.4-7 Test Debug .4-7 4.4.1 Machine Check.4-7 4.4.2 BIST.4-8 4.4.3 Internal Error Detection .4-9 4.4.4 JTAG .4-9 4.4.5 Debug Port .4-9 ELECTRICAL SPECIFICATIONS .5-1 Timing Tables 100-MHz Bus.5-1 Timing Tables 83-MHz Bus.5-5 Timing Tables 75-MHz Bus.5-9 Timing Tables 66-MHz Bus.5-13 Timing Tables 60-MHz Bus.5-17 Specifications.5-21 5.6.1 Recommended Operating Conditions .5-21 5.6.2 Maximum Ratings .5-21 5.6.3 Characteristics .5-22 5.6.4 Power Dissipation.5-23
MECHANICAL SPECIFICATIONS .6-1 CPGA Package .6-1 PAckage .6-6
THERMAL SPECIFICATIONS.7-1 Introduction .7-1 Typical Environments.7-1 Measuring TC.7-1 Estimating TC.7-v
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Recommended Thermal Solutions .7-4 Contacts .7-5
APPENDIX MACHINE SPECIFIC REGISTERS General Category MSRs. 02h: (Pentium Processor Parity Reversal Register). 0Eh: TR12 (Pentium Processor Feature Control) 10h: (Time Stamp Counter) 11h: CESR (Control Event Select Register) 12h-13h: CTR0 CTR1 (Event Counters 107h: (Feature Control Register). 108h: FCR2 (Feature Control Register A-11 109h: FCR3 (Feature Control Register A-11 10Ah: FCR4 (Feature Control Register A-12 Memory Configuration Registers A-12 General A-12 Memory Configuration Registers A-13 Control Register. A-15 APPENDIX COMPATIBILITY. Introduction Compatibility Integer instruction Compatibility. Floating-Point Compatibility
September 1998 WINCHIP PROCESSOR DATA SHEET
INTRODUCTION
WinChip 2processor, designed Centaur Technology Inc., plug-compatible alternative Intel® Pentium® processor with MMXtechnology (also known informally P55C processor). addition Intel Pentium family, WinChip processor also directly competes with other ocket 7"compatible processors such K6-2TM, Cyrix® 6x86MXprocessors. WinChip processor family based unique Centaur-developed design approach manufactured with 0.35 0.25-micron CMOS technologies well 0.25-micron technology. These technologies provide highperformance, low-cost, low-power solutions desktop mobile personal computer market. When considered individually, function, performance, cost WinChip processor family very competitive. When considered whole, WinChip processor family offers breakthrough level value.
BASIC FEATURES
WinChip processor family comprises several versions. family versions share following common features:
Plug-compatible with Intel Pentium processor- bus, electrical interface, physical package ocket Software-compatible with Intel Pentium processors thousands software applications Software-compatible with Intel technology large (32-KB each) on-chip caches. large TLBs (128 entries each). Sophisticated branch prediction mechanism. units with superscalar execution. speeds (Super7bus). cost very small 0.25-micron technology) low-cost technology.
Notable Features
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Introduction
September 1998 WINCHIP PROCESSOR DATA SHEET
PROCESSOR VERSIONS
WinChip processor suitable both desktop mobile applications. These basic versions offered several internal speed ranges several different voltage settings.
WinChip
3DNow!instructions. These instructions compatible with 3DNow! instructions included K6-2 processor. These instructions provide significant performance improvements geometry lighting calculations. 3DNow! instructions directly utilized Microsoft' Direct3D version well many games. WinChip processor initially available several speed grades: (75-MHz bus), (60-MHz bus)
Speed Versions
(83-MHz bus) (66-MHz bus) bus) Future versions WinChip processor will provide other speed grades speed combinations. particular, will supported 233, MHz. WinChip processors initially support voltage ranges: 3.52V (3.45V-.6V) 3.3V (3.135V-.6V)
Voltage Versions
Future versions WinChip processor will support lower core voltages.
Introduction
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COMPETITIVE COMPARISONS
following tables summarize major features WinChip processor primary competitors. competitive information specified competitive processor' data sheets accurate only time this datasheet written. features those that characterize primary capabilities processor. Additional specifics WinChip processor design found Chapter major themes this summary are:
WinChip processor equivalent better cache capabilities. These critical system performance modern operating systems applications. (See Table 1-1) WinChip processor generally simpler internal architecture than competitors. However, WinChip selectively implements advanced features like superscalar execution branch prediction. This design approach results good performance with small size (See Table 1-2) WinChip processor much smaller size more basic technology. This small size benefits user facilitating price (See Table 1-3)
Table 1-1. Cache Characteristics.
INTEL MAJOR FEATURES I-Cache Size Data Ways D-Cache Size Data Ways Size Ways Page Cache WINCHIP entries assoc /128 6x86MX assoc unified cache direct CYRIX
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Table 1-2. Microarchitecture Characteristics.
MAJOR FEATURES Decode General MMX/3D Issue Execute MMX/3D Branch Prediction Call/Return Stack WINCHIP Inst In-order Insts In-order Single In-order Insts In-order entries entries Insts In-order insts Out-order Insts Out-order INTEL Insts In-order Insts In-order CYRIX 6x86MX Insts In-order
Table 1-3. Technology Size
MAJOR FEATURES Technology Metal Poly WINCHIP 0.35µ 0.28µ 0.26µ Size (0.28µ)
INTEL 0.25µ
K6-2 0.25µ
CYRIX 6x86MX 0.25µ
5LM+LI
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COMPATIBILITY
WinChip processor compatible with Intel Pentium processor with technology. WinChip processor plug into existing Pentium processor-based desktop portable system boards operate without requiring changes system hardware. some cases, special BIOS needed (due possible BIOS Pentium processor-unique machine specific registers). Currently, BIOS support WinChip processor available from Award, AMI, Phoenix, SystemSoft. WinChip processor does provide Pentiumcompatible dual processing (neither mobile Pentium processor, K6-2 processors, Cyrix 6x86MX processor). Note that processors developed processors) have some differences low-level functions. (These include differences between various Intel processors between Intel processors equivalent Cyrix processors.) WinChip processor similar differences. Centaur performed extensive testing hundreds boards, peripherals, software applications, operating systems confirm WinChip processor' compatibility. Indicative this compatibility, WinChip processor XXCAL Inc. Platinum Certification (their highest compatibility rating) will soon obtain Windows Windows certification.
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DATA SHEET ASSUMPTIONS
WinChip processor specifications directly based upon Pentium processor's external specifications defined publicly available Intel publications, actual behavior (derived from testing) Pentium processor. This data sheet book provides only minimal descriptions these Pentium-compatible functions. major emphasis this document describe differences from explicit implicit (behavioral) Pentium specifications. intent these specifications make easy board designer, system designer, BIOS developer utilize WinChip processor place Pentium processor Pentium processor with technology. (This, course, makes trivially easy end-user able exploit advantages WinChip processor.) assume that reader potential direct user WinChip processor thus familiar with specifications Pentium processor. Table lists some relevant documents that define reference architecture. Table 1-4. Architecture Specification Documents
DOCUMENT TITLE Intel Architecture Software Developer's Manual, Vol. Intel Architecture Software Developer's Manual, Vol. Intel Architecture Software Developer's Manual, Vol. Pentium Processor Family Developer's Manual Pentium Processor with Technology Pentium Processor Specification Update INTEL ORDER 243190 243191 243192 241428 243185 242480 VERSION
Introduction
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September 1998 WINCHIP PROCESSOR DATA SHEET
WINCHIP ARCHITECTURE
INTRODUCTION
WinChip processor externally (bus software) compatible with Intel Pentium processor with Technology. However, internal architecture design WinChip processor very different from that Pentium processor other contemporary processors such Cyrix 6x86MX processors. WinChip processor uses unique design approach that provides significant benefits end-user. This design approach provides high performance cost power using unique architecture that includes large onchip caches extensively optimized target environment. resulting WinChip processor smaller (die size only 0.25µ geometry technology) than other processor comparable performance most recent processors. Philosophically, WinChip processor' internal design return same basic concepts RISC design that allowed microprocessor performance breakthroughs 1980' Recently, however, contemporary processors have followed different path using very complex internal designs employing advanced architecture concepts such superscalar execution, out-of-order instruction execution, reorder buffers, non-blocking caches, forth (these terms found datasheets competitive products). Unfortunately, while these advanced technical concepts make good technical reading, real bottom-line benefit that they provide end-user been limited; especially when considering resultant large chip sizes (resulting high costs) high power consumption. such advanced technical hocus-pocus found WinChip processor merely offers good compatibility with good performance, cost, power consumption.
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CONCEPTS
concepts underlying WinChip processor design are:
Simple instructions (load, store, branch, ALU) dominate instruction execution time. This basic RISC design concept, which also true architecture: over instructions executed come from these basic categories. course, imple" instructions more complex than corresponding RISC architecture instructions. WinChip processor optimizes performance these types basic instructions while minimizing hardware provided other little-used functions. little-used instructions primarily implemented microcode with minimal hardware support.
Memory performance limiting performance factor. high ratio internal clock speed versus relatively limited processor-bus speed, off-chip memoryaccess performance primary factor processor performance opposed internal instruction execution performance). WinChip processor addresses this phenomenon providing very large on-chip caches TLBs that high internal processor clock frequency. addition, sophisticated cache management algorithms included further reduce activity.
Optimize design target user environment. WinChip processor implements very specific detailed design tradeoffs provide high performance with cost. Minimal hardware provided functions that heavily used that critical performance target environments (low-end desktop mobile systems). These design optimizations based extensive detailed analysis actual behavior Windows operating systems applications Small beautiful. WinChip processor highly optimized small physical size logic transistors. addition obvious cost benefits, this small size provides secondary benefits power consumption improved reliability.
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COMPONENT SUMMARY 2.3.1 General Architecture
Figure illustrates basic components WinChip processor. Fundamentally, WinChip processor' internal design classic five-stage integer pipeline execution core with additional instruction translation stage translate instructions coming from fetch stage into internal microinstruction format. Fetching translating instructions asynchronous internal execution pipeline. Integer floating-point instructions issued executed time program order. 3DNow! instructions paired issued executed time. instructions executed retired order. Cache misses stall pipeline until data available requesting instruction. spite this basic micro-architecture, WinChip processor achieves high performance through several mechanisms:
Good highly used instructions. WinChip processor implements specific design features reduce number cycles heavily used instructions including complex functions such protect-mode segment-register loads string instructions. Very large fast on-chip caches TLBs. These reduce wait component system performance, which equal processor-running component. Lots fine-tuning low-level optimizations. This includes such items fast unaligned data access fewer pipeline interlocks than Pentium processor. Issue execution pairing instructions that benefit significantly from dual execution. This feature, like others, highly tuned application code.
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Stage Fetch
I-TLB
I-Cache
Inst Buffer Prediction X86-To-Microcode Translator Queue Trap Addr Inst Parms Immed Data
Unit
Internal Insts
Decode Address D-Cache Access Execute Writeback 3DNow!
Address
D-TLB
D-Cache
BFRS
Figure 2-1. WinChip Processor Data Flow
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2.3.2 I-Cache
I-cache contains organized two-way associative with 32-byte lines. replacement algorithm used. associated I-TLB contains entries organized 8-way associative with 7-bit pseudo-LRU replacement algorithm. This large cache one-clock access time operates high clock frequencies WinChip processor. I-TLB utilizes 8-entry unified page directory cache that significantly reduces miss penalty. addition, Icache control logic includes several innovative features that minimize cache invalidates unnecessary fetches. opposed many other contemporary processors, data I-cache exactly what came from bus; that there idden" pre-decode bits. This facilitates provision large cache capacity small physical size. I-cache dynamically turned when used reduce power requirements.
2.3.3 Translator Unit
I-cache unit delivers bytes clock instruction buffer translator unit. translator converts instructions internal instruction data forms. Assuming that instruction instruction buffer start cycle, translator translates entire instruction clock. Instruction prefixes other than require additional translator cycle each prefix. However, asynchronous fetch "ookahead" capability translator, these extra cycles prefixes rarely result bubble execution pipeline. translator also translate 3DNow! instructions each clock. airing" rules allowed combinations similar those Pentium processor 3DNow! K6-2 processor. output translator internal micro-instruction stream perform instruction function, immediate data fields from instruction, various state information used control execution (for example, operand size). internal instruction stream instruction consist micro-instructions directly generated translator, micro-instructions from on-chip (microcode), both. performance-sensitive instructions, there delay access micro-code from ROM. Chapter Architecture
September 1998 WINCHIP PROCESSOR DATA SHEET
microcode capacity larger than most microcode ROMs allow more unimportant (relative performance) functions performed microcode (versus hardware), allow extensive self-test microcode, allow extensive builtin debugging aids (for processor design debug). Instruction fetch translator operation made asynchronous from micro-instruction execution three-entry translatedinstruction queue between translator execution unit. Each entry contains three internal instructions corresponding instruction. Most performance-critical instructions represented these three generated instructions. This queue allows translator "ook-ahead"and continue translating instructions even though execution unit stalled busy with microcode sequence. translator also overlap generation multiple internal instructions with translating prefixes subsequent instruction.
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2.3.4 Branch Prediction Unit
WinChip advanced branch prediction mechanisms. These predict branch target address whether branch taken during translator stage (X). branch target address displacement branches directly calculated while branch instruction stage. target address fetched from I-cache during next cycle. This direct calculation target address eliminates need large branch target buffer (BTB) such found Pentium processor. prediction direction conditional branches performed state-of-the-art mechanism. 12-bit global branch history combined with branch address index dynamically updated branch history table (BHT) with entries. entry predicts whether conditional branch direction will agree with default direction guess translator. translator guess accurate leading overall prediction accuracy over 90%. addition, Return instructions accurately predicted 8-entry Return-address stack.
2.3.5 Execution Unit
Internal micro-instructions executed tightly coupled four-stage pipeline that very similar structure basic RISC pipeline:
Decode stage (R): Micro-instructions decoded, integer register files accessed, resource dependencies evaluated, forth. Addressing stage (A): Memory addresses calculated sent cache units. WinChip processor capable calculating most instruction address forms clock; forms containing registers shifted index register require clocks. Branches (x86 microcode) also resolved Astage. fast forwarding mechanism allows EFLAGS result instruction front conditional branch D-stage) resolve conditional branches A-stage. Resolving branches A-stage means that mispredicted, predicted, branch causes only three clock stall.
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Execute stage (D): Integer operations load accesses D-cache performed. basic registerregister functions take clock except multiply divide. Load-ALU Load-ALU-store sequences require only clocks; operation store combined. During this stage floating-point, 3DNow! execution units access their registers. These execution units off"the main execution unit that load-ALU operations these units pipelined clock.
Write-back stage (W): results operations committed registers store data written Dcache external write buffers.
Although pipeline structure similar non-x86 processors, micro-instructions associated execution units highly tuned architecture. micro-instructions closely resemble corresponding instructions. Examples specialized hardware features supporting architecture are: hardware handling condition codes, segment descriptor decode manipulation instructions, hardware automatically save floating-point environment, forth.
2.3.6 D-Cache
D-cache very similar I-cache (except setassociativity): organized four-way associative with 32-byte lines. 3-bit pseudo-LRU replacement algorithm used. associated D-TLB contains entries organized 8way associative with 7-bit pseudo-LRU replacement algorithm. This large cache one-clock access time designed operate high clock frequencies WinChip processor. D-TLB shares 8-entry unified page directory cache which reduces miss penalty. D-cache dynamically turned when used reduce power requirements.
2.3.7 Fetch Unit
instruction fetch unit manages fetching instructions I-TLB entries from delivering instructions from I-cache. implements mart" instruction prefetch mechanism minimize wasted cycles.
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2.3.8 Unit
addition integer execution unit, WinChip processor separate 80-bit floating-point execution unit that execute floating-point instructions parallel with integer instructions. floating-point unit designed maximize clock frequency minimize chip size while providing good floating-point performance typical desktop use. unit fully pipelined start floating-point multiply each clock. WinChip processor issues only instruction clock into main instruction pipeline. However, once hardwired floating point instruction (load, store, add, multiply, divide, square root, etc.) reaches unit, following integer instructions execute parallel with floating-point instruction. Certain little-used complex floating point instructions (sin, atan, etc.) integer instruction pipeline thus cannot overlapped with integer execution. floating-point unit dynamically turned when used reduce power requirements.
2.3.9 Units
WinChip processor contains separate execution units MMX-compatible instructions. instructions issued executed each clock (using same pairing rules Pentium processor). Each unit contains adder logic functions. unit multiplier-adder other shifter/packer. multiplier(-adder) fully pipelined start multiply[-add] instruction (which consists four separate multiplies) every clock. units share hardware with 3DNow! units such that clock only 3DNow! instructions executed. Architecturally, registers same floatingpoint registers. However, there actually different register files (one FP-unit units) that kept synchronized hardware. unit dynamically turned when used reduce power requirements.
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2.3.10
3DNow! Units
WinChip processor contains separate execution units 3DNow! instructions. These instructions compatible with K6-2 processor 3DNow! instructions provide performance assists graphics transformations SIMD single-precision floating-point capabilities. 3DNow! instructions issued executed each clock. Each instruction operates single precision floating-point numbers. 3DNow! unit single-precision floating-point multipliers. other unit single-precision floatingpoint adders. Other functions such conversions, reciprocal, reciprocal square root provided appropriate unit. multiplier adder fully pipelined start 3DNow! multiply instruction (which consists separate multiplies) 3DNow! instruction (which consists separate adds) every clock.
2.3.11 Unit
WinChip processor unit provides external interface compatible with Pentium processor. addition expected control functions, unit implements eight-entry page-directory cache reduce impact misses. Four 64-bit write buffers allow internal execution proceed overlapped with waiting external stores complete. WinChip processor unit contains many special features designed reduce traffic cache disruption. Examples include store byte-combining function (optional), cache cast-out snarfing, mart lock" management mechanisms, weak-read ordering (optional), forth. optional features controlled memory range registers that allow different address-space regions have different characteristics. WinChip supports speeds MHz. compatible with Super7 architecture. initial version WinChip supports only integer ratios frequency core frequencies. subsequent version will support fractional ratios.
2-10
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PROGRAMMING INTERFACE
GENERAL
general, WinChip processor compatible with both software-visible architecture Intel Pentium processor with technology. That program that executes Pentium processor should generally execute WinChip processor produce same results (with exceptions noted this datasheet). WinChip processor' Pentium-compatible functions include:
basic instructions, registers, functions floating-point (numeric processor) instructions, registers functions Pentium processor instructions registers
(CMPXCHG8B, RDMSR, WRMSR, RDTSC, CPUID, RSM, CR4)
basic operating modes: real mode, protect mode, virtual8086 mode System Management Interrupt (SMI) associated System Management Mode (SMM) interrupt exception functions debug functions (including breakpoint function) input/output functions tasking functions (TSS, task switch, etc.) Processor initialization behavior
WinChip processor, addition instructions, also includes instructions boost performance graphics compatible with AMD-3D Technology.
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However, there some differences between WinChip processor Pentium processor. These differences fall into four groups:
Additional WinChip processor functions. Examples memory range registers that allow different attributes each range. These additional functions provided through Machine Specific Registers such that compatibility affected. Implementation-specific differences. Examples cache testing features, performance monitoring features that expose internal implementation features. These types functions incompatible among different implementations.- including Intel486, Pentium, Pentium processors. Omitted functions. Some Pentium processor functions provided WinChip processor because they aren' used aren' needed targeted systems. Examples some specific functions such functional redundancy checking performance monitoring. These types differences similar those among various versions Pentium processor (for example, mobile Pentium processor also omits same functions omitted WinChip processor), among AMD-K6 Cyrix 6x86MX processors.
Low-level behavioral differences. low-level WinChip processor functions different from Pentium because results documented Intel documentation undefined, known different different implementations particular, different among Intel i486, Pentium, Pentium processors). That compatibility with Pentium processor these functions clearly needed software compatibility they wouldn' different across different implementations). Where Pentium Pentium processor results differ, WinChip processor often provides Pentium result.
This chapter summarizes first three types differences: additional functions, implementation-specific functions, omitted functions. Appendix contains more details machine-specific functions. Appendix contains details lowlevel differences.
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some areas, also include comparative information about Pentium Pro, AMD-K6, Cyrix 6x86MX processors. This information taken from data sheets these products been verified Centaur Technology. Pentium processor information, however, based detailed testing.
ADDITIONAL FUNCTIONS
WinChip processor provides some memory range management functions. These similar concept, different specifics, memory range registers Pentium Pro, AMD-K6, Cyrix 6x86MX processors (all which different from each other). These functions provided Machine Specific Registers. Appendix provides specifics WinChip Machine Specific Registers. Note that there differences specifics memory range management between WinChip predecessor, WinChip WinChip processor supports extended CPUID functions, defined AMD. WinChip processor also includes instructions boost performance graphics compatible with AMD-3D Technology
MACHINE-SPECIFIC FUNCTIONS 3.3.1 General
processor implementations provide variety machinespecific functions. Examples cache testing features, performance monitoring features that expose internal implementation features. These types functions different incompatible among different implementations- including Intel i486, Pentium, Pentium processors, between these processors competitive processors from Cyrix AMD. Intel documentation clearly identifies these types functions machine-specific warns possible changes implementations. This section describes WinChip processor machinespecific functions that most likely used software compares them related processors where applicable. Appendix describes WinChip processor machine-specific registers (MSRs). This section covers those features Pentium-compatible processors that used commonly identify control processor features. Pentium-compatible processors have same mechanisms, bit-specific data values often differ.
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3.3.2 Standard CPUID Instruction Functions
CPUID instruction available contemporary processors. CPUID instruction standard functions requested register. first function returns vendor identification string registers EBX, EDX. second CPUID function returns assortment bits that identify chip version describe specific features available. EAX:EBX:ECX:EDX return values instruction executed with are: Table
REGISTER[BITS] MEANING (highest input value understood CPUID) EBX:EDX:ECX (vendor string) WINCHIP
CPUID
"Centaur Hauls"
"Genuine Intel"
"Genuine Intel"
"Authentic AMD"
"Cyrix Instead"
return values CPUID instruction executed with are: Table 3-EAX BITS MEANING Stepping Model Same return value after Reset (see next section) WINCHIP
11:8 Family 13:12 Type
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return values CPUID instruction with are: Table
BITS MEANING present VM86 Extensions (VME) Debugging Extensions Page Size Extensions (4MB) Time Stamp Counter (TSC) supported Model Specific Registers present supported Function) Machine Check Exception CMPXCHG8B instruction APIC supported 10:11 -Reserved Memory Range Registers Global supported Machine Check Architecture supported Conditional Move supported 16:22 Reserved supported 24:31 Reserved WINCHIP NOTES
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Notes CPUID Feature Flags General: /y"entry means that default setting this (and underlying function) using MSR. These ppendix H"functions provided WinChip processor since they used target operating systems. They also provided Cyrix 6x86MX processor. WinChip processor implementation varies slightly from that Pentium processor that should have practical impact. Every system different MSRs- addresses contents. This function introduced with Pentium processor generally provided Pentiumcompatible processors. Machine Check exception defined Intel documentation machine-specific. WinChip processor' Machine Check slightly different specifics than Pentium processor' Machine Check function. Machine Check support enabled disabled MSR. CPUID reports current setting this enable control. Pentium processor-compatible CMPXCHG8B instruction provided always enabled. However, default corresponding CPUID function (due found Windows NT). This default changed MSR. This Intel-specific multiprocessing function. None other Pentium-compatible processors provide this function since utility target system environment. WinChip Cyrix 6x86MX processors have memory range registers, specifics compatible with MRRs. Pentium processor memory range registers.
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WinChip processor' MMX-technology compatible instruction support enabled disabled FCR. CPUID reports current setting this enable control.
3.3.3 Extended CPUID Instruction Functions
WinChip processor supports extended CPUID functions similar those provided AMD-K6 Cyrix GXm. These functions provide additional information about WinChip Extended CPUID functions requested executing CPUID with value range 0x80000000 through 0x80000005. WinChip CPUID instruction aliases values range 0xC0000000 through 0xC0000005 extended functions range 0x80000000 through 0x80000005 (there guarantee that this will true future processors. following table summarizes extended CPUID functions.
80000000 TITLE Largest Extended Function Input Value Processor Signature Feature Flags OUTPUT EAX=80000005 EBX,ECX,EDX=Reserved EAX=Processor Signature EBX,ECX=Reserved EDX=Extended Feature Flags 80000002 80000003 80000004 80000005 Processor Name String Processor Name String Processor Name String Cache Information EAX,EBX,ECX,EDX EAX,EBX,ECX,EDX EAX,EBX,ECX,EDX Reserved Information Data Cache Information Instruction Cache Information
80000001
Largest Extended Function Input Value (EAX==0x80000000)
Returns 0x80000005 EAX, largest extended function input value.
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Processor Signature Feature Flags (EAX==0x80000001)
Returns processor version information EAX, this value identical value after RESET. Returns feature flags EDX, this value identical value after CPUID standard function with exception EDX[31]=0 3DNow! instructions supported. EDX[31]=1 3DNow! instructions supported. Note that FCR[20]=0 then AMD-3D instructions supported EDX[31] will
Processor Name String (EAX==0x80000002-0x80000004)
Returns name processor, suitable BIOS display screen (ASCII). string characters length. string shorter, rightmost characters padded with zero. leftmost characters EAX, then EBX, ECX, EDX. leftmost character goes least significant byte (little endian). example, string WinChip 2-3D would returned extended function EAX=0x80000002 follows: 0x20544449 0x436E6957 0x20706968 0x44332D32 Since string exactly bytes, extended functions EAX=0x80000003 EAX=0x80000004 return zero EAX, EBX, ECX, EDX. Note that FCR[20] then AMD-3D instructions supported extended function EAX=0x80000002 returns WinChip
Cache Information (EAX 0x80000005)
Returns information about implementation TLBs caches.
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REGISTER EBX[31:24] EBX[23:16] EBX[15: EBX[ ECX[31:24] ECX[23:16] ECX[15: ECX[ EDX[31:24] EDX[23:16] EDX[15: EDX[
DESCRIPTION Reserved Information D-TLB associativity D-TLB entries I-TLB associativity I-TLB entries Data Cache Information Size (Kbytes) Associativity Lines Line Size (bytes) Instruction Cache Information Size (Kbytes) Associativity Lines Line Size (bytes)
VALUE
3.3.4 Processor Identification
WinChip processor provides several machine-specific features. Some these features compatible with those provided identified standard CPUID function EAX=1. Other machine-specific features described this datasheet have equivalent. These features controlled WinChip MSRs. Some these features backwardcompatible with predecessor WinChip System software must assume that future processors WinChip family will implement same machine-specific features even that these features will implemented backward-compatible manner. order determine processor supports particular machine-specific features, system software should follow following procedure.
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Identify processor member WinChip family checking Vendor Identification String entaurHauls" using CPUID with EAX=0. Once this been verified, system software must determine processor version order properly configure machine-specific registers. particular some control fields memory configuration registers were redefined WinChip There ways distinguishing between WinChip predecessor, WinChip system software only concerned with programming memory configuration registers, then read MCR_CTRL register inspect Trait Mode field (MCR_CTRL[19:17]). WinChip later versions processor family Trait Mode must written Trait Mode control field (MCR_CTRL[8:6]) order activate memory configuration registers. general system software determine processor version comparing Family Model Identification fields returned CPUID standard function EAX=1. processor version recognized then system software must attempt activate machine-specific feature. following table indicates interpret results both methods.
FAMILY MODEL TRAIT MODE MCR_CTRL[19:17] PROCESSOR VERSION WinChip appropriate datasheet. WinChip this datasheet
3.3.5 Value After Reset.
other processors, after reset register holds component identification number follows:
31:14 Reserved 13:12 Type 11:8 Family Model Stepping
specific values various WinChip processor types are:
PROCESSOR TYPE FAMILY MODEL STEPPING
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WinChip WinChip
Varies Varies
comparison, following values other processors:
PROCESSOR P54C Cyrix 6x86MX AMD-K6 TYPE FAMILY MODEL STEPPING Varies Varies Varies Varies
3.3.6
Control register (CR4) feature Pentium processor that controls some advanced features. WinChip processor provides with following specifics:
BITS MEANING VME: Enables feature PVI: Enables feature TSD: Makes RDTSC inst privileged Enables breakpoints PSE: Enables 4-MB pages PAE: Enables addr extensions MCE: Enables machine check exception PGE: Enables global page feature PCE: Enables RDPMC levels 31:9 reserved
CHIP
NOTES
Notes Chapter Programming Interface 3-11
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General: /1"means that default setting this (1). "means that always cannot set. "means that this reserved. appears when read, exception signaled attempt made write this bit. WinChip processor does provide this ppendix function this cannot set. However, exception occurs attempt made this bit. Cyrix 6x86MX processor also does provide this function. This Pentium-Pro processor function that typically provided P55-compatible processor. WinChip processor Machine Check slightly different specifics than P54C Machine Check function
3.3.7 Machine-Specific Registers
WinChip processor implements Pentium family concept Machine Specific Registers (MSRs). RDMSR WRMSR instructions provided CPUID instruction identifies that WinChip processor supports MSRs. However, WinChip processor MSRs different from Pentium Pentium processors (which different from each other, from Cyrix 6x86MX AMD-K6 processors). general, MSRs have usefulness application operating system software used. (This expected since MSRs different each processor). Appendix contains detailed description WinChip processor' MSRs.
OMITTED FUNCTIONS
This section summarizes those functions that included some Pentium processor versions, WinChip processor.
3.4.1 Pentium Appendix Enhancements
infamous Appendix functions those Pentium functions that documented Appendix (Advanced Functions) Volume Pentium Processor Family Developer's Manual. 3-12 Programming Interface Chapter
September 1998 WINCHIP PROCESSOR DATA SHEET
Unfortunately, Appendix only available those with ppropriate non-disclosure agreements place" However, most these functions publicly documented Pentium processor documentation. Appendix features identified ptional future specifically identified being supported CPUID instruction. limited utility these advanced functions (they complex operating system functions), there programs that utilize these features. particular, these functions either used all, conditionally used present, Microsoft desktop operating systems. WinChip processor does provide following Appendix functions.
Virtual Memory Enhancements (4-MB Pages).
These Pentium processor enhancements provide ability optionally define 4-MB virtual memory pages addition usual 4-KB page size. feature identification return from CPUID instruction indicates whether this feature present not. This enhancement provided WinChip processor since used target operating systems: Windows Windows Note that this function also provided Cyrix 6x86MX processor.
Virtual-8086 Mode Enhancements (VME)
These Pentium processor enhancements provide potential performance improvements mode-switching operations while operating VM86 mode. feature identification return from CPUID instruction indicates whether this feature present not. This enhancement provided WinChip processor since used target Microsoft operating systems. Note that this function also provided Cyrix 6x86MX processor.
3.4.2 Other Functions
WinChip processor also omits software interface Intel-proprietary symmetric multiprocessing support: APIC. This function omitted since target market WinChip processor portables typical desktop systems (which support APIC multiprocessing).
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feature identification return from CPUID instruction indicates whether this feature present not. This enhancement provided WinChip processor mobile Pentium processor AMDK6 Cyrix 6x86MX processors).
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HARDWARE INTERFACE
INTERFACE
WinChip processor interface compatible with Pentium processor Pentium processor with technology. This behavior specified Pentium Processor Family Developer's Manual. majority pins within interface involved with physical memory interface. These pins this interface perform same functions Pentium processor. remaining pins power ground pins, test debug support pins various ancillary control functions. Most these pins identical Pentium processor. Others associated with functions that behave slightly differently from Pentium processor WinChip processor. Still others behave differently among various versions Pentium processor, thus require clarification WinChip processor. Lastly there several Pentium processor functions which completely omitted WinChip
4.1.1 Differences
areas where WinChip processor differs from Pentium processor anticipated cause operational compatibility issues. These differences are:
Frequency Control Machine Check Exceptions BUSCHK# PEN# Drive Strengths Probe Mode JTAG Port (see Test Debug Section)
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Frequency Control
Like other Socket processors, WinChip processor derives internal clock frequency multiplying external clock based levels pins deassertion RESET. Unlike other Socket processors, WinChip does support fractional frequency multiples. Otherwise supported integer frequency multiples compatible with multiples supported Supported clock ratios shown Table 4-1. WinChip pulls three pins that default multiplier. Table 4-1. Frequency Ratios
WINCHIP CLOCK RATIO reserved reserved reserved reserved CLOCK RATIO 5/2x 7/2x 9/2x 11/2x
Machine Check Exceptions BUSCHK# PEN#
Pentium processor, BUSCHK# interrupt causes Machine Check exception ignored based CR4.MCE. difference that semantics Machine Check exception slightly different WinChip processor from Pentium processor WinChip processor doesn' save report address cycle data). section further description Machine Check.
Drive Strength
Desktop Pentium processors have three driver strengths that selected Reset certain pins (for example ADS#). driver strength selected BRDYC# BUSCHK# pins when sampled RESET deassertion
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WinChip processor only driver strengths: Table 4-2. Drive Strengths
BUSCHK# BRDYC# WINCHIP DRIVER Medium Medium Typical Typical P54C DRIVER Strong Medium Typical Typical
Only ADS#, A[20:3], HITM# W/R# configurable. other drivers typical strength. characteristics both drive strengths described Chapter Electrical Specifications.
4.1.2 Clarifications
Power Supply Voltage
WinChip processor operates with unified power plane. Depending version, processor requires either Volts 3.52 Volts inputs. WinChip package compatible with Socket that VCC2DET# internally no-connected. Flexible socket motherboards fact that VCC2DET# internally connected force motherboard core regulators produce same voltage.
Tolerance
Like P55, WinChip processor' input Volt tolerant. should driven Volt device.
4.1.3 Omissions
Advanced Peripheral Interrupt Controller (APIC)
APIC supported WinChip APIC pins (PICCLK, PICD0, PICD1) classified reserved, should connected motherboard. (The APIC also supported mobile Pentium processor, Cyrix 6x86MX AMD-K6 processors.)
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Dual Processor Interface
WinChip processors support dual processor interface. associated pins (D/P#, PBGNT#, PBREQ#, PHIT#, PHITM#) classified reserved, should connected motherboard. (The interface also supported mobile Pentium processor, Cyrix 6x86MX K6.)
Functional Redundancy Checking Mode
WinChip processors support functional redundancy checking mode. FRCMC# classified reserved, should connected motherboard (The functional redundancy checking mode also supported mobile Pentium processors, Pentium processors with technology, Cyrix 6x86MX.)
Breakpoint Performance Monitoring Signals
WinChip processors internally support instruction data breakpoints. However, WinChip does support Pentium processor' external indication breakpoint matches BP3-BP0 pins. Similarly, WinChip contains performance monitoring hooks internally, does support Pentium processor' external indication performance monitoring events PM1-PM0. associated pins unconnected WinChip package.
SIGNAL SUMMARY
Table summarizes interface signals Pentium which signals provided WinChip processor: each processor' column indicates that supported that processor.
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Table 4-3. Signal Summary
SIGNAL TYPE (TCP) A20M# A31-A3 ADS# ADSC# AHOLD APCHK# APICEN/PICD1 BE7#-BE0# APICID[3:0] BF[2:0] BOFF# BP[3:2] PM/BP[1:0] BRDY# BRDYC# BREQ BUSCHK# CACHE# CPUTYP D/C# D63-D0 D/P# DP7-DP0 DPEN# PICD0 EADS# EWBE# FERR# FLUSH# FRCMC# HIT# HITM# HLDA HOLD
(PPGA)
P54C (TCP)
P54C (PPGA)
WINCHIP (CPGA)
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SIGNAL
TYPE
(TCP)
(PPGA)
P54C (TCP)
P54C (PPGA)
WINCHIP (CPGA)
IERR# IGNNE# INIT KEN# INTR LOCK# M/IO# PBGNT# PBREQ# PCHK# PEN# PHIT# PHITM# PICCLK PRDY R/S# RESET SCYC SMI# SMIACT# STPCLK# TRST# VCC2DET# W/R# WB/WT#
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POWER MANAGEMENT
WinChip processor provides both static dynamic power management.
4.3.1 Static Power Management
WinChip processor supports five power management modes Pentium processor: NORMAL state, STOP CLOCK state, STOP GRANT state, STOP CLOCK SNOOP state, AUTOHALT state. These described Pentium Family Developer's Manual.
4.3.2 Dynamic Power Management
WinChip processor uses dynamic power management techniques reduce power consumption NORMAL state. NORMAL state, on-chip arrays, selected datapaths, associated control logic powered down when use.
TEST DEBUG 4.4.1 Machine Check
WinChip Processors provide Machine Check exception function (INT that slightly different than Pentium processor Pentium processor Machine Check function (which different from each other, course). These differences reasonable expected since Intel documentation specifies that Machine Check architecture processor-specific. both Pentium processor WinChip processor, Machine Check exception must enabled setting CR4. enabled, conditions (below) causing Machine Check ignored processor action taken. Both WinChip processor Pentium processor cause Machine Check, enabled, when:
BUSCHK# asserted PEN# asserted data parity error detected (PCHK# asserted)
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differences between WinChip processor Pentium processor are:
Pentium processor reports specifics about cycle MSR' WinChip processor does provide this bus-cycle data. WinChip processor default behavior internally detected processor errors (like Pentium processor) assert IERR# (normally) perform Shutdown cycle. However, EMCIE set, then internal errors WinChip processor cause Machine Check exception.
4.4.2 BIST
Built-in Self Test (BIST) requested part WinChip processor reset sequence using exactly same mechanism used Pentium processor (INIT asserted RESET deasserted). WinChip processor BIST performs following general functions:
hardware-implemented exhaustive test internal microcode ROM, instruction decode, instruction generation entry point generation logic. extensive microcode test internal registers datapaths. extensive microcode test data instruction caches, their tags, associated TLB'
BIST requires about million internal clocks.
Value After Reset
results BIST indicated code EAX. Normally zero after reset. BIST requested part Reset sequence, contains BIST results. after BIST Reset means that failures were detected. value other than zero indicates error occurred during BIST.
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4.4.3 Internal Error Detection
During normal execution, WinChip processor detects parity errors both caches. addition, certain "mpossible" internal states detected microcode. These errors normally reported same mechanism Pentium processor: IERR# signal asserted (normally) Shutdown occurs. (The Shutdown suppressed both processors control MSR.) Alternatively, optional feature control MSR) allows internal errors reported Machine Check exceptions.
4.4.4 JTAG
WinChip processor JTAG scan interface which used test functions proprietary Debug Port. However, unlike Pentium processor, WinChip processor does provide fully compatible IEEE 1149.1 JTAG function. From practical user viewpoint, JTAG does exist associated pins (TCK, forth) should used.
4.4.5 Debug Port
Pentium processor (and other processors such AMDK6) have proprietary Debug Port which uses JTAG scan mechanism control internal debug features robe mode". These interfaces documented available all) only under non-disclosure agreement. Similarly, WinChip processor undocumented proprietary debug interface.
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ELECTRICAL SPECIFICATIONS
TIMING TABLES 100-MHZ
Table 5-1. Clock Switching Characteristics 100-Mhz
SYMBOL PARAMETER Frequency Period High Time Time Fall Time Rise Time Period Stability 0.15 0.15 ±250 UNIT 0.8V 2V-0.8V 2V-0.8V FIGURE NOTES
Table 5-2. Output Delay Timings 100-Mhz
SYMBOL PARAMETER A[31:3] Valid Delay A[31:3] Float Delay ADS# Valid Delay ADS# Float Delay ADSC# Valid Delay ADSC# Float Delay Valid Delay Float Delay APCHK# Valid Delay BE#[7:0] Valid Delay BE#[7:0] Float Delay BREQ Valid Delay CACHE# Valid Delay CACHE# Float Delay D/C# Valid Delay D/C# Float Delay D[63:0] Valid Delay D[63:0] Valid Delay DP[7:0] Valid Delay DP[7:0] Float Delay UNIT FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
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SYMBOL
PARAMETER FERR# Valid Delay HIT# Valid Time HITM# Valid Time HLDA Valid Time LOCK# Valid Time LOCK# Float Time M/IO# Valid Time M/IO# Float Time Valid Time Float Time PCHK# Valid Time Valid Time Float Time SCYC Valid Time SCYC Float Time SMIACT# Valid Time W/R# Valid Time W/R# Float Time
UNIT
FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
Notes:
outputs glitch free signals, guaranteed rise fall monotonically when driven into capacitive loads. Most system loads must treated transmission lines. Depending length transmission line, loading impedance mismatches, signal rise fall monotonically given point along transmission line.
Table 5-3. Input Setup Hold Timings 100-Mhz
SYMBOL PARAMETER A[31:5] Setup Time A[31:5] Hold Time A20M# Setup Time A20M# Hold Time AHOLD Setup Time AHOLD Hold Time Setup Time Hold Time BOFF# Setup Time BOFF# Hold Time UNIT FIGURE NOTES
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SYMBOL
PARAMETER BRDY# Setup Time BRDY# Hold Time BRDYC# Setup Time BRDYC# Hold Time D[63:0] Read Data Setup Time D[63:0] Read Data Hold Time DP[7:0] Read Data Setup Time DP[7:0] Read Data Hold Time EADS# Setup Time EADS# Hold Time EWBE# Setup Time EWBE# Hold Time FLUSH# Setup Time FLUSH# Hold Time HOLD Setup Time HOLD Hold Time IGNNE# Setup Time IGNNE# Hold Time INIT Setup Time INIT Hold Time INTR Setup Time INTR Hold Time Setup Time Hold Time KEN# Setup Time KEN# Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time STPCLK# Setup Time STPCLK# Hold Time WB/WT# Setup Time WB/WT# Hold Time
UNIT
FIGURE NOTES
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Notes:
These level-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks.
Table 5-4. RESET Configuration Signals 100-Mhz
SYMBOL t100 t101 t102 PARAMETER RESET Setup Time RESET HoldTime RESET Pulse Width, Stable RESET Active After Stable BF0, BF1, Setup Time BF0, BF1, Hold Time BRDYC# Hold Time BRDYC# Setup Time BRDYC# Hold Time FLUSH# Setup Time FLUSH# Hold Time FLUSH# Setup Time FLUSH# Hold Time UNIT CLK's CLK's CLK's CLK's CLK's CLK's Power FIGURE NOTES
Notes:
sampled specific clock edge, setup hold times must relative clock edge which RESET signal first sampled negated sampled asynchronously, signals must stable cycles before remain until cycles after deassertion RESET. BF[2:0] pins must remain stable least before negation RESET. RESET driven synchronously, BRDYC# must meet specified hold time relative negation RESET.
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TIMING TABLES 83-MHZ
Table 5-5. Clock Switching Characteristics 83-Mhz
SYMBOL PARAMETER Frequency Period High Time Time Fall Time Rise Time Period Stability 0.15 0.15 ±250 UNIT 0.8V 2V-0.8V 2V-0.8V FIGURE NOTES
Table 5-6. Output Delay Timings 83-Mhz
SYMBOL PARAMETER A[31:3] Valid Delay A[31:3] Float Delay ADS# Valid Delay ADS# Float Delay ADSC# Valid Delay ADSC# Float Delay Valid Delay Float Delay APCHK# Valid Delay BE#[7:0] Valid Delay BE#[7:0] Float Delay BREQ Valid Delay CACHE# Valid Delay CACHE# Float Delay D/C# Valid Delay D/C# Float Delay D[63:0] Valid Delay D[63:0] Valid Delay DP[7:0] Valid Delay DP[7:0] Float Delay FERR# Valid Delay HIT# Valid Time UNIT FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
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SYMBOL
PARAMETER HITM# Valid Time HLDA Valid Time LOCK# Valid Time LOCK# Float Time M/IO# Valid Time M/IO# Float Time Valid Time Float Time PCHK# Valid Time Valid Time Float Time SCYC Valid Time SCYC Float Time SMIACT# Valid Time W/R# Valid Time W/R# Float Time
UNIT
FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
Notes:
outputs glitch free signals, guaranteed rise fall monotonically when driven into capacitive loads. Most system loads must treated transmission lines. Depending length transmission line, loading impedance mismatches, signal rise fall monotonically given point along transmission line.
Table 5-7. Input Setup Hold Timings 83-Mhz
SYMBOL PARAMETER A[31:5] Setup Time A[31:5] Hold Time A20M# Setup Time A20M# Hold Time AHOLD Setup Time AHOLD Hold Time Setup Time Hold Time BOFF# Setup Time BOFF# Hold Time BRDY# Setup Time BRDY# Hold Time UNIT FIGURE NOTES
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SYMBOL
PARAMETER BRDYC# Setup Time BRDYC# Hold Time D[63:0] Read Data Setup Time D[63:0] Read Data Hold Time DP[7:0] Read Data Setup Time DP[7:0] Read Data Hold Time EADS# Setup Time EADS# Hold Time EWBE# Setup Time EWBE# Hold Time FLUSH# Setup Time FLUSH# Hold Time HOLD Setup Time HOLD Hold Time IGNNE# Setup Time IGNNE# Hold Time INIT Setup Time INIT Hold Time INTR Setup Time INTR Hold Time Setup Time Hold Time KEN# Setup Time KEN# Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time STPCLK# Setup Time STPCLK# Hold Time WB/WT# Setup Time WB/WT# Hold Time
UNIT
FIGURE NOTES
Notes:
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September 1998 WINCHIP PROCESSOR DATA SHEET
These level-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks.
Table 5-8. RESET Configuration Signals 83-Mhz
SYMBOL t100 t101 t102 PARAMETER RESET Setup Time RESET HoldTime RESET Pulse Width, Stable RESET Active After Stable BF0, BF1, Setup Time BF0, BF1, Hold Time BRDYC# Hold Time BRDYC# Setup Time BRDYC# Hold Time FLUSH# Setup Time FLUSH# Hold Time FLUSH# Setup Time FLUSH# Hold Time UNIT CLK's CLK's CLK's CLK's CLK's CLK's Power FIGURE NOTES
Notes:
sampled specific clock edge, setup hold times must relative clock edge which RESET signal first sampled negated sampled asynchronously, signals must stable cycles before remain until cycles after deassertion RESET. BF[2:0] pins must remain stable least before negation RESET. RESET driven synchronously, BRDYC# must meet specified hold time relative negation RESET.
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TIMING TABLES 75-MHZ
Table 5-9. Clock Switching Characteristics 75-Mhz
SYMBOL PARAMETER Frequency Period High Time Time Fall Time Rise Time Period Stability 0.15 0.15 ±250 UNIT 0.8V 2V-0.8V 2V-0.8V FIGURE NOTES
Table 5-10. Output Delay Timings 75-Mhz
SYMBOL PARAMETER A[31:3] Valid Delay A[31:3] Float Delay ADS# Valid Delay ADS# Float Delay ADSC# Valid Delay ADSC# Float Delay Valid Delay Float Delay APCHK# Valid Delay BE#[7:0] Valid Delay BE#[7:0] Float Delay BREQ Valid Delay CACHE# Valid Delay CACHE# Float Delay D/C# Valid Delay D/C# Float Delay D[63:0] Valid Delay D[63:0] Valid Delay DP[7:0] Valid Delay DP[7:0] Float Delay FERR# Valid Delay HIT# Valid Time UNIT FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
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SYMBOL
PARAMETER HITM# Valid Time HLDA Valid Time LOCK# Valid Time LOCK# Float Time M/IO# Valid Time M/IO# Float Time Valid Time Float Time PCHK# Valid Time Valid Time Float Time SCYC Valid Time SCYC Float Time SMIACT# Valid Time W/R# Valid Time W/R# Float Time
UNIT
FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
Notes:
outputs glitch free signals, guaranteed rise fall monotonically when driven into capacitive loads. Most system loads must treated transmission lines. Depending length transmission line, loading impedance mismatches, signal rise fall monotonically given point along transmission line.
Table 5-11. Input Setup Hold Timings 75-Mhz
SYMBOL PARAMETER A[31:5] Setup Time A[31:5] Hold Time A20M# Setup Time A20M# Hold Time AHOLD Setup Time AHOLD Hold Time Setup Time Hold Time BOFF# Setup Time BOFF# Hold Time BRDY# Setup Time BRDY# Hold Time UNIT FIGURE NOTES
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SYMBOL
PARAMETER BRDYC# Setup Time BRDYC# Hold Time D[63:0] Read Data Setup Time D[63:0] Read Data Hold Time DP[7:0] Read Data Setup Time DP[7:0] Read Data Hold Time EADS# Setup Time EADS# Hold Time EWBE# Setup Time EWBE# Hold Time FLUSH# Setup Time FLUSH# Hold Time HOLD Setup Time HOLD Hold Time IGNNE# Setup Time IGNNE# Hold Time INIT Setup Time INIT Hold Time INTR Setup Time INTR Hold Time Setup Time Hold Time KEN# Setup Time KEN# Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time STPCLK# Setup Time STPCLK# Hold Time WB/WT# Setup Time WB/WT# Hold Time
UNIT
FIGURE NOTES
Notes:
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Electrical Specifications
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These level-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks.
Table 5-12. RESET Configuration Signals 75-Mhz
SYMBOL t100 t101 t102 PARAMETER RESET Setup Time RESET HoldTime RESET Pulse Width, Stable RESET Active After Stable BF0, BF1, Setup Time BF0, BF1, Hold Time BRDYC# Hold Time BRDYC# Setup Time BRDYC# Hold Time FLUSH# Setup Time FLUSH# Hold Time FLUSH# Setup Time FLUSH# Hold Time UNIT CLK's CLK's CLK's CLK's CLK's CLK's Power FIGURE NOTES
Notes:
sampled specific clock edge, setup hold times must relative clock edge which RESET signal first sampled negated sampled asynchronously, signals must stable cycles before remain until cycles after deassertion RESET. BF[2:0] pins must remain stable least before negation RESET. RESET driven synchronously, BRDYC# must meet specified hold time relative negation RESET.
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TIMING TABLES 66-MHZ
Table 5-13. Clock Switching Characteristics 66-Mhz
SYMBOL PARAMETER Frequency Period High Time Time Fall Time Rise Time Period Stability 0.15 0.15 ±250 UNIT 0.8V 2V-0.8V 2V-0.8V FIGURE NOTES
Table 5-14. Output Delay Timings 66-Mhz
SYMBOL PARAMETER A[31:3] Valid Delay A[31:3] Float Delay ADS# Valid Delay ADS# Float Delay ADSC# Valid Delay ADSC# Float Delay Valid Delay Float Delay APCHK# Valid Delay BE#[7:0] Valid Delay BE#[7:0] Float Delay BREQ Valid Delay CACHE# Valid Delay CACHE# Float Delay D/C# Valid Delay D/C# Float Delay D[63:0] Valid Delay D[63:0] Valid Delay DP[7:0] Valid Delay DP[7:0] Float Delay FERR# Valid Delay HIT# Valid Time 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 UNIT FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
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SYMBOL
PARAMETER HITM# Valid Time HLDA Valid Time LOCK# Valid Time LOCK# Float Time M/IO# Valid Time M/IO# Float Time Valid Time Float Time PCHK# Valid Time Valid Time Float Time SCYC Valid Time SCYC Float Time SMIACT# Valid Time W/R# Valid Time W/R# Float Time
10.0
UNIT
FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
10.0
10.0
10.0
10.0
10.0
Notes:
outputs glitch free signals, guaranteed rise fall monotonically when driven into capacitive loads. Most system loads must treated transmission lines. Depending length transmission line, loading impedance mismatches, signal rise fall monotonically given point along transmission line.
Table 5-15. Input Setup Hold Timings 66-Mhz
SYMBOL PARAMETER A[31:5] Setup Time A[31:5] Hold Time A20M# Setup Time A20M# Hold Time AHOLD Setup Time AHOLD Hold Time Setup Time Hold Time BOFF# Setup Time BOFF# Hold Time BRDY# Setup Time BRDY# Hold Time UNIT FIGURE NOTES
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SYMBOL
PARAMETER BRDYC# Setup Time BRDYC# Hold Time D[63:0] Read Data Setup Time D[63:0] Read Data Hold Time DP[7:0] Read Data Setup Time DP[7:0] Read Data Hold Time EADS# Setup Time EADS# Hold Time EWBE# Setup Time EWBE# Hold Time FLUSH# Setup Time FLUSH# Hold Time HOLD Setup Time HOLD Hold Time IGNNE# Setup Time IGNNE# Hold Time INIT Setup Time INIT Hold Time INTR Setup Time INTR Hold Time Setup Time Hold Time KEN# Setup Time KEN# Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time STPCLK# Setup Time STPCLK# Hold Time WB/WT# Setup Time WB/WT# Hold Time
UNIT
FIGURE NOTES
Notes:
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These level-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks.
Table 5-16. RESET Configuration Signals 66-Mhz
SYMBOL t100 t101 t102 PARAMETER RESET Setup Time RESET HoldTime RESET Pulse Width, Stable RESET Active After Stable BF0, BF1, Setup Time BF0, BF1, Hold Time BRDYC# Hold Time BRDYC# Setup Time BRDYC# Hold Time FLUSH# Setup Time FLUSH# Hold Time FLUSH# Setup Time FLUSH# Hold Time UNIT CLK's CLK's CLK's CLK's CLK's CLK's Power FIGURE NOTES
Notes:
sampled specific clock edge, setup hold times must relative clock edge which RESET signal first sampled negated sampled asynchronously, signals must stable cycles before remain until cycles after deassertion RESET. BF[2:0] pins must remain stable least before negation RESET. RESET driven synchronously, BRDYC# must meet specified hold time relative negation RESET.
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TIMING TABLES 60-MHZ
Table 5-17. Clock Switching Characteristics 60-Mhz
SYMBOL PARAMETER Frequency Period High Time Time Fall Time Rise Time Period Stability 0.15 0.15 ±250 UNIT 0.8V 2V-0.8V 2V-0.8V FIGURE NOTES
Table 5-18. Output Delay Timings 60-Mhz
SYMBOL PARAMETER A[31:3] Valid Delay A[31:3] Float Delay ADS# Valid Delay ADS# Float Delay ADSC# Valid Delay ADSC# Float Delay Valid Delay Float Delay APCHK# Valid Delay BE#[7:0] Valid Delay BE#[7:0] Float Delay BREQ Valid Delay CACHE# Valid Delay CACHE# Float Delay D/C# Valid Delay D/C# Float Delay D[63:0] Valid Delay D[63:0] Valid Delay DP[7:0] Valid Delay DP[7:0] Float Delay FERR# Valid Delay HIT# Valid Time 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 10.0 UNIT FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
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SYMBOL
PARAMETER HITM# Valid Time HLDA Valid Time LOCK# Valid Time LOCK# Float Time M/IO# Valid Time M/IO# Float Time Valid Time Float Time PCHK# Valid Time Valid Time Float Time SCYC Valid Time SCYC Float Time SMIACT# Valid Time W/R# Valid Time W/R# Float Time
10.0
UNIT
FIGURE NOTES (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2) (1,2)
10.0
10.0
10.0
10.0
10.0
Notes:
outputs glitch free signals, guaranteed rise fall monotonically when driven into capacitive loads. Most system loads must treated transmission lines. Depending length transmission line, loading impedance mismatches, signal rise fall monotonically given point along transmission line.
Table 5-19. Input Setup Hold Timings 60-Mhz
SYMBOL PARAMETER A[31:5] Setup Time A[31:5] Hold Time A20M# Setup Time A20M# Hold Time AHOLD Setup Time AHOLD Hold Time Setup Time Hold Time BOFF# Setup Time BOFF# Hold Time BRDY# Setup Time BRDY# Hold Time UNIT FIGURE NOTES
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SYMBOL
PARAMETER BRDYC# Setup Time BRDYC# Hold Time D[63:0] Read Data Setup Time D[63:0] Read Data Hold Time DP[7:0] Read Data Setup Time DP[7:0] Read Data Hold Time EADS# Setup Time EADS# Hold Time EWBE# Setup Time EWBE# Hold Time FLUSH# Setup Time FLUSH# Hold Time HOLD Setup Time HOLD Hold Time IGNNE# Setup Time IGNNE# Hold Time INIT Setup Time INIT Hold Time INTR Setup Time INTR Hold Time Setup Time Hold Time KEN# Setup Time KEN# Hold Time Setup Time Hold Time Setup Time Hold Time Setup Time Hold Time STPCLK# Setup Time STPCLK# Hold Time WB/WT# Setup Time WB/WT# Hold Time
UNIT
FIGURE NOTES
Notes:
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These level-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must asserted minimum pulse width clocks. These edge-sensitive signals asserted synchronously asynchronously. sample specific clock edge, setup hold times must met. asserted asynchronously, they must have been negated least clocks prior assertion must remain asserted least clocks.
Table 5-20. RESET Configuration Signals 60-Mhz
SYMBOL t100 t101 t102 PARAMETER RESET Setup Time RESET HoldTime RESET Pulse Width, Stable RESET Active After Stable BF0, BF1, Setup Time BF0, BF1, Hold Time BRDYC# Hold Time BRDYC# Setup Time BRDYC# Hold Time FLUSH# Setup Time FLUSH# Hold Time FLUSH# Setup Time FLUSH# Hold Time UNIT CLK's CLK's CLK's CLK's CLK's CLK's Power FIGURE NOTES
Notes:
sampled specific clock edge, setup hold times must relative clock edge which RESET signal first sampled negated sampled asynchronously, signals must stable cycles before remain until cycles after deassertion RESET. BF[2:0] pins must remain stable least before negation RESET. RESET driven synchronously, BRDYC# must meet specified hold time relative negation RESET.
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SPECIFICATIONS 5.6.1 Recommended Operating Conditions
Functional operation WinChip processor guaranteed conditions Table met. Sustained operation outside recommended operating conditions damage device. Table 5-21. Recommended Operating Conditions
PARAMETER Operating Case Temperature Voltage (3.3 Voltage (VRE) High Level Input Voltage level input voltage High level output current (typical drive strength) High level output current (medium drive strength) level output current (typical drive strength) level output current (medium drive strength) -16.0 VOL(max) -8.0 VOL(max) 16.0 VOH(min) 3.135 3.45 -0.3 UNITS VOH(min) NOTES
5.6.2 Maximum Ratings
While functional operation guaranteed beyond operating ranges listed Table 5-4, device subjected limits specified Table without causing long-term damage. These conditions must imposed device sustained period- such sustained imposition damage device. Likewise exposure conditions excess maximum ratings damage device.
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Table 5-22. Maximum Ratings
PARAMETER Operating Case Temperature Storage Temperature Supply Voltage (VCC) Voltage -0.5 -0.5 VCC(max) UNITS NOTES
5.6.3 Characteristics
Table 5-23. Characteristics
PARAMETER High Level Output Voltage (typical drive strength) High Level Output Voltage (medium drive strength) Level Output Voltage (typical drive strength) Level Output Voltage (medium drive strength) Input Leakage Current Input Leakage Current inputs with pull-ups Input Leakage Current inputs with pull-downs -400 -16mA -8mA 16mA UNITS NOTES
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5.6.4 Power Dissipation
Tables 5-24 5-25 give power consumption voltage ranges supported WinChip Table 5-24. Power Consumption (0.25µM)@ 3.52V
PARAMETER Normal Mode Operating Current StopGrant AutoHalt Mode Operating Current StopClock Mode Operating Current Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts 12.0 13.0 14.0 15.0 16.0 Watts Watts Watts Watts Watts snooping activity UNITS NOTES
Note: above power consumption preliminary based 70°C case 3.52Volts.
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Table 5-25. Power Consumption (0.25µM) 3.3V
PARAMETER Normal Mode Operating Power StopGrant AutoHalt Mode Operating Power StopClock Mode Operating Power Watts Watts Watts Watts Watts Watts Watts Watts Watts Watts 10.0 10.5 10.9 11.8 Watts Watts Watts Watts Watts snooping activity UNITS NOTES
Note: above power consumption preliminary based 70°C case Volts.
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MECHANICAL SPECIFICATIONS
WinChip processor packaged 296-pin ceramic grid array (CPGA).
CPGA PACKAGE
WinChip processor' CPGA package mechanically compatible with Intel' ceramic plastic staggered grid array (SPGA PPGA) packages. Intel' Pentium Processor Family Developer's Manual, comparison. Figure 6-1. CPGA Pinout (Pinside View)
ADSC# BREQ IERR# BRDY# KEN# TRST# EWBE# WB/WT# INIT IGNNE# PEN# BOFF# PCHK# APCHK# PRDY HOLD SMI# INTR R/S# HLDA ADS# LOCK# EADS# W/R# BE6# VCCDET# HITM# BUSCHK# BE0# HIT# A20M# BE2# BE4# SCYC FLUSH#
D/C#
BE1#
BE3#
BE5#
BE7#
RESET
SMIACT#
BRDYC#
AHOLD
CACHE# M/IO#
WinChip CPGA PINOUT (PINSIDE VIEW)
STPCLK#
FERR#
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Figure 6-2. CPGA Pinout (Top Side View)
TRST# FERR# IERR# STPCLK# SMI# INIT HOLD WB/WT# M/IO# IGNNE# INTR R/S# PRDY APCHK# FLUSH# W/R# EADS# ADSC# BREQ
SCYC
BE6#
BE4#
BE2#
BE0# BUSCHK# HITM# A20M# HIT#
VCCDET#
RESET
BE7#
BE5#
BE3#
BE1#
D/C# ADS# HLDA
LOCK#
SMIACT#
PCHK#
PEN#
BOFF#
BRDYC#
BRDY#
WinChip CPGA PINOUT (TOP SIDE VIEW)
KEN#
EWBE#
AHOLD
CACHE#
Table 6-1. CPGA Cross Reference
Address
Name AL-35 AM-34 AK-32 AN-33 AL-33 AM-32 AK-30 AN-31 AL-31 AL-29 AK-28
Data
Name K-34 G-35 J-35 G-33 F-36 F-34 E-35 E-33 D-34 C-37 C-35
Control
Name A20M# ADS# ADSC# AHOLD APCHK# BE0# BE1# BE2# BE3# BE4# AK-08 AJ-05 AM-02 V-04 AK-02 AE-05 AL-09 AK-10 AL-11 AK-12 AL-13
Test
Name TRST# M-34 N-35 N-33 P-34 Q-33
Reserved
H-34 J-33 L-35 Q-03 Q-35 R-04 S-03 S-05 Y-35 AA-03 AC-03
A-37 R-34 S-33 S-35 W-33 AL-19 AN-01 AN-35 A-03 B-02 C-01 A-07 A-09 A-11 A-13 A-15 A-17 A-19 A-21 A-23 A-25 A-27 B-06 B-08 B-10 B-12 B-14 B-16 B-18 B-20 B-22 B-24 B-26
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Address
Name AL-27 AK-26 AL-25 AK-24 AL-23 AK-22 AL-21 AF-34 AH-36 AE-33 AG-35 AJ-35 AH-34 AG-33 AK-36 AK-34 AM-36 AJ-33
Data
Name B-36 D-32 B-34 C-33 A-35 B-32 C-31 A-33 D-28 B-30 C-29 A-31 D-26 C-27 C-23 D-24 C-21 D-22 C-19 D-20 C-17 C-15 D-16 C-13 D-14 C-11 D-12 C-09 D-10 D-08 A-05 E-09 B-04 D-06 C-05 E-07 C-03 D-04 E-05
Control
Name BE5# BE6# BE7# BOFF# BRDY# BRDYC# BREQ BUSCHK# CACHE# D/C# EADS# EWBE# FERR# FLUSH# HIT# HITM# HLDA HOLD IERR# IGNNE# INIT INTR KEN# LOCK# M/IO# AK-14 AL-15 AK-16 Y-33 X-34 W-35 Z-04 X-04 Y-03 AJ-01 AL-07 U-03 AK-18 AK-04 D-36 D-30 C-25 D-18 C-07 F-06 F-02 N-05 AM-04 W-03 Q-05 AN-07 AK-06 AL-05 AJ-03 AB-04 P-04 AA-35 AA-33 AD-34 U-05 W-05 AH-04 T-04 Y-05
Test
Name
Reserved
AD-04 AE-03 AE-35
AN-03 AN-05 H-34 J-33 L-35 Q-35 Y-35 A-29 E-37 G-01 G-37 J-01 J-37 L-01 L-33 L-37 N-01 N-37 Q-01 Q-37 S-01 S-37 T-34 U-01 U-33 U-37 W-01 W-37 Y-01 Y-37 AA-01 AA-37 AC-01 AC-37 AE-01 AE-37 AG-01 AG-37 AN-09 AN-11 AN-13 AN-15 AN-17 AN-19 AN-21 AN-23 B-28 H-02 H-36 K-02 K-36 M-02 M-36 P-02 P-36 R-02 R-36 T-02 T-36 U-35 V-02 V-36 X-02 X-36 Z-02 Z-36 AB-02 AB-36 AD-02 AD-36 AF-02 AF-36 AH-02 AJ-37 AL-37 AM-08 AM-10 AM-12 AM-14 AM-16 AM-18 AM-20 AM-22 AM-24 AM-26
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Address
Name
Data
Name D-02 F-04 E-03 G-05 E-01 G-03 H-04 J-03 J-05 K-04 L-05 L-03 M-04 N-03
Control
Name PCHK# PEN# PRDY RESET R/S# SCYC SMI# SMIACT# STPCLK# W/R# WB/WT# VCC2DET# AC-33 AG-05 AF-04 Z-34 AC-05 AL-03 AK-20 AC-35 AL-17 AB-34 AG-03 V-34 AM-06 AA-05 AL01
Test
Name
Reserved
AN-25 AN-27 AN-29 AM-28 AM-30 AN-37
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Table 6-2. CPGA Dimensions
WinChip (Top Side View)
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Table 6-3. CPGA Package Dimensions
MILLIMETERS Symbol 0.69 3.31 0.43 49.28 45.59 2.29 3.05 1.52 2.54 0.84 3.81 0.51 49.78 45.85 2.79 3.30 Lead Count Notes 0.027 0.130 0.017 1.940 1.795 0.090 0.120 0.060 0.100 INCHES 0.033 0.150 0.020 1.960 1.805 0.110 0.130 Lead Count Notes
PACKAGE
WinChip provided 320-pin package. Further details obtained through sales representative.
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THERMAL SPECIFICATIONS
INTRODUCTION
WinChip specified operation with device case temperatures range 70°C. Operation outside this range will result functional failures potentially damage device. Care must taken ensure that case temperature remains within specified range times during operation. effective heat sink with adequate airflow therefore requirement during operation.
TYPICAL ENVIRONMENTS
Typical thermal solutions involve three components: heatsink, interface material between heatsink package, source airflow. best thermal solutions rely three components. extent that these components used, other components must improved compensate such omission. particular, interface material such thermal grease, silicone paste, graphite impregnated paper make 40°C difference case temperature (see Table 7-4). Likewise, imposition airflow realistically requirement (see Table 7-1).
MEASURING
Intel Pentium Processor Developer's Manual describes proper thermal measuring techniques detail Chapter case temperature (TC) should measured attaching thermocouple center WinChip package. heat produced processor very localized measuring case temperature anywhere else will underestimate case temperature. presence thermocouple inherently invasive; effort must taken minimize effect measurement. thermocouple should attached processor through small hole drilled heatsink. Thermal grease should used ensure that thermocouple makes good contact with package, thermocouple should come direct contact with heatsink.
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Physical Test Conditions
Case temperature measurements should made worst case operating environments. Ideally, systems should maximally configured, tested worst-case ambient temperature.
Test Patterns
During normal operation processor attempts minimize power consumption. Consequently, normal power consumption much lower than maximum power consumption. Thermal testing should done while running software which causes processor operate thermal limits. Your sales representative supply with executable program which will maximize power consumption.
ESTIMATING
WinChip processor' case temperature estimated based general characteristics thermal environment. This estimate intended replacement actual measurement. Case temperature estimated from Tables below, where, Ambient Temperature Case Temperature case-to-ambient thermal resistance junction-to-ambient thermal resistance junction-to-case thermal resistance power consumption (Watts) and,
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Table 7-1. CPGA
(°C/WATT) LAMINAR AIRFLOW (LINEAR FT/MIN) Heat Sink Inches (height) 0.25 0.35 0.45 0.55 0.65 0.80 1.00 1.20 1.40 Heat Sink (°C/Watt) 14.3 13.0 11.6
Environment: these estimates assume thermal grease between processor heatsink. Heatsinks 1.95" square.
Table 7-2. WinChip (0.25µM) Power Consumption
FREQUENCY (MHZ) (VOLTS) 3.52 3.52 3.52 3.52 3.52 POWER (WATTS) 12.0 13.0 10.5 15.0 11.8
Example: system with: WinChip 3.3V 35°C, (ambient around heatsink) 0.65"Heat Sink laminar flow
case temperature calculated
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JC)) (11.8 (3.0-0.8)) 61.0
RECOMMENDED THERMAL SOLUTIONS
Table below offers several off-the-shelf thermal solutions which known provide adequate cooling WinChip Table 7-3. Heatsink Kits
MANUFACTURER Aavid
PART NUMBER 26437 CPB-15502-02 TP5-5015 TP5-5020
Acadia Technology Cooler Master Cooler Master
Aavid 26437 attached Graphite sheet. This eliminates need thermal grease epoxy.
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CONTACTS
Table 7-4. Heatsink Contacts
MANUFACTURER Aavid CONTACT Chris Chapman PHONE (603)528-3400 ADDRESS Kool Path Laconia, 03247 1010 Morse Ave. Suite Sunnyvale, 94089 Fourier Ave. Fremont, 94539
Acadia Technology
Chung
(408)747-1349
Cooler Master
Jerry Chen
(510)770-0149
Table 7-5. Interface Material Contacts
MANUFACTURER Omega Technologies CONTACT PHONE (203)359-1660 ADDRESS Omega Drive Stamford, 06907
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APPENDIX MACHINE SPECIFIC REGISTERS
GENERAL
Tables summarize WinChip processor machine-specific registers (MSRs). Further description each follows table. MSRs read using RDMSR instruction written using WRMSR instruction. Note that there differences specifics memory range management between WinChip predecessor, WinChip There four basic groups MSRs (not necessarily with contiguous addresses). Other than defined below, reference undefined causes General Protection exception. Those that very similar function (but possibly different some detail) Pentium processor MSRs. Generally, same address used. These registers have some utility low-level programs (like BIOS). Note that some first sixteen Pentium MSRs (addresses have function WinChip processor. These MSRs cause when used WinChip processor; instead, reads these MSRs return zero, writes ignored. Memory Configuration Registers which addresses that used Pentium processor. These MSRs define memory ranges with associated attributes. These MSRs similar Pentium processor MTRRs Cyrix 6x86MX processor' registers. Note that memory trait definition WinChip compatible with predecessor, WinChip MSRs used cache testing. These addresses that used Pentium. These test functions very low-level complicated use. They documented this datasheet information will provided customers given appropriate justification.
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Machine Specific Registers
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There some undocumented internal-use MSRs used low-level hardware testing purposes. Attempts read write these undocumented MSRs cause unpredictable disastrous results; don' MSRs that documented this datasheet! MSRs reinitialized INIT interrupt; setting MSRs preserved across INIT. Table A-1. Category MSRs (Functionally Similar Pentium)
TR12 EC_CTRL FCR2 FCR3 FCR4 Time Stamp Counter Event Counter Control Event Counter Event Counter Feature Control Feature Control Feature Control Feature Control Test Register Test Register NAME 00h-01h 03h-0Dh 107h 108h 109h 10Ah Count[63:32] Count[39:32] Count[39:32] FCR2_Hi FCR3_Hi Control bits Control bits Count[31:0] Control bits Count[31:0] Count[31:0] value FCR2 value FCR3 value FCR4 value TYPE NOTES
Notes
Pentium processors have MSRs these addresses. WinChip processor, reads these addresses return zero writes ignored. Functionally similar same Pentium MSR. However, some minor details different. subset same Pentium MSR-only those bits meaningful WinChip processor have effect; rest read ignored when written. Conceptually similar Pentium ("TR12") that controls detailed functions like disabling caches. WinChip processor controls different, thus placed different address than Pentium TR12 register.
Machine Specific Registers
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FCR2 FCR3 provide system software with ability specify Vendor string returned CPUID instruction
Table A-2. Category MSRs (Memory Configuration Registers)
Base Address [31:12] same above same above same above same above same above same above same above Address Mask [31:12] Ctrl Value [11:0] same above same above same above same above same above same above same above control value TYPE NOTES
110h
MCR_CTRL
111h 112h 113h 114h 115h 116h 117h 120h
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CATEGORY MSRS 02h: (Pentium Processor Parity Reversal Register)
31:2 Reserved (Ignored write; returns read)
Both WinChip processor Intel Pentium processor have that performs same function WinChip processor Pentium processor. Other bits return when read ignored when written. Assert IERR# cause Shutdown internal parity error Assert IERR# cause Shutdown internal parity error
0Eh: TR12 (Pentium Processor Feature Control)
31:10 Reserved (Ignored write; returns read)
Both WinChip processor Pentium processor have bits that perform same functions WinChip processor Pentium processor. Other bits return when read ignored when written. Ignored. Same Pentium processor: Cache line fills both caches) suppressed; cache misses performed single transfer cycles. output affected. Note that caches flushed. AHD: Ignored. Same Pentium processor: disable Autohalt Powerdown function
Machine Specific Registers
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ITR:
Ignored. Same Pentium processor: enable Restart function
10h: (Time Stamp Counter)
Both WinChip processor Pentium processor have 64-bit that materializes Time Stamp Counter (TSC). Both systems increment once processor clock. WinChip processor, (and value returned RDTSC instruction) alias internal event-counter MSRs (CTR0/CTR1). normal system operation, register counts internal processor clocks. However, user code changes item that CTR0 CTR1 counting (see counter descriptions), then register also changes what counting. There practical reason machine-specific event counting should changed software. Pentium processor, separate counter from CTR0/CTR1.
11h: CESR (Control Event Select Register)
31:24 Reserved 23:16 CTR1 Control 15:8 Reserved CTR0 Control
Both WinChip processor Pentium have that contains bits defining behavior hardware event counters: CTR0 CTR1. CTR0 CTR1 control fields define which several possible events counted each counter. Each counter same possible events. events that counted, their identification numbers, different from Pentium processor events (which different from Pentium processor events). Pentium processor only bits identify event counter, additional controls (such event versus clock counting) bits each control field.
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CESR should written before associated CTR0 CTR1 written initialize counters. counts necessarily perfectly exact; counters intended over large number events differ counts from what might expected. Most counter events internal implementation-dependent debug functions having meaning software. counters that have end-user utility are:
EVENT DESCRIPTION Data read Data write Data miss Data read cache miss Data write cache miss Data cache writebacks Data cache snoop hits Push/push pop/pop pairing Misaligned data memory (not I/O) Code read Code miss Instruction fetch cache miss hits candidate Instructions executed Instructions pipe (V-pipe) utilization read write cycle Data read data write instructions U-Pipe (EC0) instructions V-Pipe (EC1) Returns predicted incorrectly (EC0) Returns predicted correctly (EC1) Internal clocks (default event CTR0)
12h-13h: CTR0 CTR1 (Event Counters
Both WinChip processor Pentium processor have 40-bit hardware event counters (bits 31:8 ignored). Machine Specific Registers Appendix
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107h: (Feature Control Register)
controls major optional feature capabilities WinChip processor. analogous Pentium processor TR12 (actually 0Eh) that controls things like enable, cache enable, forth. Cyrix 6x86MX processor' CCRs (Configuration Control Registers) perform similar function, does AMD-K6 processor' HDCR MSR. Table contains values FCR. defaults settings shown bits necessarily exact. actual settings changed part manufacturing process thus particular WinChip processor version have slightly different default settings than shown here. reserved values must preserved using read-modify-write sequence update FCR.
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Table A-3. Assignments
22:25 DCPUID EMOVTR E2MMX EAMD3D DPDC EBRPRED ERETSTK ECX8 EIERRINT DMCE DSTPCLK ELINEAR DSMC DTLOCK EMMX NAME DESCRIPTION Reserved Enables CPUID reporting Enables INT18 (Machine Check) internal errors Disable dynamic power management Disables Machine Check Exception Disables supporting STPCLK Enables Linear Burst Mode Disables strict cache coherency (self-modifying-code) Disables locking updates accessed dirty bits page directory/table entries Enables MMX-compatible instructions Reserved Disables Page Directory cache Enables Branch Prediction Disables I-Cache. Disables D-Cache. Disables pipelining response) Enables CALL-RET Stack operation Reserved Reserved Enables pairing MMX-compatible instructions Enables AMD-3D compatible instructions Reserved Stepping Reserved Reserved Reserved Disables CPUID instruction Enables move-to-test register instructions Reserved DEFAULT
Machine Specific Registers
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ECX8:
CPUID instruction does report presence CMPXCHG8B instruction (CX8 instruction actually exists operates correctly, however. CPUID instruction reports that CMPXCHG8B instruction supported (CX8
EIERRINT: Normal internal error behavior (IERR# possible Shutdown). Causes INT18 instead Shutdown internal error. DPM: DMCE: Normal dynamic power management behavior. Disables dynamic power management. Machine Check exception enabled. Disable Machine Check exception; check internal error condition does cause exception.
DSTPCLK: STPCLK interrupt properly supported. Ignores SPCLK interrupt. ELINEAR: Interleaved burst ordering enabled. Linear burst ordering enabled. DSMC: Strict cache coherency enabled support Pentium processor style self-modifying code. Disables strict cache coherency. I-cache/Dcache coherent only branch taken after store instruction which modifies instructions executed subsequently. Updates accessed dirty bits PDE/PTE entries performed using locked read-modify-write semantics which flushes data from D-Cache (like Pentium processor). Updates accessed dirty bits PDE/PTE entries performed without locking flushing data from D-Cache. Disables MMX-compatible instructions: they decode invalid instructions. Enables MMX-compatible instructions. Enables internal Page Directory Cache. Disables internal Page Directory Cache.
DTLOCK:
EMMX:
DPDC:
EBRPRED: Disables branch prediction function. Enables branch prediction function. Appendix Machine Specific Registers
September 1998 WINCHIP PROCESSOR DATA SHEET
DIC:
Enables I-Cache. Disables I-Cache: cache misses performed single transfer cycles, deasserted. This overrides setting CR0.CD CR0.NW. Enables D-Cache. Disables D-Cache: same semantics except D-Cache. Enables pipelining operation. Disables pipelining operation: signal ignored.
DDC:
DNA:
ERETSTK: Disables CALL-RETurn stack function. Enables CALL-RETurn stack function: branch target prediction performed. E2MMX: Disables pairing instructions. Enables pairing instructions.
EAMD3D: Disables 3D-compatible instructions. Enables 3D-compatible instructions. DCPUID: CPUID instruction supported. CPUID instruction disabled causes invalid instruction exception.
EMOVTR: Intel486 move-to/from-test register instructions supported their behavior same Pentium processor (invalid instruction exception). test register instructions cause invalid instruction exception rather treated NOPs.
A-10
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108h: FCR2 (Feature Control Register
This contains more feature control bits many which undefined. important that reserved bits preserved using read-modify-write sequence update MSR.
63:32 Last characters Alternate Vendor string
31:15 Reserved
13:12
11:8 Family
Model
AVS:
CPUID instruction vendor entaurHauls" CPUID instruction returns alternate Vendor first characters alternate Vendor stored FCR3 last characters FCR2[63:32]. These characters undefined after RESET loaded system software using WRMSR.
Family This field will returned family field subsequent uses CPUID instruction Model This field will returned model field subsequent uses CPUID instruction
109h: FCR3 (Feature Control Register
This contains first characters alternate Vendor alternate Vendor returned CPUID instruction when FCR2[AVS] FCR3 write-only MSR.
63:32 First characters Alternate Vendor string
31:0 Middle characters Alternate Vendor string
Appendix
Machine Specific Registers
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10Ah: FCR4 (Feature Control Register
This read-only because only status bits currently defined.
63:32 Reserved
31:2 Reserved
Ratio processor frequency selected pins BF2, BF1, BF0. Note that WinChip does support fractional frequency multiples:
MEMORY CONFIGURATION REGISTERS General
WinChip processor provides extensions over define variable size memory ranges with associated special attributes. These Memory Configuration Registers (MCRs) similar MTRRs Pentium processor Address Region Registers (ARRs) Cyrix 6x86MX processor. these approaches perform similar functions differ specifics. fact, there differences details between WinChip predecessor, WinChip basic function performed define memory regions special attributes these regions such write-combining weakly-ordered reads. These special attributes deviations from formal architectural behavior but, practice, work fine specific memory regions advantage these special attributes improved performance affected memory regions. A-12 Machine Specific Registers Appendix
September 1998 WINCHIP PROCESSOR DATA SHEET
Memory Configuration Registers
WinChip processor eight MCRs, each appearing 64-bit MSR. default value reset zero fields. This value causes memory have normal attributes byte-combining strongly ordered writes. Note that MCRs write-only. format
31:12 Base Address Region 11:0 31:12 Mask Defined Region 11:5 Attributes
Base
This starting physical address memory region. Each definable memory region starts 4-KB page boundary; thus order bits address ignored.
Mask
This mask defining size memory region. memory region exists Mask address memory address Base address mask address positions (31:12)
Example
example, consider memory range from 0x000A0000 0x000BFFFF. This most efficiently done masking order bits that constitute range. Viewing addresses binary:
0x000A0000 0x000BFFFF 0000 0000 0000 1010 0000 0000 0000 0000 0000 0000 0000 1011 1111 1111 1111 1111
Notice that upper bits identical, whereas lower bits define address within range. single describe this range
Base 0000 0000 0000 1010 0000 0x000A0 Mask 1111 1111 1111 1110 0000 0xFFFE0
Note that lower twelve bits mask base ignored match calculation.
Appendix
Machine Specific Registers
A-13
September 1998 WINCHIP PROCESSOR DATA SHEET
Example
Consider more complex scenario where range from 0x00080000 0x00017FFF required. Shown binary
0x00080000 0x0017FFFF 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0001 0111 1111 1111 1111 1111
this case, upper bits identical throughout range. next bits vary, combinations part desired range. range broken down into ranges that have common base bits where combinations lower order bits within original region. This implies:
0x00080000 0x000FFFFF 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111
0x00100000 0x0017FFFF 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0111 1111 1111 1111 1111
These into MCRs:
MCR0 Base 0000 0000 0000 1000 0000 0x00080 MCR0 Mask 1111 1111 1111 1000 0000 0xFFF80
MCR1 Base 0000 0000 0001 0000 0000 0x00100 MCR1 Mask 1111 1111 1111 1000 0000 0xFFF80
Attributes
There five bits attribute control defined each memory region described Table A.6-1. Note that this definition different from predecessor WinChip order avoid unintended programming system software WinChip defines Trait Mode Control field MCR_CTRL, which must appropriate value order MCRs enabled.
A-14
Machine Specific Registers
Appendix
September 1998 WINCHIP PROCESSOR DATA SHEET
Table
Write Combining: effect Writes combined with previous writes same DWORD before executing Non-Cacheable: effect Accesses within this range will disrupt cache. This useful describing video buffer. hint processor that memory controller will consider this non-cacheable (KEN# asserted) therefore processor potentially avoid castout modified line. Reserved. Weak Write Ordering (WWO): effect writes this region reordered with respect each other, this cause issues with DMA-ing devices Weak Read Ordering (WRO): effect reads which require access reordered front writes which also destined DESCRIPTION DEFAULT NOTES
Control Register
MCR_CTRL controls various pervasive behaviors write-combining write-ordering. write combining definitions string non-stack non-string defined following table. Table
DESCRIPTION Write combining definition non-stack non-string. Forward Combining Forward Overlapped Combining Forward Reverse Combining Forward, Reverse, Overlapped Combining Write combining definition string. Forward Combining Forward Overlapped Combining Forward Reverse Combining Forward, Reverse, Overlapped Combining Weak Write-Ordering Enable Reserved Trait Mode Control, must match MCR_CTRL[19:17] order enable DEFAULT NOTES
ReadWrite
ReadWrite
ReadWrite
Read-
Appendix
Machine Specific Registers
A-15
September 1998 WINCHIP PROCESSOR DATA SHEET
DESCRIPTION Memory Configuration Registers: 001: other: Enables WinChip MCRs Disables MCRs
DEFAULT NOTES Write
Before programming MCRs system software should identify processor version ensure that MCRs programmed appropriately. MCR_CTRL[19:17] contains unique value that identifies version traits supported processor. System software should copy MCR_CTRL[19:17] MCR_CTRL[8:6] only recognizes version. MCR0[4:0] attributes zero MCR0[4:0] attributes non-zero (see (see (see (see (see (see (see ReadOnly (RO) ReadOnly ReadWrite
Trait Mode Key, must write this value MCR_CTRL[8:6] order enable Memory Configuration Registers. System software should copy 19:17 MCR_CTRL[19:17] MCR_CTRL[8:6] only recognizes version. 24:20 Reserved
11111
Write-Combining
WinChip processor' write-combining feature allows multiple writes combined into single write. This permissible writes destined same 8-byte memory address. Write-combining greatly reduce memory bandwidth requirements writes that miss cache. However, associated writes destined memory mapped locations, problems arise. example, 8-bit device controlled with data register address control register address control register must written before data written, possible order writes changed writecombining inappropriately configured.
A-16
Machine Specific Registers
Appendix
September 1998 WINCHIP PROCESSOR DATA SHEET
example, device writes address then address combined, 16-bit word will where will split 8-bit device into writes. Unfortunately, most bridges split 16-bit operands into transfers with byte first. Consequently, order writes reversed. eliminate this problem, WinChip processor very configurable. Aside from disabling byte-combining, also possible limit type instructions that allowed combine. Further, possible prevent processor from combining reverse address order. Lastly, possible prevent processor from combine-matching (overlapping) byte addresses. practice reasonable system BIOS enable writecombining types system memory.
Non-Cacheable
WinChip processor improves over WinChip processor with addition Non-Cachable memory trait. This trait used processor indicate that current physical address will processor's cache. This information prevents processor from allocating space access. This prevents unnecessary invalidation trait should only regions memory which will never treated cacheable.
Weak Write-Ordering
Pentium processor ensures that writes occur same order they occur code execution. This termed strong write-ordering. This restriction performance impact that blocks processor execution when store hits line cache another store waiting retired bus. Normally systems require strong write-ordering unless they have bus-mastering devices that memory mapped control purposes. (Most devices slaves, memory-mapped I/O. floppy controller, example, device, does memory-mapped I/O.)
Appendix
Machine Specific Registers
A-17
September 1998 WINCHIP PROCESSOR DATA SHEET
However, since there devices that could perform correctly with weak write ordering, this function should only used systems where type peripherals tightly controlled known require strongly ordered writes. Weak write ordering should never turned generic BIOS, example.
Weak Read-Ordering
Pentium processor also ensures that reads writes occur same order they executed code. This prevents processor from initiating read before preceding writes have completed bus. This causes unnecessary delay processor execution. Normally possible re-order reads front writes, provided associated addresses overlap, addresses destined devices which uses memorymapped I/O. WinChip supports this behavior (under moniker "weak read-ordering") MRDs. recommended that BIOS enable weak read-ordering normal system memory.
Combining Ranges
possible describe fairly complex ranges with descriptors. Generally, this does involve overlapping MCRs. However, overlapping ranges permitted their behavior useful some cases. behavior access given memory location defined logical attribute bits MCRs matches. memory location does match MCRs, aggregate attribute other hand, matches MCRs, with attribute 0x10 other with attribute 0x01, aggregate attribute 0x11. This enables weak read ordering accesses allows write-combining defined MCR_CTRL[3:0].
A-18
Machine Specific Registers
Appendix
September 1998 WINCHIP PROCESSOR DATA SHEET
APPENDIX COMPATIBILITY
INTRODUCTION
general, WinChip processor exactly compatible with both software-visible architecture Intel Pentium processor. WinChip processor plug into existing Intel Pentium-based system boards operate without requiring change system hardware. Also, WinChip processor existing industry-standard object-code operating systems application programs. However, processors developed processors) have some minor incompatibilities low-level implementation-dependent functions. example, possible write esoteric software Intel processor (cache tests, example) that produces different results when supposedly compatible Intel Pentium processor. Similarly, there low-level incompatibilities between Intel Pentium Intel Pentium processors. Similarly, there low-level incompatibilities among lone" processors such AMD-K6 Cyrix 6x86MX processors. WinChip processor similar low-level differences with various Intel clone processors. Fortunately, these technical incompatibilities among implementations areas that have meaningful most programs, that well-understood software developers (and thus avoided). Therefore, practice, these types differences pose real barriers program compatibility across various implementations. This appendix summarizes areas where WinChip processor differs behavior from Intel Pentium processor. These differences generally cares" that they transparent system hardware programs. separate WinChip Errata document describes WinChip processor errata: differences between actual WinChip processor behavior expected results.
Appendix
Compatibility
September 1998 WINCHIP PROCESSOR DATA SHEET
COMPATIBILITY
Cycle Activity
When compared cycle cycle, WinChip Intel Pentium processors have exactly same cycles. This anticipated, unavoidable, desirable (the WinChip processor provides increased performance). This difference results from WinChip processor' different internal architecture larger cache. This issue because Intel Pentium processor itself varies different frequencies other competitive processors also have differing cycle activity.
Alignment
Although Intel Pentium processor
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