Eight full-duplex asynchronous channels supporting data rates 115.2 kb
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CL-CD1865
Eight full-duplex asynchronous channels supporting data rates 115.2 kbps* Register-based interrupt acknowledges eliminate need separate interrupt acknowledge signals Automatic prioritizing scheme allows device respond interrupt acknowledge with highest internal interrupt pending (hostprogrammable) Sophisticated interrupt schemes
Vectored interrupts Fair Share interrupts Good Datainterrupts improved throughput Simultaneous interrupt requests three classes interrupts: modem state changes
Intelligent Eight-Channel Communications Controller
OVERVIEW
CL-CD1865 cost-effective controller capable controlling eight full-duplex channels transferring data rates 115.2 kbps. advantage CL-CD1865 lies ability efficiently move data from serial channels host. This results order-of-magnitude improvement system-level throughput reduction overhead host CPU. increase overall data throughput system, device relies combination features. Most important buffers transmit receive data. Each serial channel three 8-byte FIFOs each transmit, receive, receive exception status. receive FIFOs have programmable thresholds minimize interrupt latency requirements.
(cont.)
Independent baud-rate generators each channel/direction Software compatibility with CL-CD180 CL-CD1864 devices Generation detection special characters Automatic flow control
In-band (Xon, Xoff generation, detection) Out-of-band (DTR/DSR RTS/CTS)
On-chip FIFO bytes each Status Line break detection generation
support this data rate, specified system clock frequency required.
Functional Block Diagram
RESET* CLK* R/W* A[0:6] INTEL/MOT* RREQ* TREQ* MREQ* DTACKDLY DTACK* DB[0:7] ACKIN* ACKOUT* OSC1 OSC2 DBLCLK CKOUT
SERIAL INTERFACE SERIAL INTERFACE SERIAL INTERFACE SERIAL INTERFACE HOST INTERFACE LOGIC RISC PROCESSOR FIRMWARE SERIAL INTERFACE SERIAL INTERFACE SERIAL INTERFACE SERIAL INTERFACE
MODEM MODEM MODEM MODEM MODEM MODEM MODEM MODEM
Version
World Wide Web: http://www.basiscomm.com
August 1996
OVERVIEW
CL-CD1865
Intelligent Eight-Channel Communications Controller
OVERVIEW (cont.)
CL-CD1865 based high-performance proprietary RISC processor architecture developed Basis Communications specifically data communication applications. This processor executes instructions clock cycle, uses registerwindow architecture ensure zero-overhead context switch each type internal interrupt. CL-CD1865 fabricated advanced CMOS process. device's high throughput, low-power consumption, high-level integration permit system designs with minimum parts count, maximum performance, maximum reliability.
Theory Operation
CL-CD1865 custom RISC processor assisted specialized peripheral logic. Serial data transmission reception handled `bit engines'. Each channel engine transmit another receive. While each engine handles bit-level timing, bit-to-character assembly done firmware. Bits passed processor internal interrupts, over special dedicated this purpose. reduce internal interrupts zero, special interrupt context hardware points correct register window every possible context. unique Global Index register eliminates address calculations always pointing current channel. processor assembles bits into characters, checks parity other formatting parameters, stores data FIFOs required. FIFOs maintained RAM-based structures. Both local processor host access them Pointer registers, effect Indexed Addressing mode. CL-CD1865 communicates with host service requests service acknowledgments. Service requests detected interrupt lines on-device registers. Regardless method used, CL-CD1865 features minimize both number requests serviced time required service them. FIFOs help reduce number service requests every eight characters. reduce time required request, CL-CD1865 supplies separate vectors four different types service requests. This reduces time required processor effect proper operation. instance, there unique vector `good data', that host wastes time checking status bits error conditions. there error condition, CL-CD1865 supplies unique vector pointing error-handling routine. Other vectors report transmit status modem signal change. Interrupts acknowledged either Interrupt Acknowledge pin, reading on-device register. This allows host software maximum flexibility speed handling service requests.
ADDRESS DATA
ADDRESS DECODE CONTROL LOGIC
DTACK* ACKIN*
DTR* DSR* RTS* CTS*
INTERRUPT CONTROLLER
Channel
RREQ* TREQ* MREQ*
RREQ* TREQ* MREQ*
RREQ* TREQ* MREQ*
CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL CHANNEL
CL-CD1865
INTERRUPT CONTROLLER RREQ* TREQ* MREQ*
ACKIN* ACKOUT*
ACKIN* ACKOUT*
ACKIN* ACKOUT*
CL-CD1865
CL-CD1865
CL-CD1865
Typical CL-CD1865 Host Interface
CL-CD1865 Daisy-Chain Scheme August 1996
OVERVIEW
DATA BOOK v2.0
CL-CD1865
Intelligent Eight-Channel Communications Controller
Theory Operation (cont.)
Because CL-CD1865 RISC processor processing every character sent received, features such automatic flow control special character recognition easily implemented. This further reduces processing burden host system. Both In-Band (Xon, Xoff) Out-of-Band (RTS/CTS, DTR) Flow-Control modes supported. in-band flow control, CL-CD1865 automatically starts stops transmitter when remote unit sends flow-control characters. CL-CD1865 also makes easy local host flow-control remote, `send special character' commands. out-of-band flow control, transmitter optionally asserts monitor permission send; assert/negate when Receive FIFO reaches user- definable threshold. Together, in-band out-of-band features only allow data flow controlled real time with minimum host intervention, also prevents loss data. shown previous page, CL-CD1865 interface virtually CPU, with minimum glue logic. Refer CL-CD1865 Data Sheet detailed information interface various CL-CD1865s easily implemented, with external glue, device daisy-chain scheme. `fair share' feature ensures equal access service requests, both within CL-CD1865 across multiple devices. FIFO bytes FIFO dedicated each channel partitioned bytes transmitter, bytes receiver, bytes status. receive FIFO user-programmable threshold optimize system response latency. receive FIFO threshold programming range from characters. Vectored Interrupt Structure Three interrupt signals ([R, M]REQ*) used. These signals also read on-device register. Each REQ* signal represents three interrupt groups: receive, transmit, modem signal state changes. Upon servicing host, interrupt vector generated CL-CD1865 define CL-CD1865 generated interrupt. This allows host software enter directly into proper interrupt service routine, reducing amount interaction between host controller, determining nature interrupt. Good Data Interrupt data received good, host advised number good data bytes FIFO, allowing host read data without further status queries until good data been transferred. Fair-Share Interrupt Scheme ensure equal service channels, fair share scheme used each interrupt group. channel interrupt same condition until others have chance serviced same interrupt condition.
NOTE: support 115.2 kbps, system clock required. System design simplified CL-CD1865 providing choice crystal external clock operation, frequency.
Differences Between CL-CD1865 CL-CD1864 Pins
Number
CL-CD1865 Name
CL-CD1864 Name
Comments
Pins no-connects CL-CD1864 device. CL-CD1864 true no-connect cause problems connected VCC. make single board design compatible with either CL-CD1864 CL-CD1865, configuration jumper that allows no-connect connection.
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OVERVIEW
TABLE CONTENTS
CL-CD1865
Intelligent Eight-Channel Communications Controller
Before beginning design with this device, please contact Basis Communications latest errata information. back cover this document sales office locations phone numbers.
Table Contents
CONVENTIONS DEVICE SELECTION CONSIDERATIONS INFORMATION
Diagram.11 Assignments.12 2.2.1 General.12 2.2.2 Microprocessor Interface 2.2.3 Service Request Interface 2.2.4 Communications Interface.13 2.2.5 Miscellaneous.13 Descriptions 2.3.1 General.14 2.3.2 Microprocessor Interface 2.3.3 Service Request Interface 2.3.4 Communications Interface.17 2.3.5 Miscellaneous.17
FUNCTIONAL DESCRIPTION
Introduction.18 Internal Operation.20 Service Request Interrupt Operation.25 3.3.1 Theory Operation 3.3.2 Internal Implementation Service Request Logic.27 3.3.3 Priorities Fair Share.30 Types Service Requests.31 3.4.1 Receive Service Requests 3.4.2 Transmit Service Requests.34 3.4.3 Modem Signal Change Service Requests Implementing Service Requests.34 3.5.1 Method Full Interrupt Type Three-Level Interrupt with Three-Level Acknowledge 3.5.2 Method Full Interrupt Type Three-Level Interrupt with Single-Level Acknowledge 3.5.3 Method Interrupt Interface, Single-Level Interrupt with Single-Level Acknowledge 3.5.4 Method Polled Interface 3.5.5 Comparison Interrupt Polled Code Sequences 3.5.6 Cascading Service Requests with Multiple CL-CD1865s 3.5.7 Multiple CL-CD1865s without Cascading.43 3.5.8 Acknowledging Service Requests
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CL-CD1865
Intelligent Eight-Channel Communications Controller
SYSTEM INTERFACE SYSTEM CLOCK.
System Interface Considerations.45 System Clock Rate Options 4.2.1 System Clock.45 4.2.2 External Clock 4.2.3 Clock Option 4.2.4 Rate Options 4.2.5 Maximum Throughput Limits CL-CD1865 Basic Interface Addressing.48 4.3.1 Intel® Versus Motorola® Interface Signals Addressing.48 4.3.2 Unclocked Versus Clocked Interface Interface Examples 4.4.1 Interfacing 80X86-Family Processors.51 4.4.2 Interfacing 680X0-Family Processors.51 4.4.3 Interfacing
SERIAL INTERFACES.
Receiver Operation.54 5.1.1 Basic Operation 5.1.2 Receive FIFO Operation.54 5.1.3 FIFO Timer Operations.56 5.1.4 Receive Service Requests 5.1.5 Receive Good DataService Request.57 5.1.6 Receive Exception Service Request 5.1.7 Types Errors 5.1.8 Types Exceptions 5.1.9 Programming Notes.63 Transmitter Operation 5.2.1 Basic Operation 5.2.2 FIFO Operation 5.2.3 Transmit Service Requests.64 5.2.4 Special Transmitter Commands.65 5.2.5 Special Character Transmission Send Special Character Command.65 5.2.6 Embedded Transmit Commands 5.2.7 Sending Breaks 5.2.8 Sending Inter-Character Delays 5.2.9 Summary Special Transmitter Commands Flow Control 5.3.1 Receiver Flow Control 5.3.2 Receiver Hardware (Out-of-Band) Flow Control.68 5.3.3 Receiver Software (In-Band) Flow Control 5.3.4 Transmitter Flow Control.70 5.3.5 Transmitter Hardware (Out-of-Band) Flow Control 5.3.6 Transmitter Software (In-Band) Flow Control Modem Signals General-Purpose 5.4.1 Generating Service Requests with Modem Pins 5.4.2 Using Modem Pins General-Purpose Testing CL-CD1865 Loopback Tests
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CL-CD1865
Intelligent Eight-Channel Communications Controller
PROGRAMMING
6.10 6.11 Types Registers Access Duty Cycle.77 Accessing FIFOs Versus Other Registers Initialization.78 Global Register Initialization Service Request Initialization Prescaler Channel Initialization Changes Transmitting Data.81 Receiving Data Programming Examples 6.11.1 Programming Service Match Registers.82 6.11.2 CL-CD1865 Initialization.82 6.11.3 Basic Operations 6.11.4 Interrupt Response Operations 6.11.5 Polled Mode Operation.90
DETAILED REGISTER DESCRIPTIONS
Register Quick Reference:.91 Global Registers 7.2.1 Miscellaneous Registers 7.2.2 Configuration Registers.96 7.2.3 Service Request/Interrupt Control Registers.103 Indexed Indirect Registers .109 7.3.1 Receive Data Count Register .110 7.3.2 Receive Data Register .111 7.3.3 Receive Character Status Register .112 7.3.4 Transmit Data Register .113 7.3.5 End-of-Service Request Register.114 Channel Registers .115 7.4.1 Service Request Enable Register .115 7.4.2 Channel Command Register .116 7.4.3 Channel Option Register .120 7.4.4 Channel Option Register .121 7.4.5 Channel Option Register .122 7.4.6 Channel Control Status Register.123 7.4.7 Receiver Register.124 7.4.8 Receive Time-Out Period Register .125 7.4.9 Receive Rate Period Registers (High/Low) .126 7.4.10 Transmit Rate Period Registers (High/Low) .127 7.4.11 Special Character Register .128 7.4.12 Special Character Register .129 7.4.13 Special Character Register .130 7.4.14 Special Character Register .131 7.4.15 Modem Change Register .132 7.4.16 Modem Change Option Register 1.133 7.4.17 Modem Change Option Register 2.134 7.4.18 Modem Signal Value Register .135
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CL-CD1865
Intelligent Eight-Channel Communications Controller
7.4.19 Modem Signal Value Request-to-Send Register .136 7.4.20 Modem Signal Value Data-Terminal-Ready Register .137
ELECTRICAL SPECIFICATION
Absolute Maximum Ratings.138 Recommended Operating Conditions .138 Electrical Characteristics .138 Index Timing Information .139 Electrical Characteristics .140 8.5.1 Clocked Interface .140 8.5.2 Un-Clocked Interface.150
PACKAGE SPECIFICATIONS ORDERING INFORMATION INDEX.
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CL-CD1865
Intelligent Eight-Channel Communications Controller
CONVENTIONS
Abbreviations
Symbol
Kbit kbps kbits/second Kbyte kbytes/second Mbyte
Units measure
degree Celsius microfarad microsecond (1,000 nanoseconds) hertz (cycle second) kilobit (1,024 bits) kilobit (1,000 bits) second kilobyte (1,024 bytes) kilobyte (1,000 bytes) second kilohertz kilohm megabyte (1,048,576 bytes) megahertz (1,000 kilohertz) milliampere millisecond (1,000 microseconds) nanosecond picovolt volt watt
`tbd' indicates values that determined', `n/a' designates `not available', `n/c' indicates that connect'.
CONVENTIONS
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CL-CD1865
Intelligent Eight-Channel Communications Controller
Acronyms
Acronym
CMOS DRAM FIFO HDLC PQFP SDLC
Definition
alternating current complementary metal-oxide semiconductor direct current direct-memory access dynamic random-access memory first in/first high-level data link control industry standard architecture least-significant most-significant point-to-point protocol plastic quad-flat pack random-access memory read/write synchronous data link control transistor-transistor logic
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CONVENTIONS
CL-CD1865
Intelligent Eight-Channel Communications Controller
DEVICE SELECTION CONSIDERATIONS
CL-CD1865 device enhanced version same product family CL-CD180 CL-CD1864. CL-CD1865 software compatible with both CL-CD180 CL-CD1864. this CL-CD1865 design, please skip this page. CL-CD1865 recommended designs. Please note that achieve high data rates, 66-MHz system clock required. support data rates 115.2 kbps, specified system clock frequency required. Please refer differences pins between CL-CD1864 CL-CD1865. recommended that 66-MHz, option (oscillator crystal) used wherever possible. Table 1-1. CL-CD18XX Product Family
CL-CD180
84-pin PLCC 12.5 kbps DTRSEL Pins modem/IO signals channel
Features
Package System clock Maximum rates
CL-CD1864
100-pin PQFP 12.5 kbps modem/IO signals channel
CL-CD1865
100-pin PQFP 115.2 kbps modem/IO signals channel
NOTE: This input (DTRSEL) CL-CD180 sets mode DTR*/CD* pins. When DTRSEL high, DTR*/CD* pins implement DTR* output; when low, DTR*/CD* pins become inputs.
CL-CD1864 CL-CD1865 have separate pins DTRSEL eliminated. Table 1-2. Differences Between CL-CD1865 CL-CD1864
CL-CD1865 Name
Number
CL-CD1864 Name
Comments
truly no-connects CL-CD1864 device. CL-CD1864 true no-connect, cause problems connected VCC. make single board design compatible with either CL-CD1864 CL-CD1865, configuration jumper must used allow no-connect connection.
NOTE: January 1995, 100-pin PQFP package types were changed from EIAJ JEDEC. CL-CD1865 available JEDEC package. Before beginning design converting from CL-CD1864 CL-CD1865, please contact Basis Communications package details.
WARNING: CL-CD1865 device have potential latch problems used socket. recommend
that this device surface mounted.
DEVICE SELECTION CONSIDERATIONS
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CL-CD1865
Intelligent Eight-Channel Communications Controller
INFORMATION
CL-CD1865 available 100-pin PQFP (plastic quad flat pack device) configuration shown below.
Diagram
DB[7]
DB[6]
DB[5]
DB[4]
DB[3]
DB[2]
DB[1]
DB[0]
CKOUT
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
DS*(RD*) R/W*(WR*) DTACK* RTS[0]* CTS[0]* CD[0]* DTR[0]* DSR[0]* RTS[1]* CTS[1]* CD[1]* DTR[1]* DSR[1]* RTS[2]* CTS[2]* CD[2]* DTR[2]* DSR[2]* RTS[3]* CTS[3]* CD[3]* DTR[3]* DSR[3]* RTS[4]* CTS[4]* CD[4]*
RESET*
TEST ACKIN* DBLCLK OSC2 OSC1 NO_OSC RREQ* TREQ* MREQ* TXD[7] TXD[6] TXD[5] TXD[4] TXD[3] TXD[2] TXD[1] TXD[0] RXD[7] RXD[6] RXD[5] RXD[4] RXD[3] RXD[2] RXD[1] RXD[0] DSR[7]* DTR[7]* CD[7]* CTS[7]*
CL-CD1865
100-Pin PQFP
CTS[5]*
CD[5]*
RTS[5]*
CTS[6]*
CD[6]*
RTS[6]*
DTR[4]*
DTR[5]*
DTR[6]*
DSR[4]*
INTEL/MOT*
NOTE: Denotes active-low (negative-true) signal.
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DTACKDLY
ACKOUT*
DSR[5]*
DSR[6]*
RTS[7]*
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INFORMATION
CL-CD1865
Intelligent Eight-Channel Communications Controller
Assignments
following conventions used table below: denotes active-low signal; input; input/output; output; open drain; indicates decending numbers; indicates ascending numbers. 2.2.1 General
Symbol
DBLCLK NO_OSC OSC1 OSC2 CKOUT RESET*
Number
Number Pins
Type
Default Value after Reset
(Low) (Low) (Low) (Low) (Low) (Low) (High)
NOTE: Both RESET* pins have specification volts. pull-up resistor, driver logic families specified their manufacturers providing least (such advanced CMOS, advanced Schottky, others) when driving (milliamp) load, recommended.
2.2.2 Microprocessor Interface
Symbol
A[0-6] DB[0-7] DS*(RD*) R/W*(WR*) DTACK* DTACKDLY INTEL/MOT*
Number
94-100 85-90,
Number Pins
Type
O-OD
Default Value after Reset
Three-state (floating) (High) (High) (High) (High) (Low)
INFORMATION
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CL-CD1865
Intelligent Eight-Channel Communications Controller
2.2.3 Service Request Interface
Symbol
ACKIN* ACKOUT* RREQ* TREQ* MREQ*
Number
Number Pins
Type
O-OD O-OD O-OD
Default Value after Reset
(High) (High) (High) (High) (High)
2.2.4 Communications Interface
Symbol
RxD[0-7] TxD[0-7] CD[0-7]* DSR[0-7]* DTR[0-7]* CTS[0-7]* RTS[0-7]*
Number
55-62 65-71 8,13,
Number Pins
Type
Default Value after Reset
(High) (High) (High) (High) (High) (High) (High)
2.2.5 Miscellaneous
Symbol
TEST
Number
Number Pins
Type
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CL-CD1865
Intelligent Eight-Channel Communications Controller
Descriptions
2.3.1 General
Symbol
Number
Type
Description
SYSTEM CLOCK: Input clock signal. clock crystal used, ground this input. DOUBLE CLOCK: Input clock signal. clock used, this signal high VCC. crystal used, ground this signal. Using clock recommended this device. DISABLES ON-CHIP OSCILLATOR: oscillator being used, this signal high. crystal being used, ground this input. OSCILLATORS: Connection external crystal. crystal should ATcut, parallel-mode, fundamental-frequency crystal, must twice required frequency, (for example, 66-MHz crystal provides 33-MHz operation). crystal used, OSC1 should tied high, OSC2 should connected. CLOCK OUTPUT: This output actual clock that drives CL-CD1865 internally, regardless clock source. RESET: Resets CL-CD1865. internal registers cleared initialized.
DBLCLK
NO_OSC
OSC1, OSC2
CKOUT RESET*
INFORMATION
DATA BOOK v2.0
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CL-CD1865
Intelligent Eight-Channel Communications Controller
2.3.2 Microprocessor Interface
Symbol
A[0-6] DB[0-7]
Number
94-100 85-90,
Type
Description
ADDRESS: Address inputs, used select various internal registers CL-CD1865. DATA CHIP SELECT: Chip Select must reads writes CL-CD1865, service acknowledgment cycles. Chip Select must never when ACKIN* low. DATA STROBE: When INTEL/MOT* low, this signal used control access CL-CD1865, data hold time bus. When INTEL/MOT* high, this performs same function read cycles service acknowledgment cycles. READ/WRITE: When INTEL/MOT* low, this signal controls whether current cycle read write. When INTEL/MOT* high, this signal strobes data into CL-CD1865 write cycles only. DATA TRANSFER ACKNOWLEDGE: Open-drain output. This signal indicates completion internal cycle within CL-CD1865. used insert wait states host. Note that cycles fixed length, interface correctly designed, DTACK* required insert wait states. DTACK DELAY: Controls time assertion DTACK allow `fine tuning' number wait states inserted. When low, DTACK asserts earlier than when high. INTEL/MOT*: Selects either bus-handshake styles. When low, acts Data Strobe, R/W* acts read/write. When INTEL/MOT* high, pins strobe strobe. INTEL/MOT* does affect timing interface, only logical meaning these pins. INTEL/MOT* tied either high low, should changed during regular operation.
(RD*)
R/W* (WR*)
DTACK*
O-OD
DTACKDLY
INTEL/MOT*
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CL-CD1865
Intelligent Eight-Channel Communications Controller
2.3.3 Service Request Interface
Symbol
ACKIN*
Number
Type
Description
ACKNOWLEDGMENT (SERVICE) INPUT: Must only during service acknowledge cycles. Must never when low. ACKNOWLEDGMENT (SERVICE) OUTPUT: Goes whenever CL-CD1865 recognizes that valid acknowledgment occurring (either hardware- register-based) that CL-CD1865. daisy-chain applications, ACKOUT* should connected ACKIN* next CL-CD1865. RECEIVE REQUEST OUTPUT: Asserts whenever CL-CD1865 receive condition requiring service. Negates whenever service acknowledgment receive type occurs. TRANSMIT REQUEST OUTPUT: Asserts whenever CL-CD1865 transmit condition requiring service. Negates whenever service acknowledgment transmit type occurs. MODEM REQUEST OUTPUT: Asserts whenever CL-CD1865 modem signal change condition requiring service. Negates whenever service acknowledgment modem signal change type occurs.
ACKOUT*
RREQ*
O-OD
TREQ*
O-OD
MREQ*
O-OD
INFORMATION
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CL-CD1865
Intelligent Eight-Channel Communications Controller
2.3.4 Communications Interface
Symbol
RxD[0-7] TxD[0-7]
Number
55-62 65-71
Type
RECEIVED DATA INPUTS
Description
TRANSMITTED DATA OUTPUTS
NOTE: following `modem control' signals named arbitrarily. signal general-purpose input. DSR* DTR* signals used CL-CD1865 receiver handshake flow control, used general-purpose inputs outputs. RTS* CTS* signals used CL-CD1865 transmitter handshake flow control, used general-purpose inputs outputs. cases, CL-CD1865 programmed generate interrupts whenever input pins change state specified direction.
CD[0-7]* CARRIER DETECT INPUTS: These inputs used general-purpose inputs. These pins also used ring detect inputs. DATA READY INPUTS: These inputs used control Receive Shift register flow-control purposes, general-purpose inputs. DATA TERMINAL READY OUTPUTS: Used receiver indicate that Receive FIFO exceeded user-defined threshold; other words, signal flow-control remote sender. This also used generalpurpose output. CLEAR-TO-SEND INPUTS: Used transmitter permission-to-send controls, used general-purpose inputs. REQUEST-TO-SEND OUTPUTS: Used transmitter indicate that there data sent. This used general-purpose outputs.
DSR[0-7]*
DTR[0-7]*
CTS[0-7]*
RTS[0-7]*
2.3.5 Miscellaneous
Symbol
TEST
Number
Type
Description
CONNECT: Make connections these pins. GROUND TEST: This test should connected ground.
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INFORMATION
CL-CD1865
Intelligent Eight-Channel Communications Controller
FUNCTIONAL DESCRIPTION
Introduction
CL-CD1865 coprocessor controls eight full-duplex channels that transfer data rates 115.2 kbps. CL-CD1865 efficiently moves data between serial channels host, resulting great improvement system-level throughput reduction overhead host CPU. This improvement obtained reducing number service requests (interrupts) host must respond reducing complexity time required handle each service request. CL-CD1865 relies combination features reduce number complexity service requests. Most important buffers transmit receive data. Each serial channel three 8-byte FIFOs each transmit, receive, receive-exception status. Receive FIFOs have programmable thresholds minimize interrupt latency requirements. vectored service requests Good Datainterrupt allow host system immediately transfer data upon beginning processing service request, without tedious checking flags error conditions. CL-CD1865 based high-performance, proprietary RISC processor architecture developed Basis Communications specifically data communications applications. CL-CD1865 processor executes instructions one-clock cycle, uses register window architecture ensure zero-overhead context switch each type internal interrupt. instruction this processor optimized bitoriented tasks that combined with instantaneous response sending receiving bit, allow highly efficient processing characters. firmware CL-CD1865 processor contained on-device ROM, requires user programming. CL-CD1865 processor assisted task specialized peripheral logic. Serial data transmission reception handled `bit engines'. Each channel engine transmitting
another receiving. While each engine handles bit-level timing, bit-to-character assembly CL-CD1865 processor internal interrupts over special dedicated this purpose. Special internal-interrupt context hardware reduces overhead internal interrupts zero pointing correct register window every possible context, unique Global Index register eliminates address calculations always pointing current channel. External service requests host system also hardware assisted. There queue each three classes external service requests, request/acknowledgment mechanism entirely hardware minimize response time. CL-CD1865 processor assembles bits into characters, checks parity formatting parameters, stores data FIFOs required. FIFOs maintained RAM-based structures, both local CL-CD1865 processor host access them Pointer registers Indexed Addressing mode. CL-CD1865 communicates with host service requests service acknowledgments. Service requests handled either interrupts polling. Regardless method used, CL-CD1865 features minimize both number requests serviced time required service them. number service requests reduced FIFOs since service request required only every eight characters. reduce time required request, CL-CD1865 supplies separate vectors four different types service requests. This reduces time required host determine what action take. example, there unique vector Good Data that host wastes time checking status bits error conditions. there error condition, CL-CD1865 supplies unique vector pointing error-handling routine. Other vectors report transmit status modem signal change. Service requests host system implemented CL-CD1865 three hardware service request state machines. Each machine ability `queue-up' multiple requests. state machines designed offer August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
CL-CD1865
Intelligent Eight-Channel Communications Controller
fastest response possible. Whenever CL-CD1865 processor determines that condition needs service request, queues request with appropriate state machine. state machine acknowledgment cycles from host, informs CL-CD1865 processor when valid service acknowledgment been completely serviced. This allows CL-CD1865 correctly maintain internal context processing channel being serviced. Because CL-CD1865 processor processes every character sent received, features such Automatic Flow Control Special Character Recognition easily implemented. This reduces processing burden host system. Both InBand (Xon, Xoff) Out-of-Band (RTS/CTS, DTR/DSR) Flow Control modes supported. In-Band Flow Control, CL-CD1865 automatically starts stops transmitter when remote unit sends flow-control characters. CL-CD1865 makes easy local host flow-control remote `Send Special Character' commands. Out-of-Band Flow Control, transmitter optionally asserts monit asser t/negate when Receive FIFO reaches user-definable threshold. used gate receiver off. Together, In-Band Out-of-Band features allow data flow controlled realtime with minimum host intervention, this also prevents loss data. Systems with multiple CL-CD1865s easily implemented, with external glue, daisychain scheme. fair-share feature ensures equal access service requests, both within CL-CD1865 across multiple devices. Alternately, multiple CL-CD1865s operated parallel independent devices. Serial channels CL-CD1865 entirely independent another. channel programmed combination features regardless state other channels. Bit-rate generators programmed loading divisor value, transmitters receivers each operate standard non-standard data rate.
CL-CD1865 detect received linebreak condition, send break characters length, transmit delays. This done transmit commands embedded Transmit Data Stream. CL-CD1865 also programmed detect user-defined special characters generate special service request host. Parity checking performed automatically, overridden host force parity errors test purposes. Character length Stop length also programmable per-channel. Modem pins CL-CD1865 general-purpose, that they hard-wired into UART functions. modem pins needed interface actual modems, they used general-purpose pins. either case they readable writable directly host system. addition, CL-CD1865 programmed monitor levels modem input pins generate service requests host upon detecting specified change. CL-CD1865 fabricated advanced CMOS process. high throughput, low-power consumption, high level integration permits system designs with minimum parts count, maximum performance, greater reliability. There significant difference between CL-CD1865 conventional dumb UARTs; CL-CD1865 more efficient intelligent, even when operating polled environment. Systems built with CL-CD1865 interface between host device higher level than systems built with conventional UARTs. example, with dumb UART, host must test each channel presence data, process that timeconsuming. With CL-CD1865, host queries entire serial subsystem presence data. data present, CL-CD1865 determines which channel whether good erroneous. Thus, using CL-CD1865, host-peripheral interface easier implement, faster, more efficient.
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FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
Internal Operation
internal architecture CL-CD1865 shown Figure 3-1. foundation design custom-designed that Basis Communications developed especially this application. This optimized bit-oriented tasks associated with UART functions, registers each channel, arranged register window architecture. These registers eight bits wide. CL-CD1865 processor 16-bit instruction word that retrieves from on-device ROM. Every instruction one-word long executed one-clock cycle. Whenever internal interrupt occurs (from engine), CL-CD1865 processor automatically switches context that channel's block registers. time lost saving machine state. CL-CD1865 processor executes instructions necessary handle that (typically three instructions) then returns context prior internal interrupt. internal interrupts same priority level; interrupt handler block ensures fair-share access across channels. Each channel's serial interface logic consists receive-bit engine, transmit-bit engine, receivebaud-rate generator, transmit-baud-rate generator, timer. receive-bit engine samples state time indicated receive-baud-rate generator, reports this value CL-CD1865 processor interrupt. transmit-bit engine works similar manner. baud rate tick, outputs next generates interrupt CL-CD1865 processor requesting following bit. baud-rate generators 16-bit dividers that operate from master clock, which system clock divided baud-rate generators independent, channel send receive speed. addition baud-rate generators, there channel timers each channel. 8-bit divider, operating master prescaler timer tick. This timer used time-out partially full FIFOs avoid `stale' data. other used time embedded delays transmit data stream.
eight channels continuously scanned internal logic that generates interrupts CL-CD1865 processor `fair' manner. This fairshare interrupt feature same mechanism used share service requests across multiple devices. Whenever more channels contending interrupt service, channel that serviced first does assert again until other currently pending channels serviced. This prevents fast, 64-kbps channel from demanding service from slow 1200-bps channel, allows faster channel additional service needs support higher speed. This allows more overall throughput than `round-robin' `equalaccess' method would provide. Service requests host handled fast, dedicated logic each three levels provided. Whenever CL-CD1865 processor detects condition requiring external-host service, queues request with service-request machine that level. This machine asserts External Request pin, monitors service acknowledgment same level. When service acknowledgment sensed, machine automatically provides vector host sets internal context CL-CD1865 service. Upon completion service, machine restores normal context. queue service requests deep, busy system there another request immediately pending when first completed. This method avoids delay between requests, improves overall efficiency. Modem signals implemented `conventional' input-output circuits, readable, writable either on-device host CPU. This allows maximum flexibility using these signals either conventional way, other function required. When CL-CD1865 processor using these pins implement flow-control functions, reads them under software control implements function that way. There direct hardware association between modem pins serial hardware.
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE ENGINE RREQ* TREQ* MREQ* ACKOUT* ACKIN* SERVICE REQUEST LOGIC TRANSMIT SERVICE REQUEST QUEUE RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE SERVICE REQUEST QUEUE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
RXDATA TXDATA
RXDATA TXDATA
RXDATA TXDATA
MODEM SERVICE REQUEST QUEUE ADR[0-6] DATA[1-7]
RECEIVE ENGINE TRANSMIT ENGINE INTERRUPT HANDLER DUAL-BAUD RATE GENERATORS RECEIVE ENGINE
RXDATA TXDATA
RXDATA TXDATA
DTACK* INTEL/MOT* RESET* DBLCLK NO_OSC OSC1 OSC2
INTERFACE
TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
CHANNEL TIMER
RXDATA TXDATA
PINS (MODEM CONTROL)
RTS* CTS* DTR* DSR* LINES LINES LINES LINES LINES LINES LINES
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
RXDATA TXDATA
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
RXDATA TXDATA
Figure 3-1. Internal Block Diagram August 1996
DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
CL-CD1865 workload divided into categories:
Bit-to-character conversion (and vice versa) `traditional' UART function Character-level processing such flow control, FIFO management, host interface functions
CL-CD1865 internal processor handles these tasks firmware. foreground/background scheme used: foreground internal bit-engine interrupts background everything else. This internal structure represented Figure page shows foreground communicates with background. Foreground code handles bit-to-character assembly receive, character-to-bit disassembly transmit. either case Holding register, together with Full/Empty bit, acts `gateway' between interruptdriven foreground polling-loop background code. background code executes polling loop shown Figure 3-3. After power-on reset, software runs continuously inner outer loop. Lower-priority tasks handled outer loop, higher-priority tasks handled inner loop. highest-priority tasks events that handled foreground (that interruptdriven) code. inner loop executes eight times often outer loop. checks each channel's Full/Empty bits sense another character needs moved. first checks receive, there character moved, moved execution moves next channel. receive data does need processing, then transmit checked. This mechanism gives slightly higher priority
receive than transmit, favorable because missing receive character fatal error being late transmitting error. (The effect this observed programming CL-CD1865 higher-than-rated serial baud rates providing source receive traffic with virtually 100-percent loading. CL-CD1865 heavily loaded, leaves short gaps between transmit characters because firmware following `receive' path through code. Refer Section 4.2.5 details maximum performance maximum line speed). After eight passes through inner loop (for example, checking eight channels data), pass made through outer loop. This pass checks channel host commands (such `Send Special Character'), timer functions, condition that requires posting external service request (for example, Receive FIFO full, Transmit FIFO empty, modem signal change, on). required, firmware posts service request within queue appropriate servicerequest logic. then continues normal operation, until host responds service request. After single pass through outer loop, eight passes through inner loop again made. most cases CL-CD1865 checks appropriate determine which options enabled then modifies processing accordingly. Some control bits must interpreted moved CL-CD1865 firmware from their location Option registers other locations device. Therefore, host must notify CL-CD1865 when these bits modified. Then, CL-CD1865 alters channel commanded. details channel command functions, refer Section 5.2.
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
RECEIVE DATA COUNT REGISTER
RECEIVER FIFO
RECEIVE STATUS FIFO
BACKGROUND CODE: H.R.-TO-FIFO TRANSFER, FLOW CONTROL, OTHER FEATURES (POLLING LOOP) FULL/ EMPTY FOREGROUND CODE: ASSEMBLY, S.R.-TO-H.R. TRANSFER (INTERRUPT-DRIVEN) RECEIVER SHIFT REGISTER
RECEIVER HOLDING REGISTER
RECEIVER
TRANSMITTER FIFO
BACKGROUND CODE: FIFO-TO-H.R. TRANSFER, FLOW CONTROL, OTHER FEATURES (POLLING LOOP) TRANSMITTER HOLDING REGISTER FULL EMPTY
FOREGROUND CODE: DISASSEMBLY, H.R.-TO-S.R. TRANSFER (INTERRUPT-DRIVEN)
TRANMSITTER SHIFT REGISTER
TRANSMITTER
Figure 3-2. Foreground/Background Internal Structure August 1996
DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
POWER-ON RESET
INITIALIZATION
OUTER_LOOP HOST COMMAND PROCESSING
GLOBAL (SOFTWARE) RESET
TIMER FUNCTIONS
INNER_LOOP
RCV_HLD_REG FULL
PROCESS RECEIVE CHAR.; CHECK SPECIAL FEATURES; PLACE FIFO
XMT_HLD_REG EMPTY PROCESS RECEIVE INTERRUPT
PROCESS TRANSMIT CHAR.; CHECK SPECIAL FEATURES; FETCH FROM FIFO
RECEIVE SERVICE REQUEST SCANNING
TRANSMIT SERVICE REQUEST SCANNING
MODEM SERVICE REQUEST SCANNING
Figure 3-3. Internal Operation Flow Chart
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
Service Request Interrupt Operation
CL-CD1865 enhances design efficiency, because intelligent device that more closely resembles add-in controller board than mere collection TTL. Conventional UARTs basically passive, `dumb' logic. example, when polling device channels requiring service, each channel individually tested. Because this, certain restrictions placed when FIFOs accessed. CL-CD1865 processor must determine what host doing, when manage queue events correctly efficiently.
multiple-CL-CD1865 designs share service requests daisy-chain acknowledgments. Whenever CL-CD1865 processor determines that more channels need service from host, loads appropriate service-request state machine with information about type request. service-request state machine that level then asserts request signal. Note that three request signals active same time. this point, CL-CD1865 determined which request should handled first simply asserts lines, required status various channels. (This true even AutoPri Option enabled; AutoPri takes effect when service request acknowledged, that time CL-CD1865 determines which most important request.) host, after noticing that more three service request pins active either because host interrupted polled external internal CL-CD1865 status register decides which requests more than active) services first. host begins service operation issuing Service Acknowledge cycle. pose this cycle cause CL-CD1865 internal state that type request. (Note that AutoPri set, necessary host determine which level service request acknowledge; simply acknowledges CL-CD1865 request CL-CD1865 returns vector highest-priority active request.) AutoPri being used, CL-CD1865 needs informed which three possible pending requests host wants acknowledge. There different ways CL-CD1865 informed this hardware software. hardware method based value address bus. CL-CD1865 determines type request being acknowledged value placed address during acknowledge cycle. This method used Motorola®-family processors. host places level interrupt being serviced low-order address bits during interrupt acknowledgment cycle. When host performs Service Acknowledge cycle, CL-CD1865 compares value address with three unique values stored three
FUNCTIONAL DESCRIPTION
Interrupt-Driven Versus Polled
Choosing software interface, interrupt-driven versus polled, critical overall system performance. This choice also affects software written. hardware implementation, programmer choice Mixed mode, that when poll versus when interrupt-driven. Mixedmode operation allows programmer optimize efficiency system according changing needs. advantages each method discussed Section 3.5. 3.3.1 Theory Operation CL-CD1865 three independent service request levels, each three categories Receive, Transmit, Modem signal change. priority these lines fixed, determined following three ways:
within CL-CD1865 AutoPriority Option bits. system designer assign priorities manner which three service request lines connected host interrupt controller. Under software control, host system define redefine order vice requests.
Service Request interface host implemented with five signals MREQ*, TREQ*, RREQ*, ACKIN*, ACKOUT*. MREQ*, TREQ*, RREQ* asserted when service request pending; ACKIN* asserted during serviceacknowledgment cycles; ACKOUT* used August 1996
DATA BOOK v2.0
CL-CD1865
Intelligent Eight-Channel Communications Controller
internal registers Modem Service Match register (MSMR), Transmit Service Match register (TSMR), Receive Service Match register (RSMR). These values user system initialization. match occurs only these registers, this informs CL-CD1865 type request being acknowledged. most circumstances address should have value that does match three Service Match register values during acknowledgment cycle. This causes CL-CD1865 recognize that cycle occurring, does assert DTACK*, terminate cycle, take other action. Doing this does affect CL-CD1865, system must have some other provision terminate cycle. example, CL-CD1865 shares interrupt level with another device, different values address should used control responses acknowledgment, cycle should terminate usable way. Service acknowledgments also performed software. host simply reads three CL-CD1865 performs hardware service acknowledge cycle executed. Regardless method acknowledgment used, within CL-CD1865, each service request state machine makes following determination: internal service request pending, there service acknowledge same type, asserts internal-acknowledge-accepted signal back Service Request Controller logic, negates Service Request Output pin, holds acknowledge-out daisy chain negated state. also drives value Global Service Vector register (GSVR) onto data bus, host read part Service Acknowledge cycle. GSVR value placed during Service Acknowledge cycle serves purposes. least-significant three bits GSVR indicate which four types service requests occurring. upper-five bits user-defined serve identify, daisy-chained CL-CD1865 systems, which multiple CL-CD1865s active. service request state machine does have service request pending, there software
FUNCTIONAL DESCRIPTION
acknowledgment address match, passes service acknowledgment down chain asserting ACKOUT*. there match, state machine remains idle. service request pending Receive Service Request handled, CL-CD1865 notified because three Service Match registers have different values them; therefore, only match (receive service, this case) occurred. internal grant from service request state machine causes receive service type code active channel number (previously stored time request posted CL-CD1865 processor) pushed onto service request stack. This automatically causes FIFO pointers active channel, with host intervention. host, this point, information needed handle service request. determines exact type service being requested (Transmit, Receive Good Data, Receive Exception, Modem signal change) which multiple CL-CD1865s requesting service. gets channel number reading Global Service Channel register (GSCR) then proceeds service request. completion service, host performs dummy write CL-CD1865 Interrupt Service Request register (EOSRR), that causes CL-CD1865 exit internal service request state popping service request stack. this time CL-CD1865 ready serviced another outstanding requests. another request same level pending, clock periods after write EOSRR required CL-CD1865 reassert request line. Because CL-CD1865 service request stack, support nested-service requests. example, host middle Transmit Service Request, detect that Receive Service Request asserted, process Receive Service Request, after exiting receive service routine, resume Transmit Service Request. CL-CD1865 stack three deep, three types (one each) nested required. current service request context (for example, stack) readable Service Request Status register. August 1996
DATA BOOK v2.0
CL-CD1865
Intelligent Eight-Channel Communications Controller
Global Service Channel registers (GSCR) actually three registers that provide number channel requesting service. Reading these registers causes CL-CD1865 mask three bits, specifying channel number currently active channel. Normally these registers read host when handling service request. this case, three bits number channel requesting service. three GSCR registers read when CL-CD1865 service-request context, three bits current value CAR. current channel number masked into contents bits this register CL-CD1865 when read host. actual contents register modified. These three registers provided convenience user. most applications, user only uses these locations, register some arbitrary value. However, useful record information about state CL-CD1865 software driving that associated with each three service-request types. this case, user store whatever information required unused bits. Then, when entering service routine, software check these bits find what state they were left this could used `sub-vector'.
3.3.2 Internal Implementation Service Request Logic discussed above, heart each service request level asynchronous state machine. This state machine three inputs:
MATCH from Priority Interrupt Level register comparator, ACKIN* from host system, INTERNAL_REQUEST from CL-CD1865.
NOTE: Software acknowledgments (reads from Service Request Acknowledge registers), effect, force MATCH value true their respective level.
also three outputs:
Svc_Req host system, INTERNAL_GRANT CL-CD1865, ACKOUT*, which combined with other ACKOUT* signals provide ACKOUT* next CL-CD1865 daisy chain.
August 1996
DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
Figure page shows logic implemented state machine, which described Table 3-1. Table 3-1. State Machine Logic
State Name
IDLE (INTERNAL_REQUEST ELSE (ACKIN* MATCH ELSE REQ_ACTIVE (ACKIN* MATCH (ACKIN* MATCH ELSE PASS_ACK (ACKIN* ELSE KEEP_ACK (ACKIN* ELSE
Output Condition
outputs inactive GoTo REQ_ACTIVE GoTo PASS_ACK Stay IDLE GoTo KEEP_ACK Stay REQ_ACTIVE Stay REQ_ACTIVE GoTo IDLE Stay PASS_ACK GoTo IDLE Stay KEEP_ACK
Comments
normal `resting' state pass this acknowledge wait here request asserted keep this acknowledge wait here, some other level wait here ACKOUT* asserted return when ACKIN* gone wait here while ACKIN* active INTERNAL_GRANT asserted return when ACKIN* gone wait here while ACKIN* active
NOTE: denotes point which, there match, CL-CD1865 determines pass down daisy chain. does this reasons: first, unacceptable have ACKOUT* `glitch' low; second, state machine should fast possible. When state machine senses ACKIN* match valid, cannot conclude that should assert ACKOUT*; ACKIN* other service requests levels. could wait results other MATCH comparators; however, this complicates, therefore slows down, response state machine. reason this complication causes delay implement logical function `assert ACKOUT* match') must determine long wait before declaring no-match condition. implement this delay function, synchronous state machine required, which 15-MHz clock, means delay several hundred nanoseconds from ACKIN* ACKOUT*, instead currently specified.
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
IDLE STATE OUTPUTS INACTIVE
INTERNAL_REQUEST ACTIVE
TRUE
REQUEST_ACTIVE STATE ASSERT REQUEST
FALSE
IACKIN* ACTIVE MATCH
TRUE
KEEP_ACK STATE ASSERT INTERNAL_GRANT
FALSE IACKIN* INACTIVE IACKIN* ACTIVE MATCH TRUE FALSE
TRUE FALSE
(This block redundant. placed here emphasize that there match, nothing happens.)
IACKIN* ACTIVE MATCH TRUE PASS_ACK STATE ASSERT IACKOUT*
FALSE IACKIN* INACTIVE FALSE
TRUE
Figure 3-4. Internal Service Acknowledge Decision Tree August 1996
DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
3.3.3 Priorities Fair Share CL-CD1865 implements fair-share mechanism ensure that channels receive equal service, without `data starvation'. Fair share works automatically among channels device across multiple devices. Figure page shows fair-share operational block diagram. each three service request lines, CL-CD1865 monitors both internal external value line. (The external value differ because, multiple-
CL-CD1865 applications, driven other CL-CD1865s.) service acknowledgment cycle, CL-CD1865 checks state both request values. they different, CL-CD1865 determines that there another part also driving request line, does reassert request line until external request gone inactive. This inactive level means every other CL-CD1865 with pending request serviced; therefore, okay reassert requests without controlling host bandwidth.
INTERNAL REQUEST CD1865 INTERNAL REQUEST LOGIC
EXTERNAL REQUEST (I/O PIN)
ASSERT
LATCH
Figure 3-5. Internal Fair-Share Operation
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
Types Service Requests
categor vice requests that CL-CD1865 generate explained below. Each channel's transmitter, receiver, modem pins require service from host occasionally; however, each category service request conditions tolerate different latencies being serviced. Conditions service requests fall into three basic categories:
Exception characters characters with errors that match defined special characters, line breaks, certain time-out conditions. Data must read from Receive FIFO Receive Status FIFO except when CL-CD1865 within context Receive Data Service Request. 3.4.1.1 Receive Good Data Receive Good Data Service Request asserted following three conditions:
RxFIFO threshold reached, FIFO contains Good Data. RxFIFO threshold reached, FIFO contains Good Data, Receive Data Timer times-out. RxFIFO threshold reached, FIFO contains Good Data, newly arrived data contains exception condition.
Data received from remote device needs transferred host. Data from host given Transmitter FIFO, which empty. modem signal changes state.
Three separate service request levels provided support following three categories:
Source Receive data Transmit data Modem signal change Name RREQ* TREQ* MREQ* Request Match Register Name RSMR TSMR MSMR
3.4.1 Receive Service Requests Receive Service Request unique because subtypes; that capable returning different vectors during service request acknowledge cycle. sub-types `Receive Good Data' `Receive Exception'. reason there types within category service request that, while Good Data Exceptions require different handling, they both equal priority, need serviced order they received. example, suppose good characters received, then exception character, then another good character received. There must service request first bytes Good Data, then Exception, then more Good Data. Exception Service Request different level, exception character processed either before after Good Data, sequence should This method also allows Receive Good Data-handling routine host very fast efficient, since only move bytes buffer. special-case conditions separate handler, where they slow down normal data transfers. August 1996
DATA BOOK v2.0
When these conditions occur, modified service request vector indicates host that service request Good Data. CL-CD1865 continues bytes FIFO, increments Count register each good byte added, this allows optimally efficient FIFO. necessary accept Good Data that available when Good Data Interrupt received. host buffer full accept bytes, smaller number (even read, service request context left, host buffer handled first. CL-CD1865 again generates another Good Data Service Request when three conditions listed above met. condition that caused request first place remains true, CL-CD1865 quickly generates another service request. data read, this always case. some, all, available data read, Conditions true, Condition true exception condition cause Good Data Interrupt. this becomes problem, solution temporarily disable receiving interrupts that channel. avoid FIFO overflow, disable channel very long.
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
3.4.1.2 Receive Exception Unusual exception conditions reported host character time through Receive Exception Service Request. with normal receive processing, host determines requesting channel reading GSCR. then determine specific exception(s) reading Receive Character Status register. Exception conditions generated parity errors, framing errors, FIFO overrun, special character recognition, break detect, special feature called Data Timer' (NNDT). NNDT receive timer option generate service request first receive data time-out following transfer data from FIFO host. often useful, when managing relatively large buffers, processor determine that data arrived lately'. This event used transfer contents local buffer that been storing data from CL-CD1865 FIFO host-system processing. This service request receive exception subtype, used signal that time transfer buffer. This feature enabled
disabled controlling NNDT Service Request Enable register. shown Figure 3-6, every time received character loaded into FIFO, timer restarted. timer times-out, CL-CD1865 checks there data FIFO. there Good Data Service Request posted avoid `stale data'. there data FIFO, CL-CD1865 checks that NNDT enabled `armed'. Arming occurs when last character transferred FIFO host. NNDT armed, Receive Exception Service Request posted inform host this event. Note that NNDT armed last character removed from FIFO exception character. Every Receive Exception unique, one-character event. Receive Data Count register meaning, unlike Receive Good Data case, Status byte receive exception handling routine must read. Receive Data Count register associated data character discarded CL-CD1865 service routine. Status byte must read before reading Data byte. Once Data register read, Status byte longer available.
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
BACKGROUND SCANNING DETECTS CHARACTER ARRIVED
.FROM OTHER BACKGROUND PROCESSING.
CHARACTER FIFO; RELOAD TIMER
TIMER
RESUME BACKGROUND SCANNING LOOP.
FIFO EMPTY
POST RECEIVE GOOD DATA SERVICE REQUEST
DATA TIMEOUT FEATURE ENABLED
NNDT INTERNAL FLAG 'ARMED' CLEAR NNDT INTERNAL FLAG
POST RECEIVE EXCEPTION SERVICE REQUEST
RESUME BACKGROUND SCANNING LOOP.
Figure 3-6. Receive Timer Operation August 1996
DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
3.4.2 Transmit Service Requests Each transmitter contains bytes Transmit FIFO addition Transmit Holding register Transmit Shift register. data being transmitted, FIFO status being monitored CL-CD1865. service request invoked following conditions:
3.4.3.1 Using Modem Pins Input/Output pins labelled modem pins general-purpose pins that controlled either CL-CD1865 processor host system. There direct, hardwired connection from modem directly transmitter receiver. This means that these pins used generalpurpose they needed modem-control purposes. Section more details.
Transmit FIFO Empty When Transmit FIFO empty, there still character Transmit Holding register character Transmit Shift register. host character times respond this request without causing Transmit Data Stream. Transmitter Empty Transmit FIFO, Transmit Holding register, Transmit Shift registers empty. This signifies that characters written FIFO completely transmitted.
Implementing Service Requests
CL-CD1865 designed easily interface with processor, efficient flexible enough provide maximum throughput. CL-CD1865 generates service requests waits acknowledgments these from host. However, service requests implemented either hardware software; likewise, acknowledgments affected either offer maximum advantages system designer programmer. This interfacing grouped various steps. Service requests must `noticed' host system before they acted this done following three ways: Provide three levels interrupt support, with three separate levels three separate vectors. This well-suited Motorola 680X0 processors. Provide single level interrupt support; this effective method when using 8-bit processors such Z-80 many Intel® microprocessors. Poll device directly software. Once host `noticed' service request, following choices acknowledging request beginning service Acknowledge request hardwarebased service acknowledgment, typically done interrupt-driven systems. Acknowledge request software reading from register CL-CD1865.
host select which these causes Transmit Service Request, used programming options Service Request Enable register (SRER). Data must into Transmit FIFO time other than when CL-CD1865 Transmit Service Request context that channel. During transmit service, characters eight) placed into FIFO Transmit Data register (TDR). 3.4.3 Modem Signal Change Service Requests CL-CD1865 programmed assert service request when channel's modem input signals changed states. change-detect options programmed Modem Change Option registers. Individual modem service requests enabled setting corresponding bits Service Request Enable register. host must read Modem Change register during modem change service determine which modem signal changes were detected. This indicated appropriate location. Modem Change register must reset host before exiting service request because CL-CD1865 does this. Refer Section more details.
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
Table 3-2.
Service Request Methods
host detects Service Request Three-level Hardware Interrupt Hardware-based service acknowledge Software-based service acknowledge
Full Interrupt Type
Single-level Hardware Interrupt
recommended (Inefficient)
Software Polling
host acknowledges Interrupt
recommended (Inefficient)
Full Interrupt Type
Single Interrupt
Software Polled
Thus, there theoretically possible options interfacing CL-CD1865 host system. methods practical implement without external hardware, offer performance advantage. Each other four methods advantages drawbacks depending type host being used whether that host supports more than CL-CD1865. four methods used listed Table 3-2. This method called `Full Interrupt Type system fully interrupt driven with acknowledgments hardware. requires host with least three interrupt priority levels available ability acknowledge multiple levels. This technique used Motorola 680X0 processors. most efficient method when host relatively fast interrupt context switch time when host duties other than driving CL-CD1865s. This method called `Full Interrupt Type still three levels interrupt, provides single acknowledgment level. commonly used Intel-type processor systems where there 8259A interrupt controller. 8259A receives three levels interrupt, provides vector host rather than that CL-CD1865s. Then host acknowledges CL-CD1865s Service Request reading Vector register.
DATA BOOK v2.0
This method called `Single Interrupt', best-suited systems having only single interrupt input, such most 8-bit microprocessors. After host receives interrupt entering interrupt service routine, reads CL-CD1865 evaluate which three types service requests responsible interrupt.Then acknowledges interrupt reading appropriate Request Acknowledge register. Note that single interrupt signal must generated logical three request outputs with external output gates, `wireOR'ing' them. This method called `Software Polled'. Polling often used situations where host system primarily dedicated servicing serial channels other tasks perform. usually better when host long interrupt context switch time. this method, host periodically checks CL-CD1865s determine service requests pending. they are, host acknowledges them software proceeds with service.
advantages CL-CD1865 that allows above techniques, combination. Such combination referred `Mixed-mode operation'. typical mixed-mode design, normal interrupts used signal host that service required. After host enters interrupt vice routine, vices
FUNCTIONAL DESCRIPTION
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
CL-CD1865 that generated service request. Then host polls CL-CD1865s determine more channels require service. host finds channel requiring service, handles usual manner, then proceeds poll more service requests. This process continues until CL-CD1865s handled. Because host exiting re-entering interrupt context each time, much host time saved, resulting even faster overall performance. Advantage mixed-mode design that software complete control whether fully interrupt driven poll certain circumstances. mixed-mode design recommended tune system optimum performance. CL-CD1865 evaluation board employed analyze CL-CD1865 performance evaluate different software implementations. Basis Commu-
nications testing AT-compatible '386 machine) found that mixed-mode system provided highest overall throughput with minimum host loading. This generally found case with host processors that have relatively long interrupt response times, such Intel '386. 3.5.1 Method Full Interrupt Type Three-Level Interrupt with Three-Level Acknowledge This method illustrated Figure 3-7. bestsuited 680X0-family processors. three CL-CD1865 service request lines connected Interrupt Priority Encoder. When host performs interrupt acknowledgment cycle, CL-CD1865 responds with vector. host uses this vector jump directly appropriate service routine. Other methods also used with 680X0-based system.
RREQ* TREQ* MREQ* EIGHT-LEVEL PRIORITY ENCODER ACKOUT* ACKIN*
CL-CD1865
D0-D7 A3-A6 A0-A2 RREQ* TREQ* MREQ* ACKIN* ACKOUT*
IPL1 IPL2 IPL3
M68000 MICROPROCESSOR
A8-A23 A4-A7 A1-A3 D0-D7
ADDRESS DECODE LOGIC
CL-CD1865
D0-D7 A3-A6 A0-A2
Figure 3-7. Three-Level Interrupt with Three-Level Acknowledge Example August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
CL-CD1865
Intelligent Eight-Channel Communications Controller
3.5.2 Method Full Interrupt Type Three-Level Interrupt with SingleLevel Acknowledge This method illustrated Figure 3-8. useful with 80X86 systems that 8259A Interrupt Controller. Since 8259A supplies vector host when INTA cycle occurs, host simply read CL-CD1865's vector
method described polled interface example separate device select decode provided drive ACKIN* input. After 8259A supplies vector 80X86 host CPU, host performs software acknowledgment CL-CD1865, transfers CL-CD1865 vector host. This allows service request processed.
INTERRUPT CONTROLLER (8259A EQUIVALENT)
RREQ* TREQ* MREQ* ACKOUT* D0-D7 A3-A6 A0-A2 ACKIN*
CL-CD1865
MICROPROCESSOR RREQ* TREQ* MREQ* ACKIN* A8-A23 A4-A7 A1-A3 D0-D7 ADDRESS DECODE LOGIC D0-D7 A3-A6 A0-A2 ACKOUT*
CL-CD1865
Figure 3-8. Three-Level Interrupt with Single-Level Acknowledge Example
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DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
3.5.3 Method Interrupt Interface, Single-Level Interrupt with SingleLevel Acknowledge This method illustrated Figure 3-9. bestsuited host systems having single interrupt input. three service request lines from
CL-CD1865 through `OR' gate host's interrupt input. When interrupt occurs, host system polls CL-CD1865s, determines which three levels interrupted, acknowledges accordingly.
RREQ* TREQ* MREQ* ACKOUT* ACKIN*
CL-CD1865
D0-D7 A3-A6 A0-A2
MICROPROCESSOR RREQ* TREQ* MREQ* ACKIN* ADDRESS DECODE LOGIC ACKOUT*
CL-CD1865
D0-D7 A3-A6 A0-A2
A8-A23 A4-A7 A1-A3 D0-D7
Figure 3-9. Single-Level Interrupt with Single-Level Acknowledge Example August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
CL-CD1865
Intelligent Eight-Channel Communications Controller
3.5.4 Method Polled Interface This method illustrated Figure 3-10. Polled operation used with type host CPU, used combination with interrupts provide mixed-mode system optimized particular application. polled system, host reads Service Request Status register (SRSR) within CL-CD1865 determine whether there channels that need service. (Note that unlike traditional UARTs, only register needs read determine there channels device that need attention, this saves time). host finds channels needing service, acknowledges required type reading three Request Acknowledge registers. These provide vector that used jump directly correct service routine. Processing from this point proceeds case interrupt-driven operation. Note that difference between this method Method lies host system becomes aware need vice CL-CD1865. Method single interrupt starts process. Method host polls periodically. methods combined interrupt triggers first service, host continues poll until other pending requests serviced.
There difference between CL-CD1865 conventional dumb UARTs that makes CL-CD1865 more efficient even when operating polled environment. With dumb UART, host polls each channel turn determine whether data. With CL-CD1865, host polls CL-CD1865s group whether data. does, CL-CD1865s indicates channel, rather than host testing each channel turn. fact, possible host dictate which channel serviced; CL-CD1865 determines this order. This minimizes both number polling steps required amount time each needs. This also ensures fair, balanced service channels. There several ways that host system poll CL-CD1865. Each method certain advantages. most direct method read Service Request Status register (SRSR). This register contains three bits that indicate whether there request pending receive, transmit, modem signal change, CL-CD1865 being read. There three more bits that provide same information CL-CD1865s system these three bits reflect state wire-OR'ed external request lines. Thus single read operation determine there activity.
August 1996
DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
RREQ* TREQ* MREQ* ACKOUT* ACKIN*
CL-CD1865
D0-D7
A3-A6 A0-A2
MICROPROCESSOR RREQ* TREQ* MREQ* ACKIN* ACKOUT*
CL-CD1865
D0-D7
A4-A7 A1-A3 D0-D7
A3-A6 A0-A2
Figure 3-10. Simple Software Polled Interface Example
FUNCTIONAL DESCRIPTION
DATA BOOK v2.0
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
3.5.5 Comparison Interrupt Polled Code Sequences Figure 3-11 Figure 3-12 show code sequences polled interrupt service request methods.
READ SERVICE REQUEST STATUS FROM SRSR
RECEIVE REQUEST PENDING?
GOOD DATA HANDLE `BAD' DATA
TRANSMIT REQUEST PENDING?
TRANSMIT ROUTINE
READ REQUESTING CHANNEL NUMBER
READ NUMBER BYTES FROM RDCR
MODEM SIGNAL CHANGE REQUEST PENDING?
MODEM ROUTINE
HOST'S BUFFER POINTERS
LOOP COUNTER RDCR
READ
READ RRAR ACKNOWLEDGE, STATUS VECTOR
WRITE DATA POINTER LOCATION
INCREMENT POINTER
DECREMENT LOOP COUNTER
LOOP COUNTER
SAVE POINTER
EXIT
Figure 3-11. Polled Code Sequence August 1996
DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
INTERRUPT OCCURS ENTRY POINT GOOD DATA INTERRUPT SERVICE ROUTINE READ REQUESTING CHANNEL NUMBER READ NUMBER BYTES FROM RDCR HOST'S BUFFER POINTERS LOOP COUNTER RDCR
READ WRITE DATA POINTER LOCATION INCREMENT POINTER DECREMENT LOOP COUNTER
LOOP COUNTER
SAVE POINTER EXIT
Figure 3-12. Interrupt Code Sequence
3.5.6 Cascading Service Requests with Multiple CL-CD1865s Regardless method used support service requests, multiple CL-CD1865s cascaded tying together MREQ* lines, TREQ* lines, RREQ* lines. These lines open-drain they wire-OR'ed. CL-CD1865s then daisy chained simply connecting ACKOUT* device ACKIN* next. host knows which CL-CD1865 requesting service value returned through Global Interrupt Vector register. CL-CD1865s cascaded daisy chain this
FUNCTIONAL DESCRIPTION
manner. Since multiple daisy chains possible, maximum number CL-CD1865s large. 32-per-daisy-chain limit five bits GSVR. These bits used identify which CL-CD1865 responded service request acknowledge cycle. user must program different values into upper-five bits each CL-CD1865s GSVR. Note that thirty-two CL-CD1865s logical limit daisy chain. Since takes over 1000 acknowledgment ripple down devices, efficient have long chain heavytraffic applications. August 1996
DATA BOOK v2.0
CL-CD1865
Intelligent Eight-Channel Communications Controller
NOTE: some systems that daisy chain many CL-CD1865 devices, potential timing hazard exists host processor does allow sufficient time removal ACKIN*/ACKOUT* daisy-chain signal propagate through devices. event that host processor begins operations with another section logic applies (RD* Intel environment) while active ACKIN* being applied CL-CD1865 propagation delay time, unpredictable results occur. This constitutes illegal acknowledge cycle. failure mode most often cessation service requests from device, especially type that being serviced when illegal access occurs. Take care ensure that 35ns propagation delay device included wait-state generation.
software-based mechanism uses three registers Receive Request Acknowledge register, Transmit Request Acknowledge register, Modem Request Acknowledge register. Reading these registers effect acknowledging service request, data read appropriate vector, that contents Global Interrupt Request Vector register. lowthree bits this register modified indicate specific type interrupt being acknowledged. host reads these registers when service request pending, either things happen. daisy chaining acknowledgments enabled, ACKOUT* CL-CD1865 asserts. daisy chaining enabled, part supplies vector with low-three bits `0'. Thus, possible `fish' service requests, that acknowledge each CL-CD1865 turn until non-zero vector received. `Fishing' usually efficient software technique, useful some circumstances. example, systems that normally interrupt-driven, where interrupts available diagnostics other reasons, host determine service request pending reading appropriate Request Acknowledge register. CL-CD1865 must configured daisy chain; this case returns vector request pending, `00' request pending. host three levels request turn. This method works either single CL-CD1865s multiple devices. multiple-device systems, either disable daisy chaining devices `fish' each individually, disable daisy chaining last device only `fish' device beginning chain. Both methods acknowledging service requests used interchangeably. usually advantageous Mixed mode. example, after receiving interrupt servicing normal manner, host should read Service Request Status register (SRSR) other requests pending. host acknowledge reading appropriate Request Acknowledge register (RRAR, TRAR, MRAR) proceed service request. This avoids time required host exit interrupt routine, only re-enter immediately next request.
3.5.7 Multiple CL-CD1865s without Cascading possible interface several CL-CD1865s without using cascade feature. There advantage this because there less delay incurred while waiting service acknowledgment ripple down chain devices. There possible disadvantages. each CL-CD1865's three service request lines separate input interrupt controller, interrupt controller more complex, fair-share feature does work. service request lines wire-OR'ed, fair share works, host test each CL-CD1865 turn which generated service request. implement this method, simply connect CL-CD1865 address data lines usual manner. 3.5.8 Acknowledging Service Requests mentioned Section page different methods used acknowledge service request. method hardware-based, other software-based. hardware-based mechanism specific type cycle that uses ACKIN* ACKOUT* signals Service Match registers CL-CD1865. acknowledge cycle defined where ACKIN* active inactive. This method used processors that perform interrupt acknowledge cycles, such 680X0.
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DATA BOOK v2.0
FUNCTIONAL DESCRIPTION
CL-CD1865
Intelligent Eight-Channel Communications Controller
SYSTEM INTERFACE SYSTEM CLOCK
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE ENGINE RREQ* TREQ* MREQ* ACKOUT* ACKIN* SERVICE REQUEST LOGIC TRANSMIT SERVICE REQUEST QUEUE RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RXDATA TXDATA RECEIVE SERVICE REQUEST QUEUE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RXDATA TXDATA RXDATA TXDATA
MODEM SERVICE REQUEST QUEUE ADR[0-6] DATA[1-7]
RECEIVE ENGINE TRANSMIT ENGINE INTERRUPT HANDLER DUAL-BAUD RATE GENERATORS RECEIVE ENGINE
RXDATA TXDATA
RXDATA TXDATA
DTACK* INTEL/MOT* RESET* DBLCLK NO_OSC OSC1 OSC2
INTERFACE
TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
CHANNEL TIMER
RXDATA TXDATA
PINS (MODEM CONTROL)
RTS* CTS* DTR* DSR* LINES LINES LINES LINES LINES LINES LINES
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
RXDATA TXDATA
RECEIVE ENGINE TRANSMIT ENGINE DUAL-BAUD RATE GENERATORS
RXDATA TXDATA
Figure 4-1. Internal Block Diagram August 1996
SYSTEM INTERFACE SYSTEM CLOCK
DATA BOOK v2.0
CL-CD1865
Intelligent Eight-Channel Communications Controller
System Interface Considerations
When using CL-CD1865, areas where system architects, designers, programmers should consider options system clock speed, unclocked versus clocked-host interface.
System Clock Rate Options
4.2.1 System Clock System clock high-frequency clock (supplied user) used CL-CD1865 receive necessary timing. CL-CD1865 capable handling system clock levels TTL-compatible voltage swings; however, specifications identical families logic. Specifically, clock signal (and reset signal) have lower higher than worst-case specifications some families. general, family adequate heavily loaded. Refer Specifications Section details. CL-CD1865 operate from either external clock source crystal. external clock either rated frequency, crystal must Using oscillator crystal recommended wherever possible. using clock option, please refer Table page details duty cycle requirements, clock period, minimum clock-high clock-low times. CL-CD1865 operated from main system clock clock. Operation from main system clock reduce number clocks required, allows interface between system CL-CD1865 clocked, general, typical system clock speeds exact baud-rate multiples. rates received from clock, important consider this when selecting clock value. exact baud rates needed, system clock convenient value, CL-CD1865 must supplied with clock crystal. CL-CD1865 uses several pins support various clock options. OSC1 OSC2 connection crystal 2x-clock frequency. NO_OSC strapping option that disables internal oscillator crystal being used. August 1996
Pulling NO_OSC `high' turns oscillator reduces power consumption internal noise. NO_OSC must `high' oscillator being used. DBLCLK input 2x-external clock. input 1x-external clock. crystal being used, both DBLCLK must grounded. Table various configurations. Table 4-1.
Pins
DBLK NO_OSC OSC1
Various Configurations
Option
Option
DBLCLK
Crystal
Crystal
4.2.2 External Clock recommended that option (oscillator crystal) used wherever possible. Figure shows possible design configuration clock circuitry crystal being used. Please refer CL-CD1865 Evaluation documentation details design configurations used. crystal used evaluation board 66-MHz third overtone part.
200K-500K
Figure 4-2. Clock Option
DATA BOOK v2.0
SYSTEM INTERFACE SYSTEM CLOCK
CL-CD1865
Intelligent Eight-Channel Communications Controller
Figure shows conceptual model clock oscillator circuitry.
NO_OSC OSC1 CKOUT
OSC2 DBLCLK FROM RESET LOGIC
Figure 4-3. Clock Oscillator Circuitry
4.2.3 Clock Option recommended that option used where ever possible. using options, refer page clock duty cycle requirements. 4.2.4 Rate Options CL-CD1865 supports independent transmitter receiver rates each eight channels. rate determined 16-bit period value (divisor) stored Transmitter Rate Period registers (TBPRH TBPRL), Receiver Rate Period registers (RBPRH RBPRL). These registers establish period corresponding Transmitter Receiver Rate counters. given rate, value loaded determined following equation:
frequency Hertz} Rate Divisor -(16 desired Rate bits second})
This equation yield non-integer result. nearest integer value optimum choice that rate system clock combination. value loaded Rate Period registers must that integer expressed 16-bit binary value. rounding necessary, percentage rate error calculated
Rate Divisor Integer Rate Divisor
popular rates their corresponding divisors various system clock rates shown Table 4-2.
SYSTEM INTERFACE SYSTEM CLOCK
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CL-CD1865
Intelligent Eight-Channel Communications Controller
Table 4-2.
Rate
1200 2400 4800 9600 19200 38400 56000 57600 64000 76000 115200
Rate Constants,
Divisor
493e 35b6 1adb
Table 4-4.
Rate
1200 2400 4800 9600 19200 38400 56000 57600 64000 76000 115200
Rate Constants,
Divisor
2c64 208d 1047
Error
0.000% 0.000% 0.000% 0.015% 0.015% 0.044% 0.073% 0.073% 0.393% 0.538% 0.461% 0.538% 0.703% 0.509% 0.538%
Error
0.003% 0.004% 0.008% 0.016% 0.032% 0.032% 0.160% 0.160% 0.160% 1.376% 1.440% 1.376% 2.400% 2.720% 1.376%
divisor values hex.
divisor values hex.
Table 4-3.
Rate
1200 2400 4800 9600 19200 38400 56000 57600 64000 76000 115200
Rate Constants,
Divisor
377d 28b1 1458
Table 4-5.
Rate
1200 2400 4800 9600 19200 38400 56000 57600 64000 76000 115200
Rate Constants,
Divisor
214b 186a
Error
0.003% 0.003% 0.006% 0.006% 0.006% 0.006% 0.147% 0.147% 0.467% 0.762% 0.352% 0.467% 1.696% 2.144% 3.219%
Error
0.003% 0.000% 0.000% 0.032% 0.032% 0.096% 0.160% 0.352% 0.352% 1.696% 1.547% 1.696% 2.400% 2.720% 1.696%
divisor values hex.
divisor values hex.
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SYSTEM INTERFACE SYSTEM CLOCK
CL-CD1865
Intelligent Eight-Channel Communications Controller
4.2.5 Maximum Throughput Limits CL-CD1865 internally fully static, synchronous design. Consequently, maximum data rate handled CL-CD1865 determined clock speed which operating. There fixed number CL-CD1865 processor cycles required process each character; slower CL-CD1865 processor rate equates slower rate. minimum clock frequency required determined data rate needed support. general, CL-CD1865 maintain 100% full-duplex throughput when divisors greater used. given master clock frequency, this limitation used determine maximum rate which system sustain 100% throughput both receive transmit. Divisors small used, however degradation throughput observed. This degradation seen gaps between transmit characters are, effect, extra long stop bits. This failsafe condition. Divisors smaller than work application less than eight channels enabled.
rect results. Within context service request, effective channel access value automatically controlled CL-CD1865, thus should modified host system during service-request processing. advantage this method that host never performs address computation access CL-CD1865 during service requests. Because only registers specific active channel (that being serviced) accessible host within service request routine. automatic indexing feature handles this, thus avoiding burden host. Refer Section Indexed Indirect registers details. 4.3.1 Intel® Versus Motorola® Interface Signals Addressing CL-CD1865 supports handshake methods. patterned after Motorola 680X0-family processors, other after Intel 80X86-bus interfaces. interface selection achieved INTEL/MOT* signal. When this signal `high', Intel interface selected, when this signal `low', Motorola interface selected. This selection affects logical meaning pins, effect timing. signals having dual meaning versus DS*, versus R/W*. When Intel interface selected, these pins function WR*. These pins connected either IOR* IOW*, MEMRD* MEMWR* depending whether CL-CD1865 mapped into memory space. These pins then serve select CL-CD1865, when either active (along with ACKIN*) CL-CD1865 considers itself selected. ACKIN* must never active same time. When Motorola interface selected, these signals function R/W*. must asserted (along with ACKIN*) types cycles, R/W* should when writing device. either case, choice interface entirely user. This feature user convenience, accommodate address bus-control August 1996
CL-CD1865 Basic Interface Addressing
CL-CD1865 addressed through activelow Chip Select (CS*) conjunction with seven Address Inputs A[0:6] that mapped CL-CD1865 internal addresses addressing modes global channel. Channel Addressing mode, bits defining channel accessed provided from Channel Access register (CAR) within CL-CD1865. most-significant Address Input (A6) performs selection between global- channel-specific addresses. this `1', address global, associated with specific channel. this `0', address channel-related. With exception FIFOs, channel-specific registers accessed first setting required channel number low-three bits Channel Access register. FIFOs only accessed within context service routine. Attempting force access particular FIFO setting causes unpredictable incor48
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CL-CD1865
Intelligent Eight-Channel Communications Controller
logic that used. CL-CD1865 8-bit data bus, common practice (when connecting 8-bit peripherals 32-bit systems) connect them only lane, 1-byte position. Thus, CL-CD1865 registers only appear host's address space every other byte address. most common practice connect CL-CD1865 portion data labelled D0-D7. little-endian processors, such Intel's, CL-CD1865 appears even addresses big-endian processors, such Motorola's, CL-CD1865 appears addresses. 4.3.2 Unclocked Versus Clocked Interface Depending type speed host processor, another important choice determining whether system interface will clocked unclocked with host clock. Because there single clock both interface bitrate generation, decision either Clocked Unclocked interface affected whether exact rates required. Most applications require exact rates, operate with rates varying percent exact rates required, clock speed must baud-rate multiple. method interfacing preferable another certain applications. Although easiest interface CL-CD1865 using unclocked handshake supplied DTACK*, some cases better design clocked interface. latter true host system running same clock speed multiple) CL-CD1865 speed.
one), feeding into wait-state generator. Figure page shows typical maximum cycle time clock periods plus though typically less because this specification based worst-case internal synchronization delays. Using DTACK* saves time; however, permissible hard-wire wait-state generator maximum time.
Clocked Interface
CL-CD1865 interface controlled state machine that samples falling edge clock. External strobes (CS*, DS*, R/W*; CS*, WR*) that meet setup time requirement cause cycle begin. external interface designed meet these setup CL-CD1865 access cycles. Figure page shows typical Clocked interface. cycle consists half-clock periods. During clock-low period, transaction internally, local arbitration occurs. During clock-high period, read write transaction occurs. write cycles, data from host latched internally low-to-high clock transition. read cycles, data available shortly after clock-high period. Read write cycles differ slightly timing; during write, permissible remove relatively early during high-clock period, however, this cannot done during read cycles. Strobe used output enable, must remain data appear external data bus. Service request acknowledgment cycles follow different timing than ordinary read cycles. First, necessary have address stable before asserting ACKIN*. Second, setup time from ACKIN* RD*) going falling clock edge longer additional internal logic involved service request acknowledge cycles.
Unclocked Interface
Unclocked interface easiest interface implement. Simply connect address, data, control lines customary manner, DTACK* control number wait states either connecting processor's DTACK*
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SYSTEM INTERFACE SYSTEM CLOCK
CL-CD1865
Intelligent Eight-Channel Communications Controller
A[0:6]
R/W*
CS*,
DB[0:7]
DTACK*
Figure 4-4. Typical Unclocked Interface
CL-CD1864 CLOCK
CYCLE BEGIN
R/W*
DON'T CARE
ADDRESS
DON'T CARE
VALID
DON'T CARE
DATA-READ
UNDEFINED
VALID
DTACK*
Figure 4-5. Typical Clocked Interface August 1996
SYSTEM INTERFACE SYSTEM CLOCK
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CL-CD1865
Intelligent Eight-Channel Communications Controller
Interface Examples
There some general design considerations when interfacing CL-CD1865 host environment. three Service Request pins (MREQ*, TREQ*, RREQ*) change time, this introduce metastability problems interrupt controller requires clocked signals. When designing, take care that signals stable when needed. vice Request type being acknowledged negated service acknowledgment cycle. Often, during course servicing channel, another channel reaches state where request would assert, example, while servicing receive channel one, channel two's FIFO fills. Service Request bits Service Request Status register (SRSR) does reassert until approximately clock periods after host completes write Service Request register (EOSRR). polled mixed-mode systems, determine whether another service request same level pending, make sure that host does re-read SRSR quickly, insert No-Operation similar) instruction. Performing `invalid' service acknowledgment cycle CL-CD1865 permissible, cause problems certain circumstances. Invalid Service Acknowledgment acknowledgment which there request pending. service request acknowledgment cycle performed host when service request pending, either things occur. value address matches three values three Service Match registers (MSMR, TSMR, RSMR), daisy chaining enabled, CL-CD1865 assumes that another device down daisy chain should receive request, asserts ACKOUT* pin. This propagates down CL-CD1865 chain until eventually last CL-CD1865 asserts ACKOUT*. this point, system waits endlessly unless cycle terminates. best method connect ACKOUT* last CL-CD1865 chain bus-error input host. there multiple
CL-CD1865s that cascaded, ACKOUT* signals should OR'ed together through gate PAL. acknowledgment occurs value address does match Match registers, first CL-CD1865 chain does pass along assert DTACK* system waits endlessly unless there time-out other mechanism detect this condition. either these circumstances, `value' data likely because floating (this system dependent). make robust design, valid Global Service Vector register (GSVR) value. daisy chaining enabled, then CL-CD1865 returns vector `00' invalid acknowledgments. 4.4.1 Interfacing 80X86-Family Processors Intel 80X86 family processors often 8259A interrupt controller, which supplies vector during INTA cycle. easiest interface CL-CD1865 Intel processor Mixed mode, described Section 3.5. There `bug' 8259A aware 8259A change prioritizing eight inputs, which result acknowledge outputs going briefly (~30 input changes certain time. This typically occurs higher-priority input 8259A asserts when 8259A about issue acknowledge lower-priority device. this occurs beginning cycle, this pulse cause CL-CD1865 (and other devices) malfunction. sure that this does occur. Intel 8259A Data Sheet details. 4.4.2 Interfacing 680X0-Family Processors 68000-family interface quite straightforward. three service request lines through priority encoder 680X0 inputs. CL-CD1865s ACKIN* driven decoder. When 680X0 performs Interrupt Acknowledge cycle, drives address lines with three-bit value indicating level being serviced. other address lines
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SYSTEM INTERFACE SYSTEM CLOCK
CL-CD1865
Intelligent Eight-Channel Communications Controller
level being serviced corresponds level assigned CL-CD1865, external decoding logic should assert CL-CD1865 ACKIN* pin. value address lines programmed into Service Match registers, CL-CD1865 recognizes acknowledgment proceeds described Service Request Section 3.3.1. CL-CD1865 service requests also routed single interrupt level using Mixedmode interface, described Section 3.5. 4.4.3 Interfacing CL-CD1865 directly interfaced bus, only requires small amount logic complete interface. This necessary because service request acknowledgment works CL-CD1865. defines seven levels interrupts; each level shared among multiple
cards. During Interrupt Acknowledge cycle, provides three bits address bus, indicating level being acknowledged (A1-A3). Each card must pass along interrupt levels using CL-CD1865 does automatically pass interrupt acknowledgment. recognize this difference cause problem, suppose that three Service Request lines from CL-CD1865 connected levels (see Figure page 52). Also, attach 74XX244 that during Interrupt Acknowledgment cycle provides 8-bit code consisting three address bits plus five more hard-wired bits CL-CD1865. Now, whenever acknowledgment level interrupt occurs, CL-CD1865 either responds passes acknowledgment properly. acknowledgment occurs levels 1-4, daisy chain `breaks' because CL-CD1865 does recognize match.
ACKOUT* IRQ7* IRQ6* IRQ5* ACKIN* A1-A7 IACK* 74XX244 (BUFFERS SHOWN) A1-A3 ARBITRARY VALUE CD1865
RREQ* TREQ* MREQ* ACKOUT* ACKIN* A0-A6
Figure 4-6. Incorrect Interface
SYSTEM INTERFACE SYSTEM CLOCK
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CL-CD1865
Intelligent Eight-Channel Communications Controller
This condition easily rectified, shown Figure page used assert ACKOUT* whenever ACKIN* occurs level being used CL-CD1865. programmed fixed levels. example, current Interrupt level 1-4, asserts ACKOUT* whenever ACKIN* active.
current level 5-7, asserts ACKOUT* when ACKOUT* from CL-CD1865 active. required, assignment Interrupt levels CL-CD1865 field-programmable supplying additional inputs PAL, indicating levels being used CL-CD1865.
ACKOUT* IRQ7* IRQ6* IRQ5* IRQ4* IRQ3* CL-CD1865 IRQ2* IRQ1* ACKIN* A1-A7 A0-A6 RREQ* TREQ* MREQ* ACKOUT* ACKIN*
74XX244 (BUFFERS SHOWN) A1-A3 ARBITRARY VALUE
Figure 4-7. Correct Interface
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DATA BOOK v2.0
SYSTEM INTERFACE SYSTEM CLOCK
CL-CD1865
Intelligent Eight-Channel Communications Controller
SERIAL INTERFACES
Receiver Operation
5.1.1 Basic Operation receivers disabled upon master reset. prepare receiver, first initialize then enable Once initialized enabled, receiver monitors Line waits high-to-low transition, which indicates Start bit. This sampling performed one-eighth System-clock rate regardless Programmed rate, provides accuracy synchronization with incoming data. Figure below CL-CD1865 synchronization. Once transition detected, receiver checks Input state again half-bit time later) validate that Start bit. valid Start defined `space' logic `0'. Input longer `space', then false Start assumed receiver resumes search high-to-low transition. valid Start detected, Input sampled one-bit time intervals middle ensure stable data. Characters assembled according programmed content Channel Option register (COR1).
Valid character framing (presence Stop bit), Optional Parity bits checked. After character assembled, placed temporary Holding register. Then CL-CD1865 processor checks error conditions, FIFO overrun, special character match before placing character corresponding status into Receive Status FIFOs. 5.1.2 Receive FIFO Operation Eight bytes FIFO assigned each receiver data storage, addition Receive Holding register Receive Shift register. Once number data bytes received stored FIFO reaches programmed threshold, CL-CD1865 programmed generate service request. Figure page Receive Operation. Receive FIFO Service Request threshold selected programming RxTH bits Channel Option register service request threshold one-to-eight characters selected. Once this threshold defined, service request automatically triggered when condition met. possible that time host responds service request, there more data FIFO than threshold level.
SAMPLES 1/8-SYSTEM CLOCK
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
full-bit time
Start Detect
1/2-bit time
Figure 5-1. Synchronization CL-CD1865
SERIAL INTERFACES
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CL-CD1865
Intelligent Eight-Channel Communications Controller
overrun condition occurs when data arrives, Receive FIFO Receive Holding register both full. data lost overrun indication flagged character Holding register. That character status including overrun indication eventually transferred host Receive Exception Service Request. Note that this character good, last character received before overrun occurred. Receiver Service Requests enabled disabled Receive Data Service Request Enable register (SRER). Receive Data bit, when `1', enables service requests asserted above causes. Prescaler Period Counter 16-bit counter clocked system clock. system clock 33-MHz clock, maximum count establishes clock tick every 1.9859 Prescaler Period
should generate minimum tick period Receive Time-out Counter 8-bit counter decremental every tick Prescaler Period Counter. maximum count tick, maximum time-out period 0.506 seconds. Receive Time-out always enabled transfer data when Receive Data Service Request enabled. From system applications view-point, this time-out function important asynchronous data transmission. This especially true when FIFO service request threshold FIFO greater than character. Timer Service Request eliminates long response times when excessive delay between characters occurs caused either remote operator line being disabled. Data' Timer Service request, which occurs after data transferred host, used manage transfers from host's receive data buffers.
RECEIVE DATA COUNT REGISTER
RECEIVER FIFO
RECEIVE STATUS FIFO
BACKGROUND CODE: H.R.-TO-FIFO TRANSFER, FLOW CONTROL, OTHER FEATURES (POLLING LOOP) FULL/ EMPTY
RECEIVER HOLDING REGISTER
FOREGROUND CODE: ASSEMBLY, S.R.-TO-H.R. TRANSFER (INTERRUPT-DRIVEN)
RECEIVER SHIFT REGISTER
RECEIVER
Figure 5-2. Receive Operation August 1996
DATA BOOK v2.0
SERIAL INTERFACES
CL-CD1865
Intelligent Eight-Channel Communications Controller
5.1.3 FIFO Timer Operations CL-CD1865 uses Receive FIFO Timer purposes. first avoid `stuck' `stale') data FIFO caused receiving enough characters trip threshold, which causes service request issued. second signal host that there been relatively long pause received data. useful host know that data arrived lately' when managing relatively large buffers. This event flushes buffer host processing. avoid `stuck' data, each time CL-CD1865 moves character into channel's Receive FIFO, sets channel's Receive FIFO Timer value contained channel's Receive Time-out Period register (RTPR). timer expires before data arrives, Receive Good Data sub-type service request asserted channel Receive Data Enable SRER set. other receive timer option generate service request first Receive Data Time-out following transfer data from channel host. This called Data Time-out (NNDT). This service request Receive Exception sub-type with status type `Time-out Exception'. There data character associated with Time-out Exception status. This option enabled disabled controlling NNDT SRER. enough data arrives fill Receive FIFO level RxTh bits COR3, special character arrives Receive FIFO RxSC SRER set, channel asserts Receive Data Service Request without waiting timer expire. timer times-out FIFO empty, `stale data' condition occurred, device posts Receive Good Data Interrupt. timer times-out there data, conditions checked. First, test made feature enabled, true, then another flag tested make sure this first time condition occurred. this true, Receive Exception Service Request posted. (The NNDT internal flag armed when FIFO emptied).
5.1.4 Receive Service Requests Receive Service Request unique sub-types; that capable returning different vectors during service request acknowledge cycle. sub-types Receive Good Data Receive Exception. reason there types within category service request because while Good Data Exceptions require different handling, they both equal priority need serviced order they were received. Suppose, example, good characters received, then erroneous character, then another good character, then there must service request first bytes Good Data, then Exception, then more Good Data. Exception Service Requests were different level, erroneous character would processed either before after Good Data, normal sequence. Receiver Service Requests invoked under several conditions. Conditions that cause Receive Good Data Service Request are:
Receive FIFO threshold reached exceeded Receive FIFO time-out interval between character receptions exceeds time-out value
Conditions that cause Receive Exception Service Request are:
Receive erroneous data (parity error) Framing error Stop bit) data received time-out (optional) Special character detection Break detect
NOTE: Data cannot read from Receive FIFO Receive Status FIFO except when CL-CD1865 within context Receive Data Service Request specific channel.
SERIAL INTERFACES
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CL-CD1865
Intelligent Eight-Channel Communications Controller
5.1.5 Receive Good DataService Request Receive Good Data Service Request asserted following three conditions:
Receive FIFO threshold reached, FIFO contains Good Data. Receive FIFO threshold reached, FIFO contains Good Data Receive Data Timer times-out. Receive FIFO threshold reached, FIFO contains Good Data newly arrived data contains exception condition.
5.1.6 Receive Exception Service Request Unusual exception conditions reported host character time through Receive Exception Service Request. with normal receive processing, host determines requesting channel reading GSCR. then determine specific exception(s) reading Receive Character Status register before performing appropriate action. Receive Exceptions always 1-byte deep; multiple bytes exception conditions causes multiple Receive Exception Service Requests. many exceptions, necessary read Receive Data register after Receive Status register read. example, special character detection enabled, service request recognition special character, character known definition because exception code indicates detected character character sequence. However, every exception byte placed Data FIFO, even though contents that byte suspect data, byte discarded exception service routine regardless whether read host not. This done keep Status Data FIFOs lock-step with each other. This different case Receive Good Data Service Request where user free read many bytes required. Regardless number type exceptions occurring, they reported host character time; that number-of-bytes value Receive Data Count register meaningful. Since every error reported individually, there Receive Time-out Exception generated only characters FIFOs error exception characters.
When these conditions occur, modified service request vector indicates host that service request Good Data. necessary take available Good Data when Good Data Service Request received. host buffer full accept bytes, smaller number (even `0') read. Service request context then left, host buffer dealt with first. CL-CD1865 generates another Good Data Service Request when three conditions listed above met. CL-CD1865 immediately generates another service request condition that caused first place remains true. data read, this always case. some, available data read, Conditions true; Condition true exception condition caused Good Data Service Request. this problem, solution temporarily disable Receive Service Requests that channel. avoid FIFO overflow, delay handling channel long.
August 1996
DATA BOOK v2.0
SERIAL INTERFACES
CL-CD1865
Intelligent Eight-Channel Communications Controller
5.1.7 Types Errors There four types errors recognized CL-CD1865: parity, framing, line break, overrun. parity checking enabled, parity errors logged Status FIFO suspect data placed Receive Data FIFO. error also logged framing, that absence Stop bit. these cases, suspect character Receive Data FIFO appropriate status byte placed Status FIFO. When line-break condition recognized (zero data with zero parity, Stop bit), NULL (00) character loaded into Receive FIFO, break status recorded Status FIFO. Note that parity bits received zeroes, marked both break character parity error. Generally when break character received, pre-set parity error ignored. further FIFO entries made until normal-character reception resumed, example, Start found. line must high then back this occur. Multiple errors byte possible because CL-CD1865 evaluates characters bit-by-bit receives them. example, parity error detected flagged before CL-CD1865 recognizes that framing error occurred. Parity plus framing parity plus break error occur, framing plus break error cannot occur because, character received with every equal `0', marked break character. some bits `1', Stop missing, example, `0', marked framing error. Thus, character cannot have both framing break errors. length Stop checked CL-CD1865. Stop long enough sampled mid-bit time interpreted valid Stop bit. addition other errors, overrun occurs, Overrun Error along with other error bits.
5.1.8 Types Exceptions 5.1.8.1 Special Character Recognition `Special Character Recognition' feature found only CL-CD1865 other Basis Communications data communications controllers. onchip processor compares every good character received with user-defined special characters stored registers device. Both single-character two-character sequence recognition possible. This capability several applications, including In-Band Flow Control. Special-character matches reported host Receive Exception Service Request. Four Special Character registers provided channel, allowing received characters compared many four special characters. However, these four registers shared between Receive Special Character Detection Send Special Character Command, some planning required using these characters. full features options available part Special Character Recognition allows Xon/Xoff flow-control implemented transparently host, same time, detect either other special characters data stream alert host their arrival. user individually enable CL-CD1865 channel recognize special characters. There bits used control various recognition flow-control modes.
SERIAL INTERFACES
DATA BOOK v2.0
August 1996
CL-CD1865
Intelligent Eight-Channel Communications Controller
following four registers used control character recognition: Name
SCDE RxSC XonCH XoffCH
Register
COR3 SRER COR3 COR3
Function
Enables detection special characters. Must In-Band Flow Control work. Enables generation service requests. Cannot overridden other bits. Does need In-Band Flow Control work. Controls single- versus double-character matching. Controls single- versus double-character matching.
following table shows effects XonCH XoffCH: XonCH
XoffCH
Characters matched
Match Match Match Match SCHR1-4 SCHR1 SCHR3 (SCHR2 SCHR4)
(SCHR1 SCHR3) SCHR2 SCHR4 (SCHR1 SCHR3) (SCHR2 SCHR4)
NOTE: two-character pairs share common first character; however, same character must programmed both SCHR1 SCHR2.
Single- versus double-character recognition controlled XonCH XoffCH. single-character compare enabled, CL-CD1865 compares data data stream against four special characters stored Special Character registers (SCHR1-4). fewer than four special characters required, unused Special Character register(s) should disabled duplicating pattern matched unneeded register. When reporting special character, CL-CD1865 always reports lowest-number Special Character register that matches. Special Character Recognition, first characters matched registers SCHR1-4, then XonCH XoffCH according length match wanted. SCDE bit, lastly enable service requests setting RxSC. Special characters reported host placing appropriate status word Status FIFO August 1996
recognized special character Receive Data FIFO. case two-character sequence, only second character stored Receive FIFO. This because there room only character preserving both needed these characters user-defined. 5.1.8.2 Flow-Control Characters Automatic In-Band Flow Control CL-CD1865 transmitter subset Special Character Recognition capability, understand both these features important. Refer Section page transmitter operation. Flow-control characters operation programmable per-channel basis. This important operating systems that allow users co
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