CL-CD2231/CD24XX Product Family CL-CD2231/CD24XX devices two/four

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CL-CD2231/CD24XX Product Family CL-CD2231/CD24XX devices two/four

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CL-CD2231/CD24XX
CL-CD2231/CD24XX Product Family
CL-CD2231/CD24XX devices two/fourchannel synchronous/asynchronous communications controllers, specifically designed reduce hostsystem processing overhead increase efficiency wide variety communications applications. CL-CD2231/CD24XX available 100-pin PQFP CL-CD2231/CD24XX product family: CL-CD2231, CL-CD2401, CL-CD2431, CL-CD2481.
Multi-Protocol Communications Controllers
OVERVIEW
CL-CD2231/CD24XX devices based proprietary, on-chip RISC processor that perform time-critical, low-level tasks that otherwise normally performed host system. CL-CD2231/CD24XX boosts system efficiency with on-chip DMA, on-chip FIFOs, intelligent vectored interrupts, intelligent protocol processing. onchip controller provides `fire-and-forget' transmit support host need only inform CL-CD24XX devices location packet sent. Similarly, receive, CL-CD24XX devices automatically receives complete packet with host intervention assistance. controller also transmit Append mode asynchronous applications. controller uses dual-buffer scheme that easily implements simple complex buffer schemes. Each channel direction active buffers.
(cont.)
COMMON FEATURES
Multi-protocol support: Async, HDLC/SDLC (synchro-
nous data link control)
32-bit address, 16-bit data, double-buffered con-
troller each transmitter receiver; independent bit-rate generators channel transmit receive On-chip (nonreturn zero), NRZI (nonreturn-tozero inverted), Manchester data encoding decoding DPLL (digital phase locked loop) each receiver independent timers channel
BENEFITS
Substantially reduced host overhead resulting
more channels faster overall throughput Reduced time-critical host software, enabling faster easier software development Smallest possible footprint multi-channel device (cont.)
Functional Block Diagram
SERIAL INTERFACE CHANNELS
HOST INTERFACE LOGIC HOST INTERFACE
MODEM RECEIVE/CRC TRANSMIT/CRC TIMER/BRG/DPLL MODEM RECEIVE/CRC TRANSMIT/CRC TIMER/BRG/DPLL
ON-CHIP CONTROLLER INTERFACE LOGIC
FIRMWARE
PROPRIETARY RISC PROCESSOR
August 1996
World Wide Web: http://www.basiscomm.com
CL-CD2231/CD24XX
Multi-Protocol Communications Controllers
COMMON FEATURES (cont.)
HDLC/SDLC
Four 8-bit 16-bit frame address matching generation validation (cyclic redundancy check) optionally readable Programmable leading-pad character transmission Supports shared flags receive frames Programmable number leading flags
Programmable timer closely coupled with character
reception, especially asynchronous receive operation
On-Chip Controller
Master interrupt-selectable channel
direction
Dual-configuration register sets reduce realtime
constraints
Append Block mode Chain/unchain long frames into multiple buffers 32-bit address 16-bit data transfer Programmable buffers following receive
Asynchronous
User-programmable automatic flow control modes
In-band (software) XON/XOFF Out-of-band (hardware flow control) RTS/CTS DTR/DSR Line-break detection generation Special-character character-range recognition transmission Transmit delay
8-bit character plus optional parity Enhanced features UNIX® environment
character exception
Other Features
Improved interrupt schemes
Vectored interrupts channel allow direct jump into proper service routines Good Datainterrupts eliminate need status checks
Easily cascaded multiple-device configurations 16-byte receive transmit FIFOs Local remote maintenance loopback modes Byte-endian-orientation selection that allows easy
Character expansion transmit (for example, sending <LF> expanded <CR> <LF> automatically) Programmable translation receiving character with error different pattern (for example, character with parity error translated into FFh, character system side) Flow-control transparency LNext
interface 80X86 680X0 processors Eight clock/modem control signals channel
addition above common features, each device following unique features/protocols.
CL-CD2231 CL-CD2431 Features
(Point-to-Point Protocol)
Supports data link level RFC-1661 Supports dual async control character maps control
Recognition special characters enabling
Block separation generation validation
Chaining long receive blocks into multiple buffers
characters) RFC-1662
X.21
Full support X.21 protocol Detection steady state conditions Transmission steady state conditions synchronized
Async-HDLC
Compatible with 3309/4335 Addendum Automatic insertion deletion control/escape char-
acters complements Automatic generation detection 16-bit (frame check sequence)
V.42
Apple Talk Remote Access Protocol 1.0/2.0
modem lead Programmable character character detect option Idle line condition Optional strip receive
SLIP
Supports data link level RFC-1055
CL-CD2481 Features
Programmable four-channel device with word
microcode
CL-CD2401 Features
Bisync
Programmable ASCII EBCDIC encoding Support transparent Bisync
Supports Async, HDLC/SDLC, PPP, SLIP, MNP®
Bisync, X.21
Semi-custom support firmware protocols (con-
tact local Basis Communications sales office more information)
CL-CD2231/CD24XX
Multi-Protocol Communications Controllers
CL-CD2231/CD24XX devices programmed interrupt host completion frame buffer. applications where buffers small, fixed size, dual-buffer scheme allows large frames divided into multiple buffers. applications where interface desired, device operated interrupt driven polled device. This choice available individually each channel each direction. example, channel programmed transmit interrupt-driven receive. either case, 16-byte FIFOs each channel each direction reduce latency time requirements, making both software hardware designs less timecritical. Threshold levels FIFOs userprogrammable. Efficient vectored interrupts another CL-CD2231/CD24XX devices help system efficiency. Separate interrupts generated transmit, receive, modem-signal change, with unique userdefined vectors each type channel. This allows very flexible interfacing fast efficient interrupt coding. example, Good Data interrupt allows host vector directly routine that transfers data status error checking required.
CL-CD2231/CD24XX Family Compatibility
Features
Number serial channels Interrupt on-chip mechanism FIFO depth (per channel direction) Data size (bits) ASYNC HDLC/SDLC X.21, Bisync Async-HDLC, (point-to-point protocol) Serial data rate (kbits/second) Number modem leads (per channel, including TxD) On-chip timers UNIX® character processing Special character recognition Package System interface compatibility
CL-CD2231
256/230.4 100-pin PQFP
CL-CD2401
128/134.4b 100-pin PQFP CL-CD24X1
CL-CD2431
128/134.4b 100-pin PQFP CL-CD24X1
CL-CD2481
Downloaded* Downloaded Downloaded Downloaded 128/134.4 Downloaded Downloaded 100-pin PQFP CL-CD24X1
indicates identical operation register setting. Clock frequency required 230.4 kbps (applies CL-CD2231 only). 134.4/230.4 kbps Async modes; 128/256 kbps Sync modes. Clock frequency required 134.4 kbps; this applies Revision (CL-CD2431)/Rev. later (CL-CD2401). Compatibility with pins except those supporting channels other family members. These pins connect' must pulled 4.7-k resistor CL-CD2231 (see CL-CD2231 Data Book more details). NOTE: Device microcode user-programmable; standard microcode supplied Basis Communications.
Evaluation
evaluation contains standard IBM®-compatible PC/AT board, programming examples, software drivers, documentation hardware software installation.
Sales Representatives Distributors
Basis Communications worldwide network sales representatives distributors. most current listing, please visit www.basiscomm.com.
About Company
Basis Communications networking communications semiconductor company providing Service-Specificnetworking platforms Internet. Basis Communications' products include Service-Specific Network ProcessorPlatforms, Service-Specific Controllers PCMCIA Controllers.
Copyright 1999 Basis Communications Corp. rights reserved. Printed
Basis Communications made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Basis Communications this information, infringements patents other rights third parties. This document property Basis Communications implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise). Furthermore, part this publication used basis manufacture sale items without prior written consent Basis Communications. names products Basis Communications other vendors suppliers appearing this document trademarks service marks their respective owners, which registered some jurisdictions.
Basis Communications Corp. www.basiscomm.com
46712 Bayside Parkway, Fremont, 94538 TEL: 510-668-0107 FAX: 510-624-7690

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