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CL-CD1284
Parallel Port (Peripheral-side)
High-speed, bidirectional, multi-protocol parallel port: Hardware implementation modes IEEE (standard) 1284 specification (including automatic negotiation)
Centronics®-compatible mode Reverse Byte mode Reverse Nibble mode (extended capabilities port) mode with run-length encoding/decoding (enhanced parallel port) mode 2-Mbytes/sec. transfer rate modes
IEEE 1284-Compatible Parallel Interface Controller with High-Speed Asynchronous Serial Ports
OVERVIEW
CL-CD1284 multi-function interface controller printers, scanners, tape drives, set-top boxes, data acquisition applications that require highspeed, multi-protocol parallel port asynchronous serial ports. device both programmed operation (parallel port only), which provides flexibility local interface design high-speed data transfers between device main memory. parallel port implements modes IEEE 1284 Standard Signaling Method Bidirectional Parallel Peripheral Interface Personal Computers specification, including EPP, ECP, Reverse Byte, Reverse Nibble, Compatible. Data transfer rates Mbytes/sec. achievable parallel port when device operates with 25-MHz clock. parallel port data control signals implement IEEE 1284-defined Level-2 interface drive type (symmetrical), current capability mA), slew rate (0.4 V/ns), 0.8-V hysteresis (-2.0 +7.0 protection implemented). (cont.)
GENERALPURPOSE PORT
64-byte parallel FIFO with interface
Serial UARTs
Serial channel asynchronous protocol support 115.2 kbps (register-set-compatible functionally identical CL-CD1400)
Twelve-byte FIFOs each transmitter receiver with programmable threshold receive FIFO interrupt generation Improved interrupt schemes: Good Datainterrupts eliminate need character status check User-programmable automatic flow control serial channels Special character recognition generation Special character processing, particularly useful UNIX® environments, optionally handled automatically serial channels modem control signals channel (DTR, DSR, RTS, CTS,
Functional Block Diagram
HANDSHAKE CONTROL LOCAL INTERFACE
COMPRESSION/ DECOMPRESSION DATA MOVER
BYTES
CONTROL STATE MACHINE
LEVEL-2 ELECTRICAL INTERFACE
DATA PIPELINE
FIFO
IEEE 1284 PERIPHERAL PARALLEL PORT SERIAL PORT
REGISTERS FIFO MODIFIED CL-CD1400 CORE
SERIAL PORT
August 1996
World Wide Web: http://www.basiscomm.com
CL-CD1284
IEEE 1284-Compatible Parallel Interface Controller
OVERVIEW (cont.)
serial ports implement standard asynchronous protocol. Functionally, serial ports identical register-set-compatible with CL-CD1400. table below, shows differences between CL-CD1283 CL-CD1284.
Device
CL-CD1283 CL-CD1284
made time required service them. time required service requests reduced four unique vectors that provide internal interrupt conditions. Whether receive, transmit, modem signal change, parallel port, system spends less time determining source interrupt. serial receive interrupt service time further reduced providing types receive vectors: `good' data other `exception' data. does spend time determining status every character. When receive vector signifies good data, removes data from FIFO. Status checking necessary. Exception data (framing error, overrun, break, causes interrupt with vector that immediately identify manage. RISC processor assisted process sending receiving serial data specialized hardware called `bit-engines'. These logic blocks perform task sending receiving individual bits character, thus removing task timing duration from on-device processor. processor assembles bits into characters tests various parameters (for example, parity, framing, then places characters FIFO. Since managing every character, special character processing possible, such looking responding flow-control characters (XON/XOFF), performing UNIX®-style character substitutions range checking. This reduces interrupt overhead automatically performing many operations that normally does. example, flow-control performed without involvement. CL-CD1284 daisy-chained with other CL-CD1284 CL-CD1400 devices implement larger more complex systems. Fair Share feature assures equal access service requests across multiple devices (Fair Share implemented parallel port interrupt request). parallel channel within CL-CD1284 implements protocols defined peripheral side IEEE 1284 standard. This specification defines
Number Serial Channels
Number Parallel Channels
general-purpose port included that provides eight bits individual direction-programmable that used status control external functions.
Theory Operation
CL-CD1284 efficient high-performance communications controller using on-chip RISC processor that off-loads sending receiving data from CPU. Specifically data communications applications, RISC processor employs highperformance architecture developed Basis Communications. This internal executes instructions one-clock cycle, uses windowed architecture ensure zero-overhead context switching each type internal interrupt. processor transparent user does require programming. manages serial data movement between serial channels provides flexible interrupt interface parallel channel. parallel channel, being separate having intelligence own, implements very high-speed, peripheral-side parallel data interface. Each serial channels consist separate 12byte receive transmit FIFOs. parallel channel single 64-byte FIFO support higher speeds obtainable parallel data port. serial receive FIFOs have programmable thresholds minimize interrupt latency requirements. parallel port FIFO programmable threshold receive transmit directions. deep FIFOs reduce both number interrupt requests
CL-CD1284
IEEE 1284-Compatible Parallel Interface Controller
OVERVIEW (cont.)
four bidirectional protocols that allow peripheral device communicate with host system (IBM® equivalent) through parallel printer channel. modes include Reverse Nibble, Reverse Byte (IBM® PS/2® style), ECP, implemented Intel® 80386SL processor). modes operate data rates high Mbytes/sec. IEEE 1284 port implemented functional blocks: data pipeline that includes 64byte FIFO interface; high-speed state-machine that controls parallel port implements slave-side IEEE 1284 protocols. internal RISC processor assists parallel channel providing interrupt generation, acknowledgment functions, data interface Parallel Port registers. defined IEEE 1284 specification, CL-CD1284 mode provides (run-length encoded) data compression both directions. This data compression automatically performed enabled) capable compressing long strings bytes) identical data into two-byte sequence (command/count data). Since common patterns have large amounts identical data, CL-CD1284 greatly reduces data transmission times printer applications. mode defines means sending address data over parallel channel much like processor address data interface. This widespread SCSI interface adapters that provide these services laptop computers. development hardware software, evaluation complete with application notes programmer's guide provided along with software examples evaluation board schematics. add-in card designed demonstrate capabilities CL-CD128X family devices, enable software developers begin testing code while system hardware still development. following figure shows possible configuration CL-CD1284 laser-printer application. this example, CL-CD1284 provides parallel serial data interface host system server. also provides serial channel control communication with printer console, well general-
CL-CD1284 Sample System Block Diagram
ADDRESS CONTROL PROCESSOR DATA
GENERAL-PURPOSE I/O: INTERNAL STATUS CONTROL
IEEE 1284 PARALLEL CHANNEL
CL-CD1284
HIGH-SPEED SERIAL CHANNEL (RS-232, INFRARED) HIGH-SPEED SERIAL CHANNEL LASER PRINTER CONSOLE
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About Company
Basis Communications networking communications semiconductor company providing Service-Specificnetworking platforms Internet. Basis Communications' products include Service-Specific Network ProcessorPlatforms, Service-Specific Controllers PCMCIA Controllers.
Copyright 1999 Basis Communications Corp. rights reserved. Printed
Basis Communications made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Basis Communications this information, infringements patents other rights third parties. This document property Basis Communications implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise). Furthermore, part this publication used basis manufacture sale items without prior written consent Basis Communications. names products Basis Communications other vendors suppliers appearing this document trademarks service marks their respective owners, which registered some jurisdictions.
Basis Communications Corp. www.basiscomm.com
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