Parallel Port (Peripheral-side) High-speed, bidirectional, multi-

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CL-CD1283
Parallel Port (Peripheral-side)
High-speed, bidirectional, multi-protocol parallel port: Hardware implementation modes IEEE (standard) 1284 specification (including automatic negotiation)
Centronics®-compatible mode Reverse Byte mode Reverse Nibble mode (extended capabilities port) mode with runlength encoding/decoding (enhanced parallel port) mode 2-Mbytes/sec. transfer rate modes 64-byte FIFO accommodate Kbytes compressed data with (run-length encoded) compression enabled
IEEE 1284-Compatible Parallel Interface Controller
OVERVIEW
CL-CD1283 multi-function interface controller printers, scanners, tape-drives, set-top boxes, data acquisition, other applications that require high-speed, bidirectional, parallel communication with host computer. modes IEEE 1284 Standard Signaling Method Bidirectional Parallel Peripheral Interface Personal Computers specification supported, including ECP, EPP, Reverse Byte, Reverse Nibble, Compatible. With full support this standard, CL-CD1283 provides compatibility with types host parallel ports, including older Centronics IBM® PS/2® bidirectional, latest IEEE 1284-compliant ports. dedicated state-machine design provides fastest possible response times host signal changes, with 100% guaranteed compliance IEEE 1284 timing, protocol, signaling
(cont.)
64-byte parallel FIFO with interface
Supports peripheral-side operation Data control input/output pads support IEEE 1284 level-2 interface specification interface
High-speed slave handshake interface Three clocks word transfers (cont.)
Functional Block Diagram
GENERAL-PURPOSE PORT
HANDSHAKE LOGIC
COMPRESSION/ DECOMPRESSION LOGIC BYTES DATA MOVER LOGIC FIFO CONTROL STATE MACHINE LEVEL-2 ELECTRICAL INTERFACE
INTERRUPT LOGIC
HOST INTERFACE
DATA PIPELINE
IEEE 1284 PERIPHERAL PARALLEL PORT
August 1996
World Wide Web: http://www.basiscomm.com
CL-CD1283
IEEE 1284-Compatible Parallel Interface Controller
FEATURES (cont.)
On-the-fly data compression using encoding decoding 8/16-bit data interface BYTESWAP input provides easy interface both big- little-endian systems Vectored interrupts simplify interrupt service routines
General
System clock CMOS technology enables high speed power Available 100-pin PQFP package
OVERVIEW (cont.)
requirements. CL-CD1283 device, operating MHz, signal response times support 2Mbytes/sec. transfers, provided that comparably fast host parallel port used. This performance headroom guarantees that faster data rates future host parallel port implementations will suppor peripheral applications using CL-CD1283. addition dedicated state machine, CL-CD1283 provides slave support, 64-byte FIFO allow maximum total throughput performance. Interrupts generated based status changes parallel port. Note, however that interrupts generated FIFO threshold FIFO full/empty conditions. request signal used generate interrupts long hardware software implementation handled correctly. maximum performance requirement, device monitored controlled polling detailed status registers. Another unique feature CL-CD128X family devices dedicated hardware compression/decompression mode. Special compression/decompression `on-the-fly' while data moved from FIFO. these capabilities above beyond requirements IEEE 1284 specification permit less expensive microprocessor reducing required bandwidth needed parallel port. development hardware software, evaluation complete with application notes programmer's guide provided along with software examples evaluation board schematics. add-in card designed demonstrate capabilities CL-CD128X family devices, enable software developers begin testing code while system hardware still development.
CL-CD1283
IEEE 1284-Compatible Parallel Interface Controller
ADVANTAGES
Unique Features
Supports IEEE 1284 specification
Benefits
Multi-protocol bidirectional port wide range applications. 2-Mbytes/sec. transfer rate Provides future connectivity with host systems
Hardware support IEEE 1284 timings 64-byte FIFO Parallel port signals provide level-2 drive characteristics channel compression/decompression hardware
Reduces software complexity guarantees specification compliance. High throughput with reduced load host CPU. Direct connection printer cable; reduces chip count. Reduces host interface overhead. High-speed data movement between memory parallel port. Reduces software complexity increases throughput compressed-data transfers.
Functional Block Diagram
PIPEPARALLEL PORT FIFO PARALLEL PORT LOGIC
PIPELINE CONTROL CONTROL STATE MACHINE INTERFACE LOGIC INTERRUPT LOGIC
REGISTERS
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About Company
Basis Communications networking communications semiconductor company providing Service-Specificnetworking platforms Internet. Basis Communications' products include Service-Specific Network ProcessorPlatforms, Service-Specific Controllers PCMCIA Controllers.
Copyright 1999 Basis Communications Corp. rights reserved. Printed
Basis Communications made best efforts ensure that information contained this document accurate reliable. However, information subject change without notice provided without warranty kind (express implied). responsibility assumed Basis Communications this information, infringements patents other rights third parties. This document property Basis Communications implies license under patents, copyrights, trademarks, trade secrets. part this publication copied, reproduced, stored retrieval system, transmitted, form means (electronic, mechanical, photographic, otherwise). Furthermore, part this publication used basis manufacture sale items without prior written consent Basis Communications. names products Basis Communications other vendors suppliers appearing this document trademarks service marks their respective owners, which registered some jurisdictions.
Basis Communications Corp. www.basiscomm.com
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