Organization 32768 Bits MIL-STD-883 Class High-Reliability Processing

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Organization 32768 Bits MIL-STD-883 Class High-Reliability Processing

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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
Organization 32768 Bits MIL-STD-883 Class High-Reliability Processing Single Power Supply Pin-Compatible With Existing 256K ROMs EPROMs Inputs Outputs Fully Compatible Access Cycle Times '27C256-15 '27C256-17 '27C256-20 '27C256-25 '27C256-30 Power-Saving CMOS Technology Very High-Speed SNAP! Pulse Programming 3-State Output Buffers 400-mV Minimum Noise Immunity With Standard Loads Latchup Immunity Input Output Lines Power Dissipation (CMOS Input Levels) Active Worst Case Standby Worst Case Military Operating Temperature Range 55°C 125°C
PACKAGE VIEW
NOMENCLATURE Address Inputs Inputs (programming) Outputs Chip Enable/Power Down Output Enable Ground Power Supply 13-V Programming Power Supply
description
SMJ27C256 series 144-bit, ultraviolet-light erasable, electrically programmable read-only memories. These devices fabricated using power-saving CMOS technology high speed simple interface with bipolar circuits. inputs (including program data inputs) driven Series circuits without external pullup resistors. Each output drive Series circuit without external resistors. data outputs 3-state connecting multiple devices common bus. SMJ27C256 pin-compatible with 28-pin 256K ROMs EPROMs. offered 600-mil dual-in-line ceramic package suffix) rated operation from 55°C 125°C. Because this EPROM operates from single supply read mode), ideal microprocessor-based systems. other supply needed programming. programming signals level. This device programmable SNAP! Pulse programming algorithm. SNAP! Pulse programming algorithm uses nominal programming time four seconds. programming outside system, existing EPROM programmers used. Locations programmed singly, blocks, random.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
operation
seven modes operation SMJ27C256 listed Table read mode requires single supply. inputs level except during programming SNAP! Pulse) signature mode.
operation (continued)
Table Operation Modes
FUNCTION (PINS) (20) (22) (28) (24) (10) VIH. MODE READ OUTPUT DISABLE STANDBY PROGRAMMING VERIFY PROGRAM INHIBIT CODE Data Hi-Z Hi-Z Data Data Hi-Z DEVICE SIGNATURE MODE
read/output disable When outputs more SMJ27C256s connected parallel same bus, output particular device circuit read with interference from competing outputs other devices. read output selected SMJ27C256, low-level signal applied other devices circuit should have their outputs disabled applying high-level signal these pins. Output data accessed pins through DQ7. latchup immunity Latchup immunity SMJ27C256 minimum inputs outputs. This feature provides latchup immunity beyond potential transients printed-circuit-board level when EPROM interfaced industry-standard logic devices. Input output layout approach controls latchup without compromising performance packing density. powerdown Active supply current reduced from (SMJ27C256-15 through SMJ27C256-25) TTL-level inputs) (CMOS-level inputs) applying high CMOS signal pin. this mode, outputs high-impedance state. erasure Before programming, SMJ27C256 erased exposing chip through transparent high-intensity ultraviolet (UV) light (wavelength 2537 EPROM erasure before programming necessary ensure that bits logic-high state. Logic lows programmed into desired locations. programmed logic-low erased only ultraviolet light. recommended minimum exposure dose intensity exposure time) cm2. typical 12-mW cm2, filterless lamp erases device
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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
minutes. lamp should located about above chip during erasure. After erasure, bits high state. should noted that normal ambient light contains correct wavelength erasure; therefore, when using SMJ27C256, window should covered with opaque label. SNAP! Pulse programming SMJ27C256 EPROM programmed using SNAP! Pulse programming algorithm illustrated flowchart Figure This algorithm programs device nominal time seconds. Actual programming time varies function programmer used. Data presented parallel (eight bits) pins DQ7. Once addresses data stable, pulsed. SNAP! Pulse programming algorithm uses initial pulses microseconds (µs) followed byte-verification step determine when addressed byte been successfully programmed. 100-µs pulses byte provided before failure recognized. programming mode achieved when VIH, VIL. More than device programmed when devices connected parallel. Locations programmed order. When SNAP! Pulse programming routine completed, bits verified with program inhibit Programming inhibited maintaining high-level input program verify Programmed bits verified with when VIH. signature mode signature mode provides access binary code identifying manufacturer device type. This mode activated when forced identifier bytes accessed (terminal 10); i.e., accesses manufacturer code, which output DQ7; accesses device code, which also output DQ7. other addresses must held VIL. Each byte contains parity DQ7. manufacturer code these devices device code 04h.
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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
signature mode (continued)
Start
Address First Location Program Pulse Increment Address Program Mode
Last Address?
Address First Location Program Pulse tw(E)PR
Increment Address
Verify Byte
Fail X=X+1 Interactive Mode
Pass
Last Address?
Device Failed
Compare Bytes Original Data
Fail
Final Verification
Pass Device Passed
Figure SNAP! Pulse Programming Flowchart
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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
logic symbol
EPROM
[PWR DWN]
This symbol accordance with ANSI IEEE 91-1984 Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Supply voltage range, (see Note Input voltage range (see Note inputs except 13.5 Output voltage range (see Note Minimum operating free-air temperature, 55°C Maximum operating case temperature, 125°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect GND.
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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
recommended operating conditions
PARAMETER Supply voltage Supply voltage Read mode (see Note SNAP! Pulse programming algorithm Read mode (see Note SNAP! Pulse programming algorithm inputs CMOS inputs inputs CMOS inputs 12.75 11.5 6.25 6.75 13.25 UNIT
High-level High level input voltage Low-level level input voltage Voltage level signature mode Operating free-air temperature
Operating case temperature NOTES: must applied before same time removed after same time device must inserted into removed from board while applied. connected directly (except program mode). supply current this case would ICC2 IPP1
electrical characteristics over recommended ranges supply voltage operating free-air temperature
PARAMETER IPP1 IPP2 ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) supply current supply current (during program pulse) supply curent (standby) TTL-input level CMOS-input level '27C256 '27C256 '27C256 '27C256 TEST CONDITIONS UNIT
ICC2
supply current (active)
VIL, tcycle minimum, Outputs open
Output short-circuit current Typical values 25°C nominal voltages. This parameter been characterized 25°C tested.
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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
capacitance over recommended temperature,
PARAMETER Input capacitance
ranges
supply
voltage
operating
free-air
UNIT
TEST CONDITIONS
Output capacitance Capacitance measurements made sample basis only. Typical values 25°C nominal voltages.
switching characteristics over recommended ranges supply voltage operating free-air temperature (see Notes
PARAMETER ta(A) ta(E) ten(G)R tdis tv(A) Access time from address Access time from Output-enable time from Disable time output from whichever occurs first Output data valid time after change address, whichever occurs first 27C256 Figure Figure TEST CONDITIONS (SEE NOTES '27C256 '27C256 UNIT
PARAMETER ta(A) ta(E) ten(G)R tdis tv(A) Access time from address Access time from Output-enable time from Disable time output from whichever occurs first Output data valid time after change address, whichever occurs first
TEST CONDITIONS (SEE NOTES
27C256
'27C256
UNIT
Value calculated from delta measured output level. This parameter only sampled 100% tested. NOTES: Timing measurements made logic high logic (see Figure Common test conditions apply tdis except during programming.
switching characteristics programming: (SNAP! Pulse), 25°C
PARAMETER tdis(G) ten(G)W Output-disable time from Output-enable time from UNIT
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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
recommended timing requirements programming: (SNAP! Pulse), 25°C (see Figure
th(A) th(D) tw(E)PR tsu(A) tsu(G) tsu(E) tsu(D) tsu(VPP) tsu(VCC) Hold time, address Hold time, data Pulse duration, initial program Setup time, address Setup time, Setup time, Setup time, data Setup time, Setup time, UNIT
PARAMETER MEASUREMENT INFORMATION
2.08
Output Under Test (see Note
NOTES: includes probe texture capacitance testing inputs driven logic high logic low. Timing measurements made logic high logic both inputs outputs.
Figure Load Circuit Voltage Waveforms
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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
Addresses Valid
ta(A)
ta(E) tdis ten(G)R tv(A) Output Valid
Figure Read-Cycle Timing
Verify Program tsu(A) Data Stable tsu(D) Hi-Z Address Stable th(A) Data Valid tdis(G) Address
tsu(VPP)
tsu(VCC) tsu(E) th(D)
tsu(G) ten(G)W
tw(E)PR
Figure Program-Cycle Timing (SNAP! Pulse Programming)
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SMJ27C256 32768 8-BIT UV-ERASABLE PROGRAMMABLE READ-ONLY MEMORY
MECHANICAL DATA
(R-CDIP-T**)
SHOWN
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
0.065 (1,65) 0.045 (1,14) 0.090 (2,29) 0.060 (1,53)
Lens Protrusion 0.010 (0,25) 0.175 (4,45) 0.140 (3,56)
0.018 (0,46)
Seating Plane 0.125 (3,18) 0.100 (2,54) 0.022 (0,56) 0.014 (0,36) 0.012 (0,30) 0.008 (0,20)
PINS** NARR
WIDE NARR 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.265(32,13) 1.265(32,13) 1.235(31,37) 1.235(31,37) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50)
WIDE NARR 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.465(37,21) 1.465(37,21) 1.435(36,45) 1.435(36,45) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50)
WIDE NARR 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 1.668(42,37) 1.668(42,37) 1.632(41,45) 1.632(41,45) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50)
WIDE 0.624(15,85) 0.624(15,85) 0.590(14,99) 0.590(14,99) 2.068(52,53) 2.068(52,53) 2.032(51,61) 2.032(51,61) 0.541(13,74) 0.598(15,19) 0.514(13,06) 0.571(14,50) 4040084 10/94
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with ceramic using glass frit. Index point provided terminal identification only press ceramic glass frit seal only
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IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

Organization 32768 Bits MIL-STD-883 Class High-Reliability Processing

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