Organization Bits Single Power Supply Industry Standard 32-Pin Dual-In

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Organization Bits Single Power Supply Industry Standard 32-Pin Dual-In

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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
Organization Bits Single Power Supply Industry Standard 32-Pin Dual-In-line Package Inputs Outputs Fully Compatible Static Operation Clocks, Refresh) Access Cycle Time '27C040-10 '27C040-12 '27C040-15 8-Bit Output Microprocessor-Based Systems Power-Saving CMOS Technology 3-State Output Buffers 400-mV Assured Noise Immunity With Standard Loads Latchup Immunity Input Output Pins Pullup Resistors Required Power Dissipation (VCC Active Worst Case Standby 0.55 Worst Case (CMOS-Input Levels) Military Operating Temperature Range 55°C 125°C
PACKAGE VIEW
NOMENCLATURE Address Inputs Inputs (programming) Outputs Chip Enable Output Enable Ground Supply 13-V Power Supply
description
Only program mode
SMJ27C040 304-bit, ultraviolet-light erasable, electrically programmable read-only memories (EPROMs). These devices fabricated using CMOS technology high speed simple interface with bipolar circuits. inputs (including program data inputs) driven Series circuits. Each output drive Series circuit without external resistors. data outputs 3-state connecting multiple devices common bus. SMJ27C040 offered 32-pin 600-mil dual-in-line ceramic package suffix) rated operation from 55°C 125°C. Since this EPROM operates from single supply read mode), ideal microprocessor-based systems. other (13-V) supply needed programming. programming signals level. programming outside system, existing EPROM programmers used.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
logic symbol
EPROM
[PWR DWN]
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown package.
operation
seven modes operation listed Table read mode requires single supply. inputs level except during programming signature mode. Table Operation Modes
FUNCTION Read Output Disable Standby Programming Program Inhibit Verify Signature Mode DQ0-DQ7 Data Hi-Z Hi-Z Data Hi-Z Data Code Device Code
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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
read/ output disable When outputs more SMJ27C040s connected parallel same bus, output particular device circuit read with interference from competing outputs other devices. read output single device, level signal applied pins. other devices circuit should have their outputs disabled applying high level signal these pins. Output data accessed pins latchup immunity Latchup immunity SMJ27C040 minimum inputs outputs. This feature provides latchup immunity beyond potential transients P.C. board level when EPROM interfaced industry standard logic devices. input output layout approach controls latchup without compromising performance packing density. more information application report SMLA001, "Design Considerations; Latchup Immunity HVCMOS EPROM Family", available through Sales Offices. power down Active supply current reduced from high input high CMOS input this mode outputs high-impedance state. erasure Before programming, SMJ27C040 EPROM erased exposing chip through transparent high intensity ultraviolet-light (wavelength 2537 recommended minimum exposure dose intensity exposure time) 15-Ws/cm2. typical 12-mW/cm2, filterless lamp erases device minutes. lamp should located about above chip during erasure. After erasure, bits high state. should noted that normal ambient light contains correct wavelength erasure. Therefore, when using SMJ27C040, window should covered with opaque label. After erasure (all bits logic high state), logic lows programmed into desired locations. programmed erased only ultraviolet light. SNAP! Pulse programming SMJ27C040 TMS27PC040 programmed using SNAP! Pulse programming algorithm. programming sequence shown SNAP! Pulse programming flow chart (Figure initial setup VIH, VIH. Once initial location selected, data presented parallel (eight bits) pins through DQ8. Once addresses data stable, programming mode achieved when pulsed (VIL) with pulse duration tw(PGM). Every location programmed only once before going interactive mode. interactive mode, word verified VIH, VIL. correct data read, programming performed pulling high, then with pulse duration tw(PGM). This sequence verification programming performed maximum times. When device fully programmed, bytes verified with 10%. program inhibit Programming inhibited maintaining high level inputs pins.
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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
program verify Programmed bits verified with when VIL, VIH. signature mode provides access binary code identifying manufacturer type. This mode activated when (pin forced identifier bytes accessed toggling other addresses must held low. signature code SMJ27C040 9750. selects manufacturer's code (Hex), high selects device code (Hex), shown Table Table Signature Modes
IDENTIFIER MANUFACTURER CODE DEVICE CODE PINS
VIL, VIL, VIL, VCC.
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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
Start
Address First Location 0.25 0.25 Program Pulse Increment Address Program Mode
Last Address?
Address First Location Program Pulse
Increment Address
Verify Byte
Fail X=X+1 Interactive Mode
Pass
Last Address?
Device Failed
Compare Bytes Original Data
Fail
Final Verification
Pass Device Passed
Figure SNAP! Pulse Programming Flow Chart
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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Supply voltage range, (see Note Input voltage range (see Note inputs except Output voltage range, with respect (see Note Minimum operating free-air temperature 55°C Maximum operating case temperature 125°C Storage temperature range 65°C 125°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect GND.
recommended operating conditions
Supply voltage Supply voltage High-level High level input voltage Low-level level input voltage Operating free-air temperature Operating case temperature Read mode (see Note SNAP! Pulse programming algorithm Read mode (see Note SNAP! Pulse programming algorithm CMOS CMOS 6.25 12.75 6.75 13.25 VCC+0.5 VCC+0.5 UNIT
NOTES: must applied before same time removed after same time VPP. device must inserted into removed from board when applied. connected directly (except program mode). supply current this case would IPP. During programming, must maintained 0.25
electrical characteristics over recommended ranges supply voltage operating free-air temperature
PARAMETER IPP1 IPP2 ICC1 High-level output voltage Low-level output voltage Input current (leakage) Output current (leakage) supply current supply current (during program pulse) (see Note supply current (standby) TTL-Input level CMOS-Input level TEST CONDITIONS 12.75 25°C VIL, tcycle minimum cycle time, outputs open (see Note UNIT
ICC2
supply current (active)
NOTES: This parameter only sampled 100% tested. Minimum cycle time maximum access time.
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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
capacitance over recommended ranges supply voltage operating free-air temperature, (VCC
PARAMETER Input capacitance Output capacitance Capacitance sampled only initial design after major change. typical values 25°C nominal voltages. TEST CONDITIONS UNIT
switching characteristics over recommended ranges supply voltage operating free-air temperature (see Notes
PARAMETER TEST CONDITIONS (SEE NOTE '27C040-10 (see Figure Input Input '27C040-12 '27C040-15 UNIT
ta(A) ta(E) ten(G) tdis tv(A)
Access time from address Access time from chip enable Output enable time from Output disable time from whichever occurs first (see Note Output data valid time after change address, whichever occurs first (see Note
NOTES: switching characteristics input pulse levels Timing measurements made logic high logic low. (Figure Common test conditions apply tdis except during programming. Value calculated from 0.5-V delta measured output level. This parameter only sampled 100% tested.
switching characteristics programming: (SNAP! Pulse), 25°C
PARAMETER tdis(G) ten(G) Output disable time from Output enable time from UNIT
timing requirements programming
th(A) th(D) tw(PGM) tsu(A) tsu(E) tsu(G) tsu(D) tsu(VPP) tsu(VCC) Hold time, address Hold time, data Pulse duration, program Setup time, address Setup time, Setup time, Setup time, data Setup time, Setup time, SNAP! Pulse programming algorithm UNIT
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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08 Output Under Test (see Note NOTE includes probe fixture capacitance.
Figure Output Load Circuit Input/Output Wave Forms
Addresses Valid ta(A)
ta(E) tdis ten(G) Hi-Z tv(A) Output Valid Hi-Z
Figure Read-Cycle Timing
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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
Verify Program tsu(A) Data Stable tsu(D) tsu(VPP) Hi-Z ten(G) Data Stable tdis(G) Address Stable th(A)
tsu(E) th(D) tsu(VCC)
tsu(G) tw(PGM) 13-V 6.5-V SNAP! Pulse programming.
Figure Program-Cycle Timing (SNAP! Pulse Programming)
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SMJ27C040 524288 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
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IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

Organization Bits Single Power Supply Industry Standard 32-Pin Dual-In

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