Organization Bits Single Power Supply Operationally Compatible With Ex
|
|
|
Top Searches for this datasheet
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
Organization Bits Single Power Supply Operationally Compatible With Existing Megabit EPROMs Industry Standard 32-Pin Ceramic Dual-In-line Package Suffix) Inputs Outputs Fully TTL-Compatible Maximum Access Minimum Cycle Time '27C010A-12 '27C010A-15 '27C010A-20 8-Bit Output Microprocessor-Based Systems Very High-Speed SNAP! Pulse Programming Power-Saving CMOS Technology 3-State Output Buffers 400-mV Minimum Noise Immunity With Standard Loads Latchup Immunity Input Output Pins Pullup Resistors Required Power Dissipation (VCC Active Worst Case Standby 0.55 Worst Case (CMOS-Input Levels)
PACKAGE VIEW
NOMENCLATURE Address Inputs Inputs (programming)/ Outputs Chip Enable Output Enable Ground Internal Connection Program Power Supply 13-V Power Supply
description
Only program mode
SMJ27C010A series 8-bit 576-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs). These devices fabricated using power-saving CMOS technology high speed simple interface with bipolar circuits. inputs including program data inputs) driven Series circuits without external pullup resistors. Each output drive Series circuit without external resistors. SMJ27C010A EPROM offered ceramic dual-in-line package suffix) designed insertion mounting-hole rows 15,2-mm (600-mil) centers. These EPROMs operate from single supply read mode), therefore, ideal microprocessor-based systems. other 13-V supply needed programming. programming signals level. These devices programmable using SNAP! Pulse programming algorithm. SNAP! Pulse programming algorithm uses nominal programming time thirteen seconds. programming outside system, existing EPROM programmers used. Locations programmed singly, blocks, random.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
operation
seven modes operation listed Table read mode requires single supply. inputs level except during programming SNAP! Pulse), signature mode. Table Modes Operation
MODE FUNCTION READ Data OUTPUT DISABLE Hi-Z STANDBY Hi-Z PROGRAMMING Data VERIFY Data PROGRAM INHIBIT Hi-Z CODE VIH. DEVICE SIGNATURE MODE
read/ output disable When outputs more SMJ27C010As connected parallel same bus, output particular device circuit read with interference from competing outputs other devices. read output single device, low-level signal applied pins. other devices circuit should have their outputs disabled applying high-level signal these pins. latchup immunity Latchup immunity SMJ27C010A minimum inputs outputs. This feature provides latchup immunity beyond potential transients printed circuit board level when devices interfaced industry-standard logic devices. input output layout approach controls latchup without compromising performance packing density. power down Active supply current reduced from applying high input applying high CMOS input this mode outputs high-impedance state. erasure Before programming, SMJ27C010A EPROM erased exposing chip through transparent high-intensity ultraviolet light (wavelength recommended minimum exposure dose intensity exposure time) cm2. typical 12-mW cm2, filterless lamp erases device minutes. lamp should located about above chip during erasure. After erasure, bits high state. should noted that normal ambient light contains correct wavelength erasure; therefore, when using SMJ27C010A, window should covered with opaque label. After erasure (all bits logic-high state), logic lows programmed into desired locations. programmed erased only ultraviolet light.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
SNAP! Pulse programming SMJ27C010A programmed using SNAP! Pulse programming algorithm illustrated flowchart Figure This algorithm programs nominal time thirteen seconds. Actual programming time varies function programmer used. SNAP! Pulse programming algorithm uses initial pulse microseconds (µs) followed byte verification determine when addressed byte been successfully programmed. 100-µs pulses byte provided before failure recognized. programming mode achieved when VIL, VIH. Data presented parallel (eight bits) pins through DQ7. Once addresses data stable, pulsed low. More than device programmed when devices connected parallel. Locations programmed order. When SNAP! Pulse programming routine complete, bits verified with 10%. program inhibit Programming inhibited maintaining high-level input pin. program verify Programmed bits verified with when VIL, VIL, VIH.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
Start
Address First Location 0.25 0.25 Program Pulse Increment Address Program Mode
Last Address?
Address First Location Program Pulse
Increment Address
Verify Byte
Fail X=X+1 Interactive Mode
Pass
Last Address?
Device Failed
Compare Bytes Original Data Pass Device Passed
Fail
Final Verification
Figure SNAP! Pulse Programming Flow Chart
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
signature mode signature mode provides access binary code identifying manufacturer type. This mode activated when (pin forced identifier bytes accessed toggling addresses must held low. signature code these devices 97D6. selects manufacturer's code Hex), high selects device code (Hex), shown Table Table Signature Mode
IDENTIFIER MANUFACTURER CODE PINS
DEVICE CODE VIL, VIL, VIL,
logic symbol
EPROM
[PWR DOWN]
This symbol accordance with ANSI IEEE 91-1984 Publication 617-12. package illustrated.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Supply voltage range, Input voltage range, inputs except 13.5 Output voltage range, with respect (see Note Operating free-air temperature range, 55°C 125°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect GND.
recommended operating conditions
'27C010A-12 '27C010A-15 '27C010A-20 Supply voltage Supply voltage Read mode (see Note SNAP! Pulse programming algorithm Read mode (see Note SNAP! Pulse programming algorithm CMOS CMOS 6.25 12.75 6.75 13.25 UNIT
High-level High level input voltage Low-level level input voltage
Operating free-air temperature NOTES: must applied before same time removed after same time device must inserted into removed from board when applied. During programming, must maintained 0.25
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
electrical characteristics over recommended ranges supply voltage operating free-air temperature
PARAMETER IPP1 IPP2 ICC1 High-level High level output voltage Low-level level output voltage Input current (leakage) Output current (leakage) supply current supply current (during program pulse) supply current (standby) TTL-input level CMOS-input level TEST CONDITIONS UNIT
ICC2
supply current (active) (output open)
tcycle minimum cycle time, outputs open
Minimum cycle time maximum access time
capacitance over recommended ranges supply voltage operating free-air temperature,
PARAMETER Input capacitance Output capacitance Capacitance measurements made sample basis only. typical values 25°C nominal voltages. TEST CONDITIONS UNIT
switching characteristics over recommended ranges operating conditions (see Notes
PARAMETER ta(A) ta(E) ten(G) tdis tv(A) Access time from address Access time from chip enable Output enable time from Output disable time from whichever occurs Output data valid time after change address, whichever occurs Series load, Input Input TEST CONDITIONS '27C010A-12 '27C010A-15 '27C010A-20 UNIT
Value calculated from 0.5-V delta measured output level. NOTES: switching characteristics, input pulse levels Timing measurements made logic high logic (reference testing waveform). Common test conditions apply tdis except during programming.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
switching characteristics programming: (SNAP! Pulse), 25°C (see Note
PARAMETER tdis(G) ten(G) Disable time, output disable time from Enable time, output enable time from UNIT
NOTE switching characteristics, input pulse levels Timing measurements made logic high logic (reference testing waveform).
timing requirements programming
tw(PGM) tsu(A) tsu(E) tsu(G) tsu(D) tsu(VPP) tsu(VCC) th(A) th(D) Pulse duration, program Setup time, address Setup time, Setup time, Setup time, data Setup time, Setup time, Hold time, address Hold time, data SNAP! Pulse programming algorithm UNIT
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PARAMETER MEASUREMENT INFORMATION
2.08
Output Under Test (see Note
NOTE includes probe fixture capacitance.
testing input/output waveforms
testing inputs driven logic high logic low. Timing measurements made logic high logic both inputs outputs. Figure Test Output Load Circuit
ta(A) ta(E) ten(G) Hi-Z tdis tv(A) Output Valid Hi-Z Address Valid
Figure Read-Cycle Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ27C010A 131072 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORY
PROGRAMMING INFORMATION
Verify Program tsu(A) Data-In Stable tsu(D) tsu(VPP) tsu(VCC) tsu(E) tsu(G) tw(PGM) tdis(G) ten(G) characteristics device must accommodated programmer. 13-V 6.5-V SNAP! Pulse programming. ten(G) th(D) Address Stable th(A) Data-Out Valid tdis(G) Address
Figure Program-Cycle Timing (SNAP! Pulse Programming)
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Other recent searches
XZMDKVG57W - XZMDKVG57W XZMDKVG57W Datasheet
SMR1D - SMR1D SMR1D Datasheet
SMR3D - SMR3D SMR3D Datasheet
SH7709S - SH7709S SH7709S Datasheet
SH7729R - SH7729R SH7729R Datasheet
SH7706 - SH7706 SH7706 Datasheet
SH7727 - SH7727 SH7727 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
