Organization 8-Bit Flash Memory Compatible With Existing 1M-bit EPROMs

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Organization 8-Bit Flash Memory Compatible With Existing 1M-bit EPROMs

Datasheet Thumbnail

Top Searches for this datasheet

SMJ28F010B 131072 8-BIT FLASH MEMORY
Organization 8-Bit Flash Memory Compatible With Existing 1M-bit EPROMs High-Reliability MIL-PRF-38535 Processing Tolerance ±10% Inputs Outputs Compatible Maximum Access Minimum Cycle Time 28F010B-12 '28F010B-15 '28F010B-20 Industry-Standard Programming Algorithm Program Erase-Cycle Latchup Immunity Input Output Lines Power Dissipation -Active Write -Active Read -Electrical Erase 82.5 -Standby 0.55 (CMOS-Input Levels) Military Temperature Range 55°C 125°C
PACKAGE VIEW
NOMENCLATURE Address Inputs Inputs (programming) Outputs Chip Enable Output Enable Internal Connection Power Supply 12-V Power Supply Ground Write Enable
description
SMJ28F010B 576-bit, programmable read-only memory that electrically bulk-erased reprogrammed. available program erase-endurance-cycle version. SMJ28F010B flash memory offered 32-lead ceramic 600-mil side-braze dual in-line package (DIP) (JDD suffix) leadless ceramic chip carrier suffix).
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 1998, Texas Instruments Incorporated
products compliant MIL-PRF-38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
device symbol nomenclature
SMJ28F010B
Temperature Range Designator 55°C 125°C
Package Designator Ceramic Side-Braze Dual- In-Line Package
Speed Designator
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
logic symbol
FLASH MEMORY
[PWR DWN] (READ) (WRITE)
This symbol accordance with ANSI IEEE 91-1984 Publication 617-12. numbers shown package.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
functional block diagram
State Control Array Program Erase Stop Timer Program-Voltage Switch Chip-Enable Output-Enable Logic Data Latch Erase-Voltage Switch Input Output Buffers
Command Register
Column Decoder Column Gating
Decoder
576-Bit Array Matrix
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
operation
Table lists modes operation device. Table Operation Modes
FUNCTION MODE Read Output Disable Read Standby Write Inhibit Algorithm-Selection Mode Read Read Write Output Disable Standby Write Inhibit Write VPPL VPPL VPPL VPPL VPPH VPPH VPPH VPPH (22) (24) (12) (26) (31) Data Hi-Z Hi-Z Manufacturer-Equivalent Code Device-Equivalent Code Data Hi-Z Hi-Z Data
VIH. VPPL VPPH programming voltage specified device. more details, recommended operating conditions.
read/ output disable When outputs more SMJ28F010B devices connected parallel same bus, output particular device circuit read with interference from competing outputs other devices. Reading output SMJ28F010B enabled when low-level signal applied pins. other devices circuit must have their outputs disabled applying high-level signal these pins. standby write inhibit Active current reduced from applying high level with high CMOS level this mode, outputs high-impedance state. SMJ28F010B draws active current when deselected during programming, erasure, program erase verification. continues draw active current until operation terminated. algorithm-selection mode algorithm-selection mode provides access binary code identifying correct programming erase algorithms. This mode activated when forced VID. identifier bytes accessed toggling other addresses must held low. selects manufacturer-equivalent code 89h, high selects device-equivalent code B4h, shown Table Table Algorithm-Selection Modes
Manufacturer-Equivalent Code PINS
Device-Equivalent Code =VIL, VIL, VIL, VID, VIL, VPPL.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
programming erasure erased state, bits logic Before erasing device, memory bits must programmed logic Then entire chip erased. this point, bits, which logic programmed accordingly. fast-write fast-erase algorithms further details. command register command register controls program erase functions SMJ28F010B. algorithm-selection mode activated using command register addition previously described method. When high, contents command register function being performed changed. command register written when pulsed low. address latched leading edge pulse, while data latched trailing edge. Accidental programming erasure minimized because commands must executed invoke either operation. command register inhibited when below erase write lockout voltage, VLKO power-supply considerations Each device must have 0.1-µF ceramic capacitor connected between suppress circuit noise. Changes current drain require have bypass capacitor well. Printed-circuit traces both power supplies should appropriate handle current demand.
command definitions
commands include read, algorithm-selection mode, set-up-erase, erase, erase-verify, set-up-program, program, program-verify, reset. Table lists command definitions with required cycles. Table Command Definitions
COMMAND Read Algorithm-Selection Mode Set-Up-Erase Erase Erase-Verify Set-Up-Program Program Program-Verify Reset REQUIRED CYCLES FIRST CYCLE OPERATION Write Write Write Write Write Write Write ADDRESS DATA SECOND CYCLE OPERATION Read Read Write Read Write Read Write ADDRESS 0000h 0001h DATA
Legend: Address memory location read during erase verify Address memory location read Address memory location programmed. Address latched falling edge Data read from location during read operation Data read from location during erase verify Data programmed location Data latched rising edge Data read from location during program verify Modes operation defined Table
read command Memory contents accessed while high low. When high, writing into command register invokes read operation. When device powered default contents command register read operation enabled. read operation remains enabled until different command written command register.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
algorithm-selection mode command algorithm-selection mode activated writing into command register. device-equivalent code B4h) identified value read from address location 0001h, manufacturer-equivalent code 89h) identified value read from address location 0000h. set-up-erase erase commands erase-algorithm initiates with VIL, VIL, VIH, VPPH, enter erase mode, write set-up-erase command, 20h, into command register. After SMJ28F010B erase mode, writing second erase command, 20h, into command register invokes erase operation. erase operation begins rising edge ends rising edge next erase operation requires least complete before erase-verify command, A0h, loaded. Maximum erase timing controlled internal stop timer. When stop timer terminates erase operation, device enters inactive state remains inactive until command received. program-verify command SMJ28F010B programmed sequentially randomly, because programmed byte time. Each byte must verified after programmed. program-verify operation prepares device verify most recently programmed byte. invoke program-verify operation, must written into command register. program-verify operation ends rising edge While verifying byte, SMJ28F010B applies internal margin voltage designated byte. true data programmed data match, programming continues next designated byte location; otherwise, byte must reprogrammed. Figure shows commands operations combined byte programming. erase-verify command bytes must verified following erase operation. After erase operation complete, erased byte verified writing erase-verify command, A0h, into command register. This command causes device exit erase mode rising edge address byte verified latched falling edge erase-verify operation remains enabled until command written command register. determine whether bytes have been erased, SMJ28F010B applies margin voltage each byte. read from byte, bits designated byte have been erased. erase-verify operation continues until bytes have been verified. read from byte, additional erase operation needs executed. Figure shows combination commands operations electrically erasing SMJ28F010B. set-up-program program commands programming algorithm initiates with VIL, VIL, VIH, VPPH, enter programming mode, write set-up-program command, 40h, into command register. programming operation invoked next write-enable pulse. Addresses latched internally falling edge data latched internally rising edge programming operation begins rising edge ends rising edge next pulse. program operation requires completion before program-verify command, C0h, loaded. Maximum program timing controlled internal stop timer. When stop timer terminates program operation, device enters inactive state remains inactive until command received. reset command reset SMJ28F010B after set-up-erase-command set-up-program-command operations without changing contents memory, perofrm consecutive writes into command register. After executing reset command, device defaults read mode.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
fast-write algorithm
Figure shows process flow programming SMJ28F010B. fast-write algorithm programs nominal time seconds.
fast-erase algorithm
Figure shows process flow erasing SMJ28F010B using fast-erase algorithm. memory array must completely programmed (using fast-write algorithm) before erasure begins. Erasure typically occurs second.
parallel erasure
Several devices erased parallel, reducing total erase time. Since rate which each flash memory erase differs, every device must verified separately after each erase pulse. After given device been successfully erased, erase command should reissued this device. devices that complete erasure should masked until parallel erasure process finished (see Figure Examples mask device during parallel erase include driving high, writing read command (00h) device when others receive set-up-erase erase command, disconnecting device from electrical signals with relays other types switches.
flow charts
Figure Figure Figure flow charts showing fast-write algorithm, fast-erase algorithm, parallel-erase flow.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
flow charts (continued)
Operation
Start Address 10%, Setup
Command
Comments
Initialize Address Standby
Wait ramp VPPH (see Note Initialize pulse count
Write Set-Up-Program Command
Write
Write Data Increment Address Wait Write Program-Verify Command X=X+1
Set-UpProgram Write Write Data
Data
Write Standby
Wait Read Fail Verify Byte
Valid address data Wait
Write
ProgramVerify
Data C0h; ends program operation Wait
Standby
Pass Interactive Mode Last Address
Read
Read byte verify programming; compare output expected output
Write Read Command Power Down Apply VPPL Apply VPPL
Write
Read
Data 00h; resets register read operations Wait ramp VPPL (see Note
Standby
Device Passed Device Failed
NOTES: recommended operating conditions value VPPH. recommended operating conditions value VPPL.
Figure Algorithm-Selection Programming Flow Chart
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
flow charts (continued)
Operation Preprogram Bytes Address Initialize addresses 10%, Write Set-Up-Erase Command Initialize pulse count Write-Erase Command Setup Program Bytes
Start
Command
Comments
Entire memory must before erasure fast-write programming algorithm
Standby
Wait ramp VPPH (see Note
Write
Wait X=X+1 Interactive Mode
Set-UpErase
Data
Write Erase-Verify Command
Write
Erase
Data
Wait Increment Address Read Verify Byte Pass Fail 1000?
Standby
Wait
Write
EraseVerify
Addr Byte verify; Data A0h; ends erase operation
Standby
Last Address?
Wait
Read
Write Read Command Apply VPPL Apply VPPL Power Down
Read byte verify erasure; compare output
Write
Read
Data 00h; resets register read operations Wait ramp VPPL (see Note
Device Passed
Device Failed
Standby
NOTES: Refer recommended operating conditions value VPPH. Refer recommended operating conditions value VPPL.
Figure Flash-Erase Flow Chart
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
flow charts (continued)
Start
Program Devices
Give Erase Command Devices
Device
Mask Device
Device Erased
Give Erase Command Unmasked Devices
Devices Erased Give Read Command Devices
1000 Give Read Command Devices
Devices Pass
Finished With Errors
number devices being erased.
Figure Parallel-Erase Flow Chart
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Supply voltage range, Input voltage range (see Note inputs except 13.5 Output voltage range (see Note Output short-circuit current (see Note Operating free-air temperature range during read erase program, 125°C Storage temperature range, Tstg 65°C 150°C Maximum power dissipation, Lead temperature (soldering, seconds) 300°C Junction temperature, 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: voltage values with respect VSS. voltage input undershoot periods less than voltage output overshoot periods less than more than output shorted time, duration cannot exceed second.
recommended operating conditions
Supply voltage Supply voltage During write read flash erase During read only VPPL) During write read flash erase (VPPH) CMOS CMOS 11.4 11.5 12.6 UNIT
High-level High level input voltage Low-level level input voltage Voltage level algorithm-selection mode Operating free-air temperature
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
electrical characteristics over recommended ranges supply voltage operating free-air temperature (unless otherwise noted)
PARAMETER IPP1 IPP2 IPP3 IPP4 ICCS High-level High level output voltage Low-level level output voltage algorithm-selection-mode current Input current (leakage) Output current (leakage) supply current (read standby) supply current (during program pulse) supply current (during flash erase) supply current (during program erase-verify) TTL-input level supply current (standby) CMOS-input level supply current (active read) average supply current (active write) average supply current (flash erase) average supply current (program erase-verify) except TEST CONDITIONS VPPH, VPPL VPPH VPPH VPPH VIL, MHz, IOUT VIL, Programming progress VIL, Erasure progress VIL, VPPH, Program erase-verify progress VPPH Read mode 0.45 200* 5.0* UNIT
ICC1 ICC2 ICC3 ICC4
VLKO erase write-lockout voltage This parameter production tested.
capacitance over recommended range supply voltage
PARAMETER Input capacitance Output capacitance input capacitance TEST CONDITIONS 25°C, 25°C, 25°C, UNIT
This parameter production tested.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
switching characteristics over recommended ranges supply voltage operating free-air temperature (see Figure
PARAMETER ta(A) ta(E) ten(G) tc(R) td(E) td(G) tdis(E) tdis(G) th(D) Access time from address, Access time from chip enable, Access time from output enable, Cycle time, read Delay time, low-Z output Delay time, low-Z output Chip disable time Hi-Z output Output disable time Hi-Z output Hold time, data valid from address, (see Note Series load, load Input Input TEST CONDITIONS ALTERNATE SYMBOL tAVQV tELQV tGLQV tAVAV tELQX tGLQX tEHQZ tGHQZ tAXQX tWHGL '28F010B-12 '28F010B-15 '28F010B-20 UNIT
trec(W) Recovery time, before read This parameter production tested. NOTE Whichever occurs first
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
timing operations (see Figure Figure
ALTERNATE SYMBOL tc(W) tc(W)PR tc(W)ER th(A) th(E) th(WHD) tsu(A) tsu(D) tsu(E) tsu(VPPEL) trec(W) trec(R) tw(W) tw(WH) tr(VPP) tf(VPP) Cycle time, write using Cycle time, programming operation Cycle time, erase operation Hold time, address Hold time, Hold time, data valid after high Setup time, address Setup time, data Setup time, before Setup time, Recovery time, before read Recovery time, read before Pulse duration, (see Note Pulse duration, high Rise time, Fall time, tAVAV tWHWH1 tWHWH2 tWLAX tWHEH tWHDX tAVWL tDVWH tELWL tVPEL tWHGL tGHWL tWLWH tWHWL tVPPR tVPPF '28F010B-12 '28F010B-15 '28F010B-20
UNIT
NOTE Rise fall time
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
timing requirements alternative E-controlled writes (see Figure
ALTERNATE SYMBOL tc(W) tc(E)PR th(EA) th(ED) th(W) tsu(A) tsu(D) tsu(W) tsu(VPPEL) trec(E)R trec(E)W tw(E) tw(EH) Cycle time, write using Cycle time, programming operation Hold time, address Hold time, data Hold time, Setup time, address Setup time, data Setup time, before Setup time, Recovery time, write using before read Recovery time, read before write using Pulse duration, write using Pulse duration, write, high tAVAV tEHEH tELAX tEHDX tEHWH tAVEL tDVEH tWLEL tVPEL tEHGL tGHEL tELEH tEHEL '28F010B '28F010B-12 '28F010B '28F010B-15 '28F010B '28F010B-20 UNIT
PARAMETER MEASUREMENT INFORMATION
2.08 Output Under Test (see Note
NOTE includes probe fixture capacitance.
Figure Test Output Load Circuit
0.45 Note
NOTE testing inputs driven logic high 0.45 logic low. Timing measurements made logic high logic both inputs outputs. Each device should have 0.1-µF ceramic capacitor connected between closely possible device pins.
Figure Test Input Output Waveform
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
PARAMETER MEASUREMENT INFORMATION
tc(R)
ta(A)
Address Valid
ta(E) trec(W) td(E) Hi-Z td(G) ten(G)
tdis(E)
tdis(G) th(D) Ouput Valid Hi-Z
Figure Read-Cycle Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
PARAMETER MEASUREMENT INFORMATION
Program Command Program Latch Verify Address Data Programming Command
Power Set-UpProgram Standby Command tc(W) tsu(A) th(A) tsu(E) th(E) trec(R) th(WHD) tw(W) tsu(D) Hi-Z
Program Verification
Standby Power Down
tc(W)
tc(W) th(A) tsu(A)
tc(R)
tsu(E) th(E) tc(W)PR tw(WH)
tsu(E) th(E)
tdis(E)
trec(W)
tdis(G)
th(WHD) tw(W) tsu(D) tw(W) tsu(D)
th(WHD)
th(D) ten(G) td(G)
Data Data VPPH VPPL tr(VPP) tsu(VPPEL) Data
td(E) ta(E)
Valid Data
tf(VPP)
Figure Write-Cycle Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
PARAMETER MEASUREMENT INFORMATION
Power Set-UpErase Standby Command tc(W) tc(W) th(A) tsu(A) tsu(E) th(E) trec(R) th(WHD) th(WHD) tw(W) tsu(D) Hi-Z Data Data tsu(VPPEL) VPPH VPPL tr(VPP) tf(VPP) Data td(E) ta(E) Valid Data tw(W) tsu(D) th(WHD) tw(W) tsu(D) tw(WH) tc(W)ER tsu(E) th(E) tsu(E) th(E) tdis(E) tc(R) EraseVerify Command
Erase Command
Erasing
Erase Standby Verification Power Down
tc(W)
trec(W) tdis(G) th(D) ten(G) td(G)
Figure Flash-Erase-Cycle Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
PARAMETER MEASUREMENT INFORMATION
Program Command Program Latch Verify Address Data Programming Command
Power Set-UpProgram Standby Command tc(W) tsu(A) th(EA) tsu(W) th(W) trec(E)W
Program Verification
Standby Power Down
tc(W)
tc(W) th(EA) tsu(A)
tc(R)
tsu(W) th(W) tc(E)PR tw(EH)
tsu(W) th(W)
tdis(G)
trec(E)R
tdis(E)
th(ED) tw(E) tsu(D) Hi-Z Data Data VPPH VPPL tr(VPP) tf(VPP) tsu(VPPEL) Data td(E) ta(E) Valid Data tsu(D) th(ED) tw(E) tw(E) tsu(D) th(D) th(ED) ten(G) td(G)
Figure Write-Cycle (Alternative E-Controlled Writes) Timing
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
MECHANICAL DATA
(R-CQCC-N**)
TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
TERMINALS
0.285 (7,24) 0.345 (8,76) 0.445 (11,30) 0.295 (7,49) 0.355 (9,02) 0.455 (11,56) 0.061 (1,55) 0.065 (1,65) 0.065 (1,65)
0.073 (1,85) 0.079 (2,01) 0.079 (2,01) 0.345 (8,76) 0.540 (13,72) 0.540 (13,72)
0.365 (9,27) 0.560 (14,22) 0.560 (14,22)
0.045 (1,14) 0.035 (0,89)
0.025 (0,64) 0.015 (0,38)
0.045 (1,14) 0.035 (0,89)
0.025 (0,64) 0.015 (0,38)
0.028 (0,71) 0.022 (0,56)
0.050 (1,27)
0.055 (1,40) 0.045 (1,14)
0.028 (0,71)
4040137 03/95 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with metal lid. terminals gold plated.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
SMJ28F010B 131072 8-BIT FLASH MEMORY
MECHANICAL DATA
(R-CDIP-T32)
1.620 (41,15) 1.580 (40,13)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
0.605 (15,37) 0.585 (14,86)
0.065 (1,65) 0.045 (1,14)
0.120 (3,05) 0.089 (2,26)
0.060 (1,52) 0.030 (0,76)
0.610 (15,49) 0.590 (14,99)
Seating Plane
0.100 (2,54)
0.021 (0,53) 0.015 (0,38)
0.175 (4,45) 0.125 (3,18)
0.014 (0,36) 0.008 (0,20) 4040280/B 03/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. This package hermetically sealed with metal lid. terminals will gold plated.
POST OFFICE 1443
HOUSTON, TEXAS 77251-1443
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1998, Texas Instruments Incorporated

Organization 8-Bit Flash Memory Compatible With Existing 1M-bit EPROMs

Top Searches for this datasheet

Other recent searches