S.K. Leong POLYFET DEVICES August 1991 Power Mosfets have made conside

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S.K. Leong POLYFET DEVICES August 1991 Power Mosfets have made conside

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Surfacing facts DMOS Power transistors from Published Data Sheets
S.K. Leong POLYFET DEVICES August 1991 Power Mosfets have made considerable progress since days introduction some years ago. Original manufacturers, Siliconix Acrian have left field, others have come take their places. technology improved over course years mainly changing device methodology from VMOS DMOS structure. Compared capabilities achieved very early days, power output 600W being achieved Motorola 1000 delivered Polyfet gold metallized devices. industry served select companies, namely Polyfet Devices (Producer first gold metallized Cross Section Vertical DMOS transistor Fets), MA-COM PHI, Motorola, Phillips Thomson CSF. N-channel enhancement mode vertical D-MOS transistor choice structure employed these companies. Although DMOS common denominator, there enough differences design processing details distinguish transistors from make another despite similar attributes. Therefore, more than likely, some re-tuning matching networks will required when substituting devices. This also true Semetex counterfeit devices. Semetex neither licensee approved second source Polyfet's patented devices.) Some parameters affecting performance junction parasitic capacitances, (Forward Transconductance) maximum drain current, Idsat. Most this information readily available from published data sheets. intent this article provide engineer some basic knowledge extract "behind scene" information various manufacturers identify different geometries used create their line transistors.
Vertical DMOS Basics
First, shall review fundamentals DMOS transistor order relate physical properties data sheet electrical parameters.
Fig. shows cross section Vertical DMOS structure continuous gate design, employed most manufacturers, shows discontinuous gate design employed Polyfet. term DMOS stands Double Diffused MOS. Although this technology invented over years ago, progress overshadowed success familiar lateral device structure universally employed digital circuits. Originally primary advantage DMOS over standard ability form control very narrow channels. Whereas standard relied photo-lithography control channel lengths about microns; DMOS able achieve controls micron less depending precise controllable diffusion junction depths. DMOS processing channel length formed difference side diffusion between Source diffusion VDMOS Continuous Gate Design Body diffusion. Current flow enhancement mode DMOS transistor begins when positive gate voltage greater than threshold voltage device applied. Referring Fig. current flows laterally from source, through channel then "vertically" down drain. term Vertical DMOS derived from this pattern current flow. This pictorial representation current flow Motorola's TMOS devices.
Drain Current Gate Voltage Relationship
classical square equation describing current flow devices when drain voltage that much greater than Gate voltage, describe below However this equation does hold short channel DMOS devices, especially higher current levels, carrier velocity saturation high longitudinal electric field. high drain currents, better described where:-
_0.5
Drain current Width gate transistor. (Perimeter) Channel length. Electron mobility Gate capacitance unit area; inversely proportional gate oxide thickness Applied Gate voltage. Gate threshold voltage. (Usually measured gate voltage required cause drain current flow. confused data sheet VGS(th) which measured very high drain currents.)
where:vs electron drift velocity
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width, gate deserves further clarification. shows view DMOS transistor cell. high power DMOS transistor designs, many cells paralleled together achieve large value; thus achieving large perimeter value. case Polyfet design, dice 1.25 long respectively. channel length, which often called gate length, defined lateral spacing difference formed side diffusions source body. Unlike, lateral devices, independent gate material geometry. Polyfet designs, micron wide. Large ratios necessary achieve high Idsat Rdon values. contrast Bipolar transistors which benefit base conductivity modulation obtain saturation voltages, transistors have resort large active areas achieve same. This prime reason DMOS transistors more expensive then their bipolar counter parts. However, DMOS transistors have many superior attributes, such higher power gain wider bandwidth, more than justify premium. From Equation note other parameters that adjust achieve high Idsat higher electron mobility Mobility affected doping density silicon crystal orientation. main advantage DMOS over VMOS that mobility higher; difference crystal plane, <111> <100>, along which electrons flow. (650 volt-sec.) enhanced thinning down gate oxide thickness. This value ranges from 1200o from manufacturer manufacturer. trade with thin gate oxides lower Gate Source voltages which point would rupture. Most manufacturers guarantee minimum gate oxide breakdown while typical values excess 60v. other trade offs with thin gate oxides increases parasitic capacitances Crss Ciss. Another process parameter change that improve Idsat Rdsat (Rdon) increase doping material. higher doped lowers drain resistance. However, final limitation governed desired minimum Bvdss value. achieve Bvdss greater than volts achieve some degree ruggedness, doping levels usually kept about ohm-cm epi. Parasitic capacitance, Coss, directly affected doping density. Using high doping densities achieve Rdsat penalty higher Coss values.
Forward Transconductance
measured ratio change drain current change gate voltage fixed drain source voltage. constant varies with applied gate voltages. shows typical plot Polyfet equivalent part from PHI; series. gate voltages, increases with increasing gate voltage governed square relationship described Equation higher gate voltage about volts begins saturate accordance Both devices have very similar characteristics rated similarly power well. maximum value scattering-limited drift velocity value about cm/sec. devices with 1000oA gate oxide, maximum Gm/unit length perimeter 24umho/micron. even higher gate voltages, begins fall pinching effects parasitic JFET finite source drain resistances. rate fall reduced keeping body separation large. adverse effect increase gate drain capacitance continuous gate designs. Unlike Bipolar transistors where Beta increases with temperature, decreases with increasing temperature. This self regulating feature prevents thermal runaway, adding ruggedness MOSFET transistor.
Polyfet Devices Written S.K. Leong Phone (805)484-4210
Polyfet equivalent
Derivative
Note constant
Derivative
very important feature transistor maximum frequency operation, directly proportional inversely proportional input capacitance. Further more, since proportional W/L; shown that inversely proportional square channel length,
Polyfet Devices Written S.K. Leong Phone (805)484-4210
power gain amplifier been demonstrated function well. This relationship shown Equation Obviously, have good performance, power gain linearity, desirous have
characteristics that high, obtained gate voltages flat possible over wide range gate voltage. Achieving these require good device design manufacturing techniques. Since other parameter obtaining good performance Crss, important relationship exists between Crss. higher Gm/Crss ratio, higher performance capability transistor.
Capacitances
Three capacitances associated with device shown Fig. gate structure capacitances both drain, Cgd, source, Cgs. inherent body drain junction forms Cds. However, instead these capacitances, manufacturers report values Ciss, Crss Coss their data sheets. Ciss parallel combination Coss parallel combination Cgd. Crss same Cgd. Since quite small compared Cds, Coss nearly equal Cds. relationship these capacitances voltage bias Polyfet shown
Coss Output Capacitance
This primarily diode junction capacitance formed between body Nepi. with junction capacitance, highest value when there bias across Drain Source/Body. Upon application drain voltage, depletion layer which increases width with increasing drain voltage formed. Fig. depletion width increases, capacitance, which DMOS Capacitances inversely proportional plate spacing, falls rapidly. manufacturers specify Coss VDS, when minimum. Since Coss body area dependent doping very similar value among manufacturers, equal Bvdss devices, value Coss used direct comparison active device area from design another.
Ciss Input Capacitance
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Ciss does vary much with Drain Source voltage bias. Most this capacitance formed between Source metal interconnects Gate material. dielectric between these materials silicon dioxide. Other than keeping this oxide maximum, other option keep Source metal area minimum. This more easily achieved using Gold metallization because this higher current density capability compared Aluminum. Other contributions Ciss Gate Source overlap capacitance gate channel capacitance. Gate Source overlap area formed side diffusion Source under gate material. typical DMOS processing, this order perhaps half micron. With Patented Polyfet process, this overlap essentially zero. Therefore, with given transistor size, value Ciss desirable. importance value Ciss relationship shown
Crss Feedback capacitance
Despite being lowest absolute value among three capacitances, most effect performance. bipolar transistor, this also Miller capacitance suffers from voltage gain multiplication; zero bias voltage, this capacitance formed between
Miller Crss(1+
Miller Crss
Capacitance Polyfet devices gate material drain. drain voltage applied, depletion width formed body drain junction creates another capacitor which connects series former. Being lower value, ultimately dominates drain voltage increased. This explains rapidly falling value Crss increasing Vds. continuous gate designs, separation distance between body body kept minimum achieve Crss values. This disadvantage reducing Idsat because reduces parasitic JFET current saturation capability. Visualize this throat pipe being squeezed down size infringing body diffusions. Given active transistor area, keeping Crss small while impairing Idsat, challenge device designers. good figure merit transistor ratio Crss/Coss.
Ratio Analysis
examining ratios above mentioned parameters determine make transistor. common practice Power transistor
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Crss with Reverse Bias Voltage, Vds.
manufacturing wire bond dice parallel achieve higher Power output levels. example, Polyfet F2001 made with package rated 2.5W 1000 Mhz. When dice wired parallel same package, part rated 1000 Ghz; F2012. Upon reviewing values capacitances data sheets, ratio between transistors seen. another example, this same ratio found between BL242 BL244 devices. (See Table details) above examples describe single ended devices. Push pull transistors assembled with single ended devices common flange. Data sheets report characteristic side only. comparison study between UF2820R UF2840P identifies former having single ended configuration later push pull configuration. push pull rated single ended 20W. other hand, 28100M push pull configuration evidenced ratio capacitance values. identity obtain evaluating ratios such Gm/Crss Crss/Coss absolute values Coss. this method determine different basic types used create product line. Additionally, generic that used make product line identified this way. Manufacturers will same create more lines testing different frequencies. This evident between UF28XX devices their LF28xx devices. Note ratios Gm/Crss, Gm/Coss Crss/Coss same these series, indicating same generic being used. Additionally, LF2805A UF2805B same part tested Coss single device different frequencies. plot Coss Idsat parts from various manufacturers. correlation between strong. mentioned earlier. Coss directly proportional which parameters Idsat equation. (See Table single devices' Coss highlighted.
Conclusion
There that learned careful study Data Sheets. having better knowledge make transistor product line make engineer more profit when choosing transistors applications.
Polyfet Devices Written S.K. Leong Phone (805)484-4210
Table Comparison various device characteristics
S.E.=Single Ended; Push Pull (Prefer high) (Prefer low) TEST Min. ConfiRATIO RATIO FREQ GAIN guraTypical values CRSS/ IDSAT DEVICE POUT Dice tion COSS CRSS CISS CRSS COSS COSS AMPS SERIES LF2802A 1000 0.04 6.67 2.00 30.00 LF2805A 1000 0.08 LF2810A 10.0 1000 0.16 12.0 POLYFET SERIES F2001 F2002 F2021 F2012 10.0
1000 1000 1000 1000
0.20 0.40 0.60 0.80
12.0 18.0 24.0
18.0 27.0 36.0
20.00
3.33
16.67
SERIES APPEARS SERIES LOWER PERFORMANCE UF2805B 0.08 6.67 UF2810P 10.0 0.08 UF2815B 15.0 0.24 12.0 18.0 OLDER SERIES DU2820S 20.0 DU2840S 40.0 DU2860T 60.0 SERIES UF2820R 20.0 UF2840P 40.0 UF28100M 100.0 UF28150J 150.0 POLYFET SERIES F1069 20.0 F1058 30.0 F1008 40.0 F1072 100.0 F1015 100.0
2.00
30.00
0.50 1.00 1.50 0.60 0.60 1.80 2.40
30.0 60.0 90.0 25.0 25.0 75.0 100.0
16.0 24.0 24.0 32.0
30.0 60.0 90.0 35.0 35.0 105.0 140.0
6.25 7.50
1.67 2.40
26.67 32.00
0.80 0.80 1.60 2.40 3.20
20.0 20.0 40.0 60.0 80.0
12.0 16.0
30.0 30.0 60.0 90.0 120.0
20.00
4.00
20.00
10.0 15.0 20.0
PHILLIPS 500Mhz SERIES BLF543 10.0 BLF544 20.0 BLF545 40.0 BLF546 80.0 BLF548 150.0 ACRIAN ISOFET SERIES VMIL20FT 20.0 VMIL40FT 40.0 VMIL120FT 120.0 MOTOROLA SERIES MRF175LU 100.0 MRF175GU 150.0
0.30 0.60 0.60 1.20 2.40
12.0 24.0 24.0 48.0 96.0
12.8 25.6
16.0 32.0 32.0 64.0 128.0
9.38
2.50
26.67
10.0 20.0
0.35 0.70 2.10
40.0 80.0 240.0
12.0
30.0 60.0 180.0
17.50
0.88
5.00
3.00 3.00
200.0 200.0
20.0 20.0
180.0 180.0
15.00
1.50
10.00
PHILLIPS FREQ SERIES BLF242 BLF244 15.0 BLF245 30.0
0.15 0.60 1.20
10.0 40.0 80.0
15.0 60.0 120.0
15.00
1.50
10.00
10.07
Polyfet Devices Written S.K. Leong Phone (805)484-4210
Additional Reading U.S. Patent 4,561,168. "Method Making Shadow Isolated Metal DMOS Devices. Inventors Pitzer Rice. Assignee: Siliconix. 1985 U.S. Patent 4,866,492. "Low Loss Fet". Inventor: Fred. Quigg. Assignee: Polyfet Devices. 1988. U.S. Patent 4,877,749. "Method Forming Loss Fet". Inventor: Fred. Quigg. Assignee: Polyfet Devices. 1988. "Double Diffused transistor achieves microwave Gain." Gauge Electronics Feb. 1971. "Physics Semiconductor Devices" S.M. Sze. Edition, John Wiley Sons. Chapter "Mosfet" Spice Subcircuit Representation Power Mosfets using Empirical Methods" Dolny Review, Sept. 1985. 308-320. Power Amplifier Design Using VMOS Power FETs". Leighton, Design, Jan. 1980; 32-37. Power Fets. Their Characteristics Applications" Helge Granberg. Motorola Application Note AR346. "Understanding Data Sheet Parameters" Norman Dye. Motorola Application Note. AN1107.
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S.K. Leong POLYFET DEVICES August 1991 Power Mosfets have made conside

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