DATA BOOK ADVANCED INFORMATION AUGUST 1996 Revision Microele
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ACC2087 ENHANCED SUPER CHIP
DATA BOOK ADVANCED INFORMATION
AUGUST 1996 Revision
Microelectronics Corporation, 2500 Augustine Drive, Santa Clara, 95054 Phone: (408) 980-0622 Fax: (408) 980-0626
Micro
Microelectronics Corporation 2500 Augustine Drive, Santa Clara, 95054 Phone: (408) 980-0622 Fax: (408) 980-0626 Copyright 1996 Microelectronics Corporation. rights reserved. 520141 Revision August 1996 part this document copied reproduced form means without prior written consent Microelectronics Corporation. Microelectronics Corporation makes warranty products bears responsibility errors which might appear this document. Specifications subject change without notice. Micro trademark Microeletronics Corporation. IBM, PS/2, Micro Channel trademarks International Business Machines. Pentium, Intel trademarks Intel Corporation. trademark Cyrix Corporation. trademark Advanced Micro Devices
Microelectronics Corporation, 2500 Augustine Drive, Santa Clara, 95054 Phone: (408) 980-0622 Fax: (408) 980-0626
Micro
Table Contents
Title ACC2087 Introduction ACC2087 Features ACC2087 System Block Diagram ACC2087 Internal Block Diagram ACC2087 Functional Description Interface 80387 Interface Control Clock Generator Clock Mode Selection Stop Grant, Stop Clock, Clock Scaling Clock Throttling Local Peripheral Support Intel System Management Mode Interface Power Management Features 2.10 Shadow Register Table Description 2.11 High Performance Cache Controller 2.12 Memory Controller 2.13 Memory Mapping 2.14 Shadow 2.15 Interrupt Controllers 2.16 2.17 Memory Mapper 2.18 Timer/Counter 2.19 ACC2087 Address 2.20 2.21 Arbitration Logic 2.22 Refresh Generation Logic 2.23 Staggered Refresh Logic 2.24 Port Logic 2.25 Controller Converter 2.26 Turbo Speed Control Logic 2.27 8-bit/16-bit Options 2.28 128K/64K BIOS Range 2.29 Reset Shutdown Logic 2.30 OS/2 Optimization 2.31 Floppy Disk Drives 2.32 Serial Port Interface 2.33 Parallel Port Interface Page
Micro
Table Contents Title ACC2087 Description ACC2087 Descriptions Clock Interface Reset Interface Interface Power Management/Cache/DRAM/AT Multiplex Interface Dedicated Power Management Interface Dedicated Cache Interface DRAM Interface Interface Keyboard/Mouse Interface 3-10 Interface 3-11 COM1 Interface 3-12 COM2 Interface 3-13 LPT1 Interface ACC2087 Numerical List ACC2087 Desktop Notebook Multiplexed Summary ACC2087 Pins Status Various Types ACC2087 Numerical List with Multifunction pins Power Plane Description contd. Page
ACC2087 Register Settings ACC2087 Register Settings
ACC2087 Upgrade Advanced Parallel Port Description, Features, Block Diagram Features Block Diagram Programmable Configuration Registers Parallel Port Interface
ACC2087 Specifications ACC2087 Specifications ACC2087 Package Specifications
Appendix List Sales Representatives
MicroSection Introduction 2087 Features
Supports Intel iDX4, AM486, Cyrix 5x86, 486s, Blue Lightning microprocessor with operation 3.3V 5.0V mixed voltage system design Level Write Back Cache Level Cache Controller
Support either write back write through implementation cache size
High Performance DRAM Controller
Supports four banks 32-bit DRAM, Fast Page Mode only, allowing memory
Integrated Peripheral Controller: 8237, 8259, 8254, 74612 Integrated Floppy Disk Controller supports floppy disk drives Supports interface Supports high speed 16C550 compatible UARTs with Byte FIFOs Supports bi-directional Parallel port with mode Support mode where Floppy Disk Drive used Parallel Port PS/2 compatible Keyboard Controller Mouse Power Management Control
Power-On Suspend Power-Off Suspend Doze Idle Detection Suspend resume Button support Stop Clock Protocol Battery monitoring signal dedicated low-battery warning alarm
Supports Flash EPROM Local Fast reset Fast gate (Port 256-pin PQFP device
Micro2087 System Block Diagram
Micro2087 Internal Block Diagram
MicroSection Functional Description
Interface
ACC2087 supports 386DX CPUs. interface selection determined detecting pull pull down resistor (M486) during reset period. pull resistor will trigger ACC2087 operating mode. pull down resistor will trigger ACC2087 operating 386DX mode. 486DX mode configuration mode configuration
80387 Interface Control
80387 interfaces directly 386DX with error-reporting logic built ACC2087. coprocessor error sent ACC2087, generating interrupt request CPU, followed service request. write operation port will clear interrupt request. Clock Generator
ACC2087 Clock Generator provides flexible clock signals support internal external timing requirements. Clock outputs CPU, NPU, Keyboard Controller generated from these inputs. Three clock sources (CLKSRC, X24M X14M) used derive system clock output (SYSCLK). Signal X14M interfaces 14.318 crystal generate 14.318 frequency. crystal used signal X24M provide timing signal integrated floppy disk controller. CLKSRC input same input clock. CLKSRC input must driven external oscillator. This input times operation clock provides turbo mode operation clock mode, respectively. clock derived from three sources: CLKSRC, X14M, X24M programming register 4-0). CLKSRC divided approximated 16MHz frequency, 14.318 directly, generated from external directly.
MicroClock Mode Selection
ACC2087 supports both clock clock. clock phase determined selecting CLKX1 signal clock from ACC2087 selecting CLKX2 signal clock from ACC2087. clock clock source, which times operation clock. clock, every cycle consists CLKI periods. clock used both 486DX/SX systems 386DX systems. mode, ACC2087 provides dedicated Clock, which half CLKSRC This pin, (pin CLKx2, actually phase reference clock.
clock clock clock source which times operation clock. clock, every CLKI input period becomes completed cycle. clock used primarily systems. CLKx1 used clock input.
clock
MicroStop Grant, Stop Clock, Clock Scaling:
Notebook system, ability switch clock very important feature power saving. ACCACC2087 supports this feature providing interface Stop Grant Stop Clock Clock Scaling functions.
ACC2087 Clock Scaling
Clock Stop-Grant Protocol Clock Mode: When Register Register ACC2087 set, "Turbo" toggle clock between turbo sleep frequency. clock also switched between turbo sleep frequency programming Register toggle frequency. Clock Mode: When Register zero, ACC2087 will toggle between turbo sleep frequency.
MicroClock Throttling:
further reduce power consumption Notebook system, ACC2087 supports another mode called Clock Throttling. After scaling clock, ACC2087 periodically assert STPCLK# request which will force into Stop Grant State. Hence power further reduced. Local Peripheral Support Master Mode Support Local Cycle
ACC2087 supports VL-Bus with master modes. further enhance flexibility, local detected under System Management Mode (SMM). ACC2087 determines whether cycle local cycle detecting existence local cycle signal, signaled local device. When ACC2087 Register 1Bh, one, (READY0#, LBA#) becomes LBA# pin. This connected local device's local acknowledge signal. When LBA# asserted low, ACC2087 will terminate cycles, relinquish control local bus. ACC2087 starts sense LBA# status from until beginning ENABUS# shown below.
Local Detection
Micro
local devices operating with fast speed clock, ACC2087 offers option delay ADS# cycle internally detect local acknowledge delay cycle shown below. Register 1Ah, programs ACC2087 internal ADS# timing. Register 18h, programs cycle delay.
Local Delay Option
Intel System Management Mode Interface (SMM)
System Management Mode (SMM) designed handle power management interrupts that totally transparent existing programs, operating systems operation modes. ACC2087 contains dedicated logic interface with implemented Intel SL-enhanced battery-powered portable computers. ACC2087 utilizes DRAMs located between segments A000h B000h separate memory (SMRAM) required functions. Before activating function, system BIOS first needs load service routine into separate memory (SMRAM). During power-up, system BIOS turn ACC2087 remap feature that memory physically located between segment A000h segment B000h accessed logically through locations between 128K memory installed system. system BIOS then loads code into this area, disables remap then enables ACC2087 support. remap space reserved SMM. blocks available programmed segment 3000h executing handler. remap function will available when used.
Micro
SM-RAM Mapping Initializing System Management Mode power management interrupt generated ACC2087 connected SMI# pin. interface circuit been integrated ACC2087 handle cycle, memory map, internal cache. ACC2087 will enter cycles when detects SMIACT# being asserted CPU. physical memory (30000h 3FFFFh) dedicated System Management Mode (SMM) will enabled. will this dedicated SMRAM perform state save state restore starting address location 3FFFFh, proceeding downward stack-like fashion execute handler starting address location 38000h. Register ACC2087 contains enable bits. Setting will enable While provides access SMRAM starting segment 3000h.
System Management Mode Interface (Intel SL-Enhanced CPU)
MicroPower Management Features
ACC2087 provides powerful mechanism system power management that completely transparent operating system application software. designed from system level synthesize manage power consumption lowest power operation while maintaining system performance portable system. ACC2087 implements four special power saving modes provide most sophisticated system information needed power management application. They "Local Standby" "Global Standby" "Suspend Resume" "Doze" mode. ACC2087 also provides dedicated battery input (LBAT#) warning timer external battery pack. transition LBAT# should trigger this programmed warning timer. 1khz tone will generated through speaker output soon LBAT# transition detected. transition been detected, upon warning timer time-out, will generated. Local Standby Mode (LSM) "Local Standby" mode provides three dedicated local standby control circuits monitor activity address general chip select (GCS), VRAM, Keyboard/Mouse, respectively. When associated programmed timer timed out, optional will generated status will set. break event such hard disk access will generate bring system back normal operation. Global Standby Mode (GSM) When system been idle programmed standby timer count there screen activity programmed VRAM count, system into global standby mode. peripheral devices powered clock stopped under global standby mode. Suspend Resume Mode suspend mode entered pressing suspend/resume button receiving battery input. addition suspend resume button, ACC2087 user-defined buttons, User button Standby button, which bring system suspend mode. suspend disk resume feature also supported ACC2087 through SL-compatible shadow register. Doze Mode Doze mode provides mechanism that allows power saving even between keystrokes. This mechanism utilizes Frequency Modulation (FM) Pulse Modulation (PM) techniques which commonly used telecommunications field. This mode used only provide temperature control when busy (non-Doze) also further reduce power consumption when busy (Doze).
MicroArchitecture System Power Management
2.10
Shadow Register Table Description
defined register bits ACC2087 readable writeable support Intel type shadow register. Also register readable further support power-saving feature. Through shadow registers, ACC2087 powered current state suspended disk. device then powered back same state before last power when desired. This suspend resume capability minimizes system's battery power consumption. Table summarizes shadow registers their descriptions. registers listed originally write-only standard. shadow mechanism makes them readable through 0F2h/0F3h indexing scheme.
some registers that contain bytes have only index assigned, following sequence must followed: 0f2h, indx ;make sure sequence will broken ;output index, clear byte pointer, point byte
of3h
;save somewhere ;high byte, byte pointer will changed, stay high byte.
Micro
mask
write 0F2h with index 0Axh will clear byte pointer, which will pointer byte. first read from 0F3h after writing index will pointer high byte. Only byte pointer shared paired register sets. first read from 0F3h will return byte, second read will return high byte.
those registers that bits, unused bits status undefined. Software needs these bits when restores. base address registers, word count registers, channel mode registers, channel mask registers, value read back from shadow registers original values loaded. value read back from shadow registers timer count original values loaded.
MicroShadow Register Table Register Name Base Address Count Base Address Count Base Address Count Base Address Count Mode Mode Mode Mode CNTLR Mask Reg. PIC1 ICW2 PIC1 ICW4 PIC1 OCW3 Mask index CNTR CNTR high CNTR CNTR high CNTR CNTR high Base Address Count Base Address Count Base Address Count Base Address Count Mode Mode Mode Mode CNTLR Mask Reg. PIC2 ICW2 PIC2 ICW4 PIC2 OCW3 Mnemonic SHDMA0BA SHDMA0WC SHDMA1BA SHDMA1WC SHDMA2BA SHDMA2WC SHDMA3BA SHDMA3WC SHDMA0MOD SHDMA1MOD SHDMA2MOD SHDMA3MOD SHDMAMSK1 SHINT1ICW2 SHINT1ICW4 SHINT1OCW3 SHNMIMASK SHT1CH0CL SHT1CH0CH SHT1CH1CL SHT1CH1CH SHT1CH2CL SHT1CH2CH SHDMA4BA SHDMA4WC SHDMA5BA SHDMA5WC SHDMA6BA SHDMA6WC SHDMA7BA SHDMA7WC SHDMA4MOD SHDMA5MOD SHDMA6MOD SHDMA7MOD SHDMAMSK2 SHINT2ICW2 SHINT2ICW4 SHINT2OCW3 Original Address 0C0h 0C2h 0C4h 0C6h 0C8h 0CAh 0CCh 0CEh 0D6h 0D6h 0D6h 0D6h 0DEh 0A1h 0A1h 0A0h Index 0A0H 0A1h 0A2h 0A3h 0A4h 0A5h 0A6h 0A7h 0C0h 0C1h 0C2h 0C3h 0C4h 0D0h 0D1h 0D2h 0D6h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0A8h 0A9h 0AAh 0ABh 0ACh 0ADh 0AEh 0AFh 0C5h 0C6h 0C7h 0C8h 0C9h 0D3h 0D4h 0D5h Comment bytes bytes bytes bytes bytes bytes bytes bytes byte byte byte byte 1byte byte byte byte byte 1byte byte byte byte byte byte bytes bytes bytes bytes bytes bytes bytes bytes byte byte byte byte byte byte byte byte
Micro2.11 High Performance Cache Controller
integrated ACC2087 cache controller supports direct mapped cache from Kbytes Mbytes size. direct mapped architecture means that specified line cache capable caching only certain range memory addresses. order address bits choose location (index) while high order address bits (tag) identify entry. write policy, ACC2087 supports either write through write back cache implementations. addition, ACC2087 cache architecture used both 386DX applications. 386DX design, ACC2087 cache controller used support primary cache. system, internal cache enabled, ACC2087 direct mapped cache used secondary cache. Write Back Cache Policy write back cache policy implemented ACC2087 allows system minimize frequency unnecessary slow DRAM updates. instance, when there consecutive write cycles, ACC2087 simply updates cache without introducing memory delay. write back cache design allows write cycles completed zero wait state accesses without updating system main memory. Therefore, "stale" data created where cache data main memory data coherent. write back cache design uses "dirty" keep track whether each cache data line "clean" "dirty" line. "clean" line, dirty means cache data corresponding main memory identical. "dirty" line, dirty indicates cache data been modified, which some point must written back main memory. Following write back cache mechanism ACC2087: Write cache write cycle, ACC2087 will write cache "dirty" Write Miss cache write miss cycle, ACC2087 will write DRAM directly. Read cache read cycle, ACC2087 will read from cache directly. Read Miss cache read miss cycle, ACC2087 will examine "dirty" status. non-dirty, cache will updated directly. dirty, cache data will "write back" before being updated. ACC2087 write back cache enabled programming configuration register When Register write back enabled ACC2087 will integrated comparators determining cache miss status. described earlier, "dirty" status must updated well detected write back mode. MA10 becomes dirty status signal (DIRTY) becomes dirty write enable signal (DTYWE#). Refer figure 1.4.
MicroPosted Write Write Through
ACC2087 cache controller supports write-through post write cache update options prevent data from being used. write-through option simplest keep cache coherent. cache write cycle, memory controller will update DRAM same time that written cache. ACC2087 cache controller default mode write-through mode.
Write Back Cache Circuit Block Diagram ACC2087 also supports posted write cache system programming Configuration Register 7=1. posted write option allows data buffered before updating main memory. system performance therefore increased, since processor start cycle before write cycle main memory completed. Cache Burst Line Size ACC2087 supports flexible line size structure cache burst. ACC2087 supports bit, bit, line sizes. Configuration Register bits determine line size. case cache read cycle, ACC2087 will pull burst ready signal, BRDY#, fill internal cache lines quickly. line size requires only cycles fill cache lines. line size requires cycles. case read miss cycle, ACC2087 burst mode will generate four continuous DRAM read cycles line size fill both internal external cache. line size, ACC2087 burst mode will generate burst cycles instead four. 2.12 Memory Controller
Memory Controller feature ACC2087. This versatile circuit provides complete control megabytes system DRAM. control mode, generates four Address Strobes (RAS#0-3) Memory Write Enable signal (WEN#). Memory Controller also provides interface transfer control controller master. ACC2087 Memory Controller supports 256KB, 512KB, DRAM devices. ACC2087 provides control signals programmable control support 256Kx1, 512Kx1, 1Mx1, 1Mx4, 4Mx1 4Mx4 (symmetrical only).
Micro2.13 Memory Mapping
Memory Mapping translates system within range, which reserved system BIOS application, accessible address range above physical space. example, memory installed, memory mapping feature DRAMs range mapped address immediately above Memory Mapping enabled Register configuration registers. When Shadow enabled simultaneously with Memory Mapping, quantity available Memory Mapping reduced. Shadow segment enabled, 320KB mapped. Shadow segment enabled, 256KB mapped. segments enabled, mapped. This mapping function used memory options, except option 2.14 Shadow
Shadow provides option transfer BIOS video-extension BIOS program codes into system RAM. This option provides significant performance improvement applications requiring intensive BIOS calls. Shadow implements alternate BIOS source copying complete EPROM program code into system RAM. This referred "shadowing" because DRAM EPROM both located same physical address space. This change transparent rest system. then disabled, allowing respond place. ACC2087 Shadow configured five independent segments: 00C0000 00C7FFF (Shadow C0), 00C8000 00CFFFF (Shadow C1), 00D0000 00DFFFF (Shadow 00E0000 00EFFFF (Shadow 00F0000 00FFFFF (Shadow Each segment enabled shadow operation individually simultaneously. Enabling Shadow segment requires steps. "shadow enable" configuration segment shadowed must allow transfer code from EPROM DRAM. second step sets "Shadow Read Only" configuration corresponding segment protect Shadow RAM. Interrupt Controllers 2.15 Interrupt Controllers
There programmable interrupt controllers ACC2087. They fully compatible with Intel's 8259 controller, providing interrupt sources external internal). internal line connects 8254 Counter output. These interrupt controllers prioritize interrupt requests CPU. 2.16
ACC2087 controllers, compatible with Intel 8237, which provide total seven external channels. Combined with Memory Mapper, each channel 24-bit address output access data throughout megabyte system address space.
Micro2.17 Memory Mapper
ACC2087 built-in logic equivalent 74LS612, generating upper address bits during cycle. 2.18 Timer/Counter
ACC2087 provides three internal counters, which compatible with 8254. clock input each counter tied clock 1.19 MHz, which derived dividing 14.318 crystal input output Counter connected IRQ0 input interrupt controller Counter initiates refresh cycle Counter generates sound waveforms speaker. 2.19 ACC2087 Address
ACC2087 address decode fully compatible PC/AT requirements. ACC2087 decoded address range from allow users areas used PC/AT. Range 000-00F 020-021 040-043 060/064 060-064 070-071 080-08F 0A0-0A1 0C0-0DF 0F8-0FF 2.20 Device controller 8237A-5 Interrupt controller 8259A, Master Timer, 8254 Integrated Keyboard Controller External Keyboard Controller Real-time clock, (non-maskable interrupt) mask page register, 74LS612 Alternative Gate FAST RESET Register. Interrupt controller 8259A controller 8237A-5 Clear Math Coprocessor Busy Reset Math Coprocessor ACC2087 Configuration Register Index ACC2087 Configuration Register Data Math Coprocessor
system configuration control speaker port. also circuitry detect refresh. This condition read back Port 61h. 2.21 Arbitration Logic
There possible sources hold request CPU. Either controller issues hold request output Counter 8254 makes high transition. HOLD line active when either source requesting hold. ACC2087 contains logic arbitration. 2.22 Refresh Generation Logic
ACC2087 contains circuitry perform DRAM refresh cycle. Refresh circuitry contains 8-bit counter address SA0-7 during refresh. addition, three more address counter bits presented inside ACC2087 support refresh DRAMs bits.
Micro2.23 Staggered Refresh Logic
ACC2087 refresh logic works perform periodic refresh both system DRAM extended Bus. ACC2087 initiates refresh cycle driving REFRESH# output low, driving refresh address onto Bus, simultaneously generating staggered refresh pulses four outputs. outputs staggered reduce current drain caused refresh operation. During each refresh cycle, ACC2087 drives current refresh address onto address bus. This provides refresh address extended memory. 2.24 Port Logic
ACC2087 contains non-maskable interrupt (NMI) signal generation logic. caused error parity error. Port identifies source error. power signal masked off. enabled writing address with low; disabled writing address with high. 2.25 Controller Converter
flexible ACC2087 Controller provides control logic needed interface CPU, alternate masters, local memory, primary secondary cache bus. Each access initiated ACC2087 decoding address cycle type provided local bus. cycle type determined monitoring signals D/-C, W/-R M/-IO. controller seven modes operation which defined follows: Local Memory Mode Local memory mode entered addresses part installed memory cycle defined memory access. Local Peripheral Mode Local Peripheral Mode entered when ACC2087 LBA# signal asserted during local cycle. ACC2087 will ignore transactions when LBA# properly asserted. local peripheral decodes local address accesses local device. peripheral will assert LBA# properly complete cycle. When local peripheral interface enabled, READY# available coprocessors. Weitek device should treated local peripheral device. accesses will always include wait state. Mode This mode active when HLDA low. controller generates IOR#, IOW#, INTA#, MEMR#, MEMW# signals. Mode mode active HLDA active. controller drives IOR#, IOW#, MEMR#, MEMW# signals.
MicroRefresh Mode
Refresh mode active when HLDA REFRESH# active. MEMR# becomes active this time perform refresh both local DRAM. Master Mode Master mode active when HLDA active card slot pulls MASTER# low. card controls system address, data line control line. Conversion Mode ACC2087 contains logic convert between 16-bit 8-bit data accessing. During conversion cycle, command strobe (MEMR#, MEMW#, IOR#, IOW#) activated times. 2.26 Turbo Speed Control Logic
clock frequency switched between CLKSRC clock. frequency switch generated through either hardware software. TURBO provided support front panel turbo speed switch. TURBO high selects CLKSRC clock. TURBO selects clock clock. power conservation, standby mode clock control provided. system needs pre-select standby frequency first, then BIOS will monitor activity system. pre-defined conditions standby mode satisfied, system will into standby mode programming Register Turbo/Sleep been Turbo pin, when driven low, will force system into sleep mode. standby mode operating frequency pre-set programming bits configuration Register clock source MHz, standby frequencies output CLKOUT follows: Frequency
Micro2.27 8-bit/16-bit Options
ACC2087 supports both 8-bit 16-bit data buses. configured pull-up pull-down resistor 139, ENMAX#, demonstrated below: 8-bit configuration 16-bit configuration
2.28
128K/64K BIOS Range
BIOS range different sizes 128K accommodate various application requirements. Refer Configuration Register definition configure size BIOS range. 2.29 Reset Shutdown Logic
reset shutdown logic contains circuitry RESET CPURDY# signals. Reset circuitry generates resets. general system reset with power other CPU. PWRGOOD signal generates system reset synchronized CPUCLK. When SWRESET# signal generated from integrated/external keyboard controller (called warm reset), CPURST activated reset CPU. CPURST asserted least sixteen CPUCLK cycles then deactivated proper operation.
Micro2.30 OS/2 Optimization
ACC2087 implements OS/2 optimization, which more efficient switch back forth between real protected modes OS/2 environment when frequent calls made. Conventional methods require processor communicate with integrated /external keyboard controller switching protected mode activating gate A20. With OS/2 optimization, ACC2087 allows control software reset gating through Port 92h. Configuration Register Port 92h, Fast Gate, Alternative RESET Control Function Reserved Fast Gate Fast reset
This controls address A20. When enables A20. When this makes Signal inactive, thus preventing Address from going beyond 0FFFFFh boundary Real Mode. much faster than Gate signal because just simple write operation. Default setting this application software reinitialize microprocessor switch operation from Protected Mode Real Mode. Setting this does reset whole system, only affects CPU. This reset function same that integrated/external keyboard controller's "KBRST" signal. However, provides faster reset sequence. This read application software determine rest cold boot. only writing register power Default
Micro2.31 Floppy Disk Drives
With ACC2087, designers build PC/XT compatible Floppy Disk Drive with fast access time, high reliability cost capability. ACC2087 integrates functions standard floppy disk drive controller. Data separator Write precompensation circuit Decode logic Data rate selection Clock generation Drive interface drivers receivers. This integration greatly reduces number components required interface floppy disk drives microprocessor system. ACC2087 supports floppy disk drives. compatible with System double density format (MFM), Sony EMCA format. ACC2087 contains decode logic internal registers, write logic read logic. system address decoder compatible with drive system. Handshaking signals provided make operation easy incorporate with external control chip. ACC2087 operates either Non-DMA modes. Non-DMA mode, ACC2087 generates interrupts processor each time data byte made available. mode, processor only needs load command into ACC2087 which will control data transfers. Data Separator ACC2087 minimizes read error rates high performance floppy disk drives. on-chip phase locked loop digital circuit adjusts clock used during data read keep phase with data signal. Write compensation included addition formatting, encoding/decoding, stepper motor control, status sensing functions. inputs compatible, outputs high current, open drain with direct drive interface. Using single crystal input, ACC2087's internal Clock Generation circuit provides timing signals sampling clock, write clock, master clock. generates handle standard data rates Kb/s support Kb/s data rate. ACC2087 executes following fifteen commands from microprocessor. Read Data Read Deleted Data Read Track Read Write Data Write Deleted Data Format Track Scan Equal
MicroScan Equal Scan High Equal Recalibrate Sense Interrupt Status Specify Sense Drive Status Seek Register Descriptions
There floppy disk controller registers ACC2087, three registers status signals used diskette operations, data register, controller registers. addresses these registers described tables below. Address Secondary Registers WRITE Digital output register Main status register Data register Digital input register Data register Diskette control register
Primary
READ Input Register
Input Register (HEX 3F0) Input Register general purpose input register. Function General purpose programmable General purpose programmable General purpose programmable General purpose programmable General purpose programmable General purpose programmable
MicroDigital Output Register (HEX 3F2) (8-bits) (W).
Digital Output Register controls drive motors, drive selection, feature enable. bits cleared reset line. Function Reserved. Motor Enable Motor Enable Interrupt Enable. Floppy Disk Controller reset. Drive Select Select drive Select drive Reserved. Reserved.
Main Status Register (HEX 3F4) main status register controls data flow between microprocessor controller. Function Request Master. Data Register ready transfer. Data Input/Output. Data transfer from controller; Data transfer from bus. Execution Mode (Non-DMA mode). Execution Controller Busy. Controller busy. Drive Busy. Diskette seek mode. Drive busy. Drive Busy. Diskette seek mode. Drive Busy. Drive Busy. Diskette seek mode. Drive Busy. Drive Busy. Diskette seek mode. Drive Busy.
Data Register (HEX 3F5) (R/W) Data Register consists four status registers stack. Only register presented data time. stores data, commands parameters, provides diskette/drive status information. Data bytes passed through data register program obtain results after command.
MicroStatus Register (ST0)
Function (Interrupt Code). Normal termination command. Abnormal termination command. Invalid command issue. Abnormal termination because ready signal from changed state during command execution. (seek end). Seek end. (Equipment Check). When fault signal received from FDD, track signals fails occur after step pulses; error. (Not Ready). Drive ready; Drive ready. (Head address). Head select; Head select. US1,US0 (Unit select). Drive select. Drive select. Drive select. Drive select.
Status Register (ST1) Function (End Cylinder). When tries access sector beyond final sector cylinder. used. This always (Data Error). When detects error either field data field. (Over Run). serviced host system during data transfer within certain time interval. used. This always Data). During execution Read, Write Verify Data specified sector cannot found. (Not Writable). "write Protect" signal detected from diskette drive during execution. Missing Address Mark. When cannot detect data address mark deleted data address mark.
MicroStatus Register (ST2)
Function used. Always (Control Mark). deleted data encountered during execution Read Data Scan command. (Data Error Data Field). detects error data field. (Wrong Cylinder). Wrong cylinder. (Scan Equal Hit). During execution Scan command, condition "equal" satisfied. (Scan Satisfy). During execution Scan command, cannot find sector. (Bad Cylinder). cylinder. (Missing Address mark Data Field). When data read from medium, cannot find data address mark deleted data address mark.
Status Register (ST3) Function Fault. Write Protected. Ready. Track Two-Side. Head Address. US1, Unit Select US0, Unit Select
Digital Input Register (HEX 3F7) Digital Input Register diagnostic purposes. Function Diskette Change (DSKCHG) Tri-State
MicroDiskette Control Register (HEX 3F7) Diskette Control Register sets precompensation. Function Reserved Transfer Rates Select Reduced Write Current Control Commands 500Kb/s 300Kb/s 250Kb/s Reserved RWC#=1 RWC#=0 RWC#=0 RWC#=0
diskette controller ACC2087 capable performing fifteen commands. Each command initiated multi-byte transfer from microprocessor. result also multi-byte transfer back microprocessor. Each command consists three phases: Command, Execution, Result. Command microprocessor issues required information controller perform specific operation. Execution controller performs specified operation. Result After completing operation, status information other housekeeping information made available microprocessor. Command Symbol Descriptions Address Line controls selection main status register (A0=0) data register (A0=1). Cylinder Number. Current selected cylinder (track), numbers through Data. Data pattern written into sector.
Data Bus. data bus, where stand most significant bit, stands least significant bit. Data Length. value this byte normally ignored controller. However byte must written this location. Track. final sector number cylinder.
Micro
Length. length During Read/Write commands this value determines number bytes that sync keeps after bytes. During Format command determines size Head Address. Head number specified field. Head. Selected head number (H=HD commands) Head Load Time. head load time selected increments.) Head Unload Time. Time after Read Write operation. increments). Must select mode. Multitrack. high, multitrack operation performed. MT=1 after finishing read/write operation side automatically starts searching sector side Number. number data bytes written sector.
Cylinder Number. cylinder number reached result seek operation; desired position head. Non-DMA Mode. Present Cylinder Number. Cylinder number completion Sense Interrupt Status command, current position head. Record. sector number read written. Read/Write. Either Read Write signal. Sector. Number sectors cylinder. Skip. Skip deleted data address mark. Stepping Rate. These bits indicate stepping rate increments). Stepping rate applies drives (FH=1ms, EH=2 etc.).
ST0-ST3 Status 0-Status four registers that store status information after command been executed. This information available during result phase after command execution. These registers must confused with main status register (selected A0=0). ST0-ST3 read only after command been executed only they contains information relevant command. Scan Test. STP=1 during scan operation, data contiguous sectors compared byte byte with data sent from processor DMA). STP=2, alternate sectors read compared.
US0-1 Unit Select. Selected drive number
MicroCommand Format following commands issued controller. indicates "don't care" condition. READ DATA Command Phase Cylinder Number Head Address Sector Number Number Data Bytes Sector Track Length Data Length
Byte Byte Byte Byte Byte Byte Byte Byte Byte Result Phase Byte Byte Byte Byte Byte Byte Byte
Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
MicroREAD DELETED DATA Command Phase Cylinder Number Head Address Sector Number Number Data Bytes Sector Track Length Data Length
Byte Byte Byte Byte Byte Byte Byte Byte Byte Result Phase Byte Byte Byte Byte Byte Byte Byte
Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
READ TRACK Command Phase Byte Byte Byte Byte Byte Byte Byte Byte Byte Cylinder Number Head Address Sector Number Number Data Bytes Sector Track Length Data Length
MicroResult Phase Byte Byte Byte Byte Byte Byte Byte READ Command Phase Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
Byte Byte Result Phase Byte Byte Byte Byte Byte Byte Byte
Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
WRITE DATA Command Phase Cylinder Number Head Address Sector Number Number Data Bytes Sector Track Length Data Length
Byte Byte Byte Byte Byte Byte Byte Byte Byte
MicroResult Phase Byte Byte Byte Byte Byte Byte Byte Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
WRITE DELETED DATA Command Phase Cylinder Number Head Address Sector Number Number Data Bytes Sector Track Length Data Length
Byte Byte Byte Byte Byte Byte Byte Byte Byte Result Phase Byte Byte Byte Byte Byte Byte Byte
Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
FORMAT TRACK Command Phase Number Data Bytes Sector Sectors Cylinder Length Data
Byte Byte Byte Byte Byte Byte
MicroResult Phase Byte Byte Byte Byte Byte Byte Byte Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
SCAN EQUAL Command Phase Cylinder Number Head Address Sector Number Number Data Bytes Sector Track Length Scan Test
Byte Byte Byte Byte Byte Byte Byte Byte Byte Result Phase Byte Byte Byte Byte Byte Byte Byte
Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
MicroSCAN EQUAL Command Phase Cylinder Number Head Address Sector Number Number Data Bytes Sector Track Length Scan Test
Byte Byte Byte Byte Byte Byte Byte Byte Byte Result Phase Byte Byte Byte Byte Byte Byte Byte
Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
SCAN HIGH EQUAL Command Phase Cylinder Number Head Address Sector Number Number Data Bytes Sector Track Length Scan Test
Byte Byte Byte Byte Byte Byte Byte Byte Byte
MicroResult Phase Byte Byte Byte Byte Byte Byte Byte Status Register Status Register Status Register Cylinder Number Head Address Sector Number Number Data Bytes Sector
RECALIBRATE Command Phase (This command result phase.)
Byte Byte
SENSE INTERRUPT STATUS Command Phase
Byte Result Phase Byte Byte Specify
Status Register Present Cylinder Number
Command Phase (This command result phase.)
Byte Byte Byte
SENSE DRIVE STATUS Command phase
Byte Byte
MicroResult Phase Byte SEEK Command Phase (This command result phase.) Cylinder Number Seek Status Register
Byte Byte Byte INVALID Result Phase
following status byte returned microprocessor when invalid command received. Byte Status Register
MicroFloppy Disk Drive Support Parallel Port
ACC2087 allows floppy disk control signals multiplex parallel port pins external floppy disk drive support. enable this function, Register BEh, enable this function. Table summarizes signals which multiplexed with parallel port pins.
Connector
mode HEAD# WDATA# MOIN# DSIN# RWC# DIR# STEP# INDEX# TRK0# RDDATA# DSKCHG#
Parallel Port Mode ERROR# SLCT BUSY ACK# AUTOFD# INIT# SLIN#
Parallel Port Connector
Micro2.32 Serial Port Interface
ACC2087 supports NS16C550 compatible serial ports. Each serial port interface converts data from peripheral devices modems from serial-in-data parallel-out-data. Data transmitted from converted from parallel-in-data serial-out-data. status UART read during operation. Status includes type condition transfer operations progress, error conditions. Each serial port interface three types internal registers: Control, Status, Data registers. Control registers Rate Select Register (Divisor Latch LSB). Rate Select Register (Divisor Latch MSB). Line Control Register. Interrupt Enable Register. Interrupt Identification Register. FIFO Control Register. Modem Control Register. Status registers Line Status Registers Modem Status Register Data registers Receiver Buffer Register Transmitter Holding Register Scratch Register Table summarizes serial port registers.
MicroTable
Register Receiver Buffer Register (read only) Transmitt-er Holding Register (write only) Divisor Latch (LS) Divisor Latch (MS) Interrupt Enable Register
Serial Port Register Summary
Data (MSB) Data Data Data Data Data Data Data (LSB)
Data
Data
Data
Data
Data
Data
Data
Data
Enable Modem Status Interrupt
Enable Receiver Line Status Interrupt Interrupt
Enable Transmitt-er Holding Register Interrupt Interrupt
Enable Received Data Available Interrupt Interrupt Pending Enable FIFO
Interrupt Identificatio Register (Read only) FIFO Control Register (Write only) Line Control Register Modem Control Register Line Status Register
FIFOs Enabled
FIFOs Enabled
RCVR Trigger (MSB) Divisor Latch Address
RCSV Trigger (LSB) Break
Reset FIFO XMIT
Reset FIFO RCVR
Stick Parity
Even Parity Select Loop
Parity Enable Interrupt Enable Framing Error
Number Stop Bits Used
Word Length Select Request Send Overrun Error
Error RCVCR FIFO Data Carrier Detect
Transmitter Empty
Modem Status Register Scratch Register
Ring Indicator
Transmitter Holding Register Empty Data Ready
Break Interrupt
Parity Error
Word Length Select Data Terminal Ready Data Ready
Clear Send
Delta Receive Line Signal Detect
Trailing Edge Ring Indicator
Delta Data Ready
Delta Clear Send
MicroProgrammable Baud Rate Generator
serial port interface ACC2087 contains programmable Baud Rate Generator that divides clock from MHz. divisor from 16-1 used. output frequency baud rate generator data rate [divisor clock (baud rate 16)]. divisor stored 16-bit binary format 8-bit divisor latch registers. These divisor latch registers must loaded during initialization. 16-bit baud counter immediately loaded after either divisor latches loaded prevent long counts initial load. serial port receiver circuitry ACC2087 programmable data bits character. Word with less than eight bits right justified, Data which first data received. Unused bits character less than eight bits output parallel output serial port. Data received SIN0(1) (serial input) shifted into Receiver Shift Register clock (16X) provided input. Based position start bit, this clock synchronized incoming data. When complete character shifted into Receiver Shift register, assembled data bits loaded parallel into Receiver Buffer Register (RBR). Data Ready flag Line Status register set. Transmitter Holding Register (THR) (HEX 2F8, DLAB Receiver Buffer Register (HEX 2F8, DLAB Transmitter Holding Register Receiver Buffer Register data registers that hold from five eight bits data. fewer than eight data bits transmitted, always first serial data received transmitted. Data registers buffered twice allow read write operations executed same time UART converting parallel serial serial parallel. data received buffered twice permit continuous data reception without loss data. Receiver Shift register shifting character into serial port, Receiver Buffer register holding previously received character CPU. data Receiver Buffer register read before complete reception next character, data Receiver register goes low. overrun condition flagged Overrun error (Bit Line Status register). Table contains Receiver Buffer Register definitions. Table Receiver Buffer Register Function Data Data Data Data Data Data Data Data
Transmitter Holding Register holds parallel data from data until Transmitter Shift register empty ready accept character. receiver word length transmitter number stop same. character less than eight bits, unused bits ignored transmitter microprocessor data bus. Table contains definitions Transmitter Holding register.
MicroTable Transmitter Holding Register Function Data Data Data Data Data Data Data Data
first serial data transmitted. Interrupt Enable Register (IER) (HEX 2F9, DALB R/W) Interrupt Enable Register write register that enables serial port interrupts independently. interrupts activate interrupt output. interrupts disabled resetting Bits this register. Interrupts enabled setting appropriate bits this register high. When interrupts disabled, Interrupt Identification register active (high) INTSE0(1) signal inhibited. other system functions operate normally, including setting Line Status register Modem Status register. Table contains Interrupt Enable register definitions. Table Interrupt Enable Register Function Received Data Available interrupt. enable; disable. Transmitter holding register empty interrupt. enable; disable. Receiver line status interrupt. enable; disable. Modem Status interrupt. enable; disable. Must logic
Interrupt Identification Register (IIR) (HEX 2FA, Interrupt Identification Register interrupt capability interface current microprocessors. serial port interface prioritizes interrupts into four levels minimize software overhead during data character transfer. four levels interrupt conditions include Priority Priority Priority Priority Receiver Line Status Received Data Ready Transmitter Holding Register Empty Modem Status
Interrupt Identification register stores information that interrupt pending type interrupt. When addressed during chip select time, this register indicates highest priority interrupt pending. other interrupts acknowledged until services this interrupt. Table contains Interrupt Identification register definitions. Table contains interrupt identification, reset information.
MicroTable Interrupt Identification Register
Function Indicates pending interrupt. When this low, interrupt pending register contents used pointer appropriate interrupt service routine. When this high, interrupt pending. Identifies highest priority pending must FIFO mode, this along with when time-out interrupt pending. Enable FIFO. These bits when FIFO Control Register one.
Table Interrupt Reset Interrupt Identification Bit2 Bit1 Priorit Interrupt Reset Functions Interrupt Interrupt Flag Source None Receiver line status Received data available None Received data available
Level
Interrupt Reset Control
Character Time-out
THRE
Atleast character FIFO characters have been read from input FIFO during last character times THRE
Read Read FIFO drops below trigger level Read
Modem status
CTS0#(1), DSR0#(1). RI0#(1), RLSD0#(1).
Read THRE interrupt source write Read
defined
MicroFIFO Control Register (HEX 2FA,
Function Enable FIFO. When enabled. Resetting this will cleared bytes both FIFOs. Reset FIFO Receiver. When clears bytes receiver FIFO. logic counter will reset Reset FIFO Transmitter. When clears bytes Transmitter FIFO. logic counter will reset Trigger Receiver (LSB). This used trigger level receiver FIFO. Trigger Receiver (MSB). This used trigger level receiver FIFO. FIFO Trigger Level (Bytes)
Address, Read, Write inputs used with Divisor Latch Access (DLAB) Line Control register [LCR(7)] select register read written. Refer Table register select states. Table DLAB Serial Port Internal Register Selection Register Receiver buffer register (read only) Transmitter holding register (write only) Interrupt enable register Interrupt identification register (read only) Line control register Modem control register Line status register Modem status register Scratch register Divisor latch (LSB) Divisor latch (MSB)
Don't care Note that serial port accessed only when internal chip select signal CSSE0#(1) low. Line Control Register (LCR) (HEX 2FB, R/W) Line Control Register controls format data character. contents read precluding need store line characteristics system memory. Table contains contents Line Control register.
MicroTable Line Control Register Function Word length select Word length select Stop select Parity enable Even parity select Stick parity break Divisor latch access Logic Logic
stop bits Enabled Even parity Enabled Enabled
stop Disabled parity Disabled Disabled
number bits each serial character programmed according following states. LCR(1) LCR(0) Word length bits bits bits bits
Specifies number stop bits each character transmitted. stop generated checked transmitted data. when 5-bit word selected, stop bits generated. when 8-bit word selected, stop bits generated. receiver checks first stop only regardless number stop bits selected. When high, generates checks parity between last data word stop serial data. When parity enabled (Bit parity selected. When parity enabled even parity selected. When parity enabled parity transmitted received opposite state from state indicated Parity therefore forced known state receiver check parity known state. When serial output forced spacing (logic state. break disabled when this acts only serial output effect transmitting logic. enables alert terminal computer system. following sequence used, erroneous extraneous characters transmitted because break. Load zeros, character, response Line Status register break response next Line Status register Wait transmitter become idle (Line Status register clear break when normal transmission must restored.
Micro
Must high access Divisor latches Baud rate generator during read write operation. This must input access Receiver buffer, Transmitter holding, Interrupt enable registers.
Modem Control Register (MCR) (HEX 2FC, R/W) Modem Control Register controls interface with modem data set. This register read written. Table contains Modem Control register definitions. Table Modem Control Register Function Data terminal ready (DTR). When Data terminal ready [DTR0#(1)] output forced logic When this reset logic DTR0#(1) output forced logic Request send (RTS). When Request send [RTS0#(1)] output forced logic When this reset logic RTS0#(1) output forced logic used. Interrupt enable. When high, Serial port interrupt (SIRQ3, SIRQ4) output enabled. Loopback.This provides local loopback feature perform diagnostic testing channel. When high, SOUT0(1) marking state (logic receiver data input Serial Input [SIN0(1)] disconnected. output Transmitter Shift register looped back into Receiver Shift register input. four modem control inputs disconnected. Modem control outputs connected four modem control inputs internally. Modem control output pins forced high (inactive state). diagnostic mode, data transmitted received immediately processor verify transmit receive data paths selected serial port.
Line Status Register (LSR) (HEX 2FD, W/R) Line Status Register usually first register read determine cause interrupt poll status serial port interface. Refer Table definitions. Table Line Status Register Function Data ready (DR) Overrun error (OE) Parity error (PE) Framing error (FE) Break interrupt (BI) Transmitter holding register empty (THRE) Transmitter empty (TEMT) used Logic Ready Error Error Error Break Empty Empty Logic ready error error error break empty empty
Micro
Bits error conditions that produce Receiver Line Status interrupt (priority interrupt Interrupt Identification register). This interrupt enabled setting Interrupt Enable register Bits cleared when Line Status register read. Bits three error flags that provide status error condition detected receiver circuitry: Overrun error, Framing error, Parity error. Error flags high error condition when stop bits received. This high when incoming character received transferred into Receiver Buffer register FIFO. will reset after reading data FIFO. Overrun error means that Receiver Buffer register read before next character transferred into Receiver Buffer register, overwriting previous character. This reset when reads contents Line Status register. parity error means that last character received parity error based programmed calculated parity received character (Line Control register framing error means that last character received incorrect (low) stop bits (caused when required stop absent stop short detected). This high when stop following last data parity detected zero (spacing level). This reset when reads contents Line Status register. This indicates that last character received break character. break character defined invalid complete data character, including parity stop bits. This high when received data input held spacing (logic state longer time than full word transmission time (start data bits parity stop bits). reset when reads contents Line Status register. This indicates that Transmitter Holding register empty receive another character. interrupt enabled (Interrupt Enable register this when active causes interrupt. interrupt cleared when Interrupt Identification register read. high when character transferred from Transmitter Holding register into Transmitter Shift register. This reset when loads Transmitter Holding register. reset when reads Line Status register. This high when Transmitter Holding register Transmitter Shift register both empty. When character loaded into Transmitter Holding register, this remains until character transferred SOUT0(1) (Serial output pin). reset when reads Line Status register. This always zero.
MicroModem Status Register (MSR) (HEX 2FE, R/W)
Modem Status Register provides with status modem input lines from modem peripheral devices. read serial port modem signal inputs accessing data interface ACC2087. Four bits this register indicate modem inputs have changed since last read Modem status register. These bits high when control input from modem changes state. When reads Modem Status register, these bits reset low. CTS0#(1), DSR0#(1), RI0#(1) RLSD0#(1) signals modem input lines channel. Bits through status indications these lines. modem status interrupt Interrupt Enable register enabled, change state modem input signals reflected modem status bits register interrupt generated. Modem Status register priority interrupt. Refer Table definitions. Note that state status inverted version actual input pin. Table Modem Status Register Function Delta clear send. Indicates that CTS0#(1) input serial port interface changed state since last time read CPU. Delta data ready. Indicates that DSR0#(1) input serial port interface changed state since last time read CPU. Trailing edge ring indicator. Indicates that RI0#(1) input serial port interface changed state since last time read CPU. high transitions activate this bit. Delta data carrier detect. Indicates that RLSD0#(1) input serial port interface changed state since last time read CPU. Clear send. This complement CTS0#(1) input from modem. This input tells serial port that modem ready receive data from transmitter output serial port. serial port interface loop mode (Modem Control register this equivalent Modem Control register (request send). Data ready. This complement DSR0#(1) input from modem serial port. This input tells that modem ready provide received data serial port receiver circuitry. channel loop mode (Modem Control register this equivalent Modem Control register (data terminal ready). Ring indicator. This complement RI0#(1) pin. channel loop mode (Modem Control register this connected Modem Control register. Data carrier detect. This complement receiver line detect signal input equivalent Modem control register
Modem status inputs reflect modem input lines with change status. Reading Modem Status register clears delta modem status indications does affect status bits. status bits reflect state input pins regardless mask control signals. bits true, state change occurs during read operation, state change reflected Modem Status register. bits false, state change indicated after read. Setting status bits inhibited Line Status register Modem Status register during status read operations. status condition generated during read, status until trailing edge read. status during read operation, same status condition occurs, that status cleared trailing edge read instead being again.
MicroScratch Register (SR) (HEX 2FF, R/W)
Scratch Register 8-bit Read/Write register. This register does affect either channel serial port. used programmers hold data temporarily. Table contains definitions. Table Scratch Register Function Data Data Data Data Data Data Data Data
Transmitting serial port interface transmitting function includes Transmitter Holding register, Transmitter Shift register, associated control logic. Bits Line Status Register indicate status Transmitter Holding register Transmitter Shift register. transmit 8-bit word, word written Transmitter Holding register through SD0-SD7. microprocessor performs write operation only transmitted. Line Status register high when word automatically transferred from Transmitter Holding register Transmitter Shift register when start transmitted. When transmitter idle, Bits Line Status register high. first word written causes reset zero. After transfer, return high. remains while data word transmitted. second character transmitted Transmitter Holding register, Line Status register reset low. Because data word cannot transferred from Transmitter Holding register Transmitter Shift register until empty, Line Status register remains until word completely transmitted. When last word transmitted Transmitter Shift register, Line Status register high. Line Status register high transfer time later. Receiving Serial asynchronous data input into SIN0(1) (Serial Input pin). idle state line providing input into high. Start detection circuitry continually searches high transition. When transition detected, counter reset. Count clock 1/2, which center start bit. signal still mid-bit sample start bit, start considered valid. verifying start bit, receiver prevented from assembling false data character caused going noise spike Serial Input pin. Line Control register determines number data bits character, number stop bits, parity used, polarity parity. Line Status register provides status receiver Receiver Buffer register. data received (indicated Line Status register) high. reads Receiver Buffer register through SD0-SD7. This read resets Line Status register. character read before character transfer from Receiver Status register Receiver Buffer register, overrun error status (Line Status register parity check looks even parity
Micro
parity which precedes first stop bit. parity error Line Status register error detected. stop high, framing error indicated Line Status register center start defined clock count 1/2. data received Serial Input symmetrical square wave, center data cells occurs within 3.125% mid-point. This 46.875% error margin. start begin much clock cycle before detected. Baud Rate Generator Baud Rate generator generates clocking UART function provides standard ANSI/CCITT rates. external clock into provides oscillator driving Baud Rate generator. Divisor Latch registers DLM, external frequency determine data rate. rate selected programming divisor latches. When divisor divides (provides maximum baud rate given input frequency input). Table shows baud rate 1.8432 Clock. Table Baud Rate 134.5 1200 1800 2000 2400 3600 4800 7200 9600 19200 38400 56000 Baud Rates 1.8432 Clock Divisor 2304 1536 1047
MicroResetting RESET# input must held reset serial port circuits idle mode until initialization. state RESET# signal causes following events. Initializes transmitter receiver internal clock counters.
Clears Line Status register except Bits which set. Also clears Modem Control register. discrete lines, memory elements logic associated with these registers also cleared turned off. Line Control register, Divisor latches, Receiver Buffer register Transmitter Buffer register affected.
After rest condition removed, serial port remains idle until programmed. hardware reset sets Bits Line Status register. When interrupts enabled, activates interrupt. Refer Table summary reset effects.
Table
Reset Summary Reset Control Reset Reset Reset Reset Reset Reset Reset Read LSR/Reset Read RBR/Reset Read IIR/Write THR/Reset Read MSR/Reset Reset Reset Reset bits (0-3 forced permanent) high, Bits Bits permanently bits bits Bits low, Bits high Bits low, Bits input signal High High High
Register/Signal Interrupt Enable Register Interrupt Identification Register Line Control Register Modem Control Register Line Status Register Modem Status Register Serial Output (SOUT) Interrupt (Receiver line status) Interrupt (Receiver data available) Interrupt (THRE) Interrupt (Modem Status) RTS# DTR#
Micro2.33 Parallel Port Interface
parallel port interface ACC2087 provides compatibility Centronics type printer. configuration register allows parallel port configured PS/2 type bi-directional parallel port Extended Capabilities Port (ECP) modes. Table lists registers associated with parallel port interface. address parallel port shown below: Data Port Status Port Control Port Base Address Base Address Base Address
microprocessor reads information parallel through Read Data register. read write functions register controlled state read (IOR#) write (IOW#). microprocessor reads status printer five most significant bits Read Status register. Table contains definitions this register. Table Register Read Data Read Status Read Control Write Data Write Control Table Parallel Port Interface Register Summary BUSY# ACK# SLCT IRQENB IRQENB ERROR# SLIN SLIN INIT# INIT# AUTOF AUTOF STROBE STROBE
Read Status Register Function Error Printer select Paper Empty Acknowledge Printer busy
Read Control Register reading state control lines. Write Control Register sets state control lines. Table contains definitions Write Control Register.
MicroTable Write Control Register Function Strobe inform printer presence valid byte parallel port Autofeed paper Initialize printer Select Interrupt enable Direction Must Must
Decoder parallel port address decoder selects registers according states signals listed Table Table Address Decoder Register Selection
Control Signals IOR# IOW#
CSPA#
Register Selected Read Data register Read Status register Read Control register Invalid Write Data register Invalid Write Control register Invalid
CSPA# internal signal parallel port logic.
MicroExtended Capability Port (ECP)
mode also supported ACC2087 with 16bytes FIFO. address register configuration shown below: Address Map: (Base Address 278h 378h) Data Port ECPAFIFO ECPCFIFO ECPDFIFO TFIFO CNFGA CNFGB Base Address 000h Base Address 000h Base Address 001h Base Address 002h Base Address 400h Base Address 400h Base Address 400h Base Address 400h Base Address 401h Base Address 402h
Register Configuration: ECPAFIFO FIFO Address (Mode 011) Description Write only. This used indicate data type. When bits [6:0] address. When field [6:0] length. used indicate many times next data will appeared. example: [6:0] time, [6:0] times, [6:0] times, etc. Write only. This address length encode (RLE) described above.
MicroDevice Status Register (Mode All) Description Read only. nBUSY. This indicates inverted version parallel port BUSY signal. Read only. nACK. This indicates version parallel port nACK signal. Read only. PERROR. This indicates version parallel port PERROR signal. Read only. SELECT. This indicates version parallel port SELECT signal. Read only. nFAULT. This indicates version parallel port nFAULT signal. Reserved.
Device Control Register (Mode All) Description Reserved. Read/Write. Direction. When data written peripheral. drivers enabled. When standard parallel port mode (mode 010), this effect. mode, drivers tri-stated sets direction that data will read from peripheral. Read/Write. When disables nACK interrupt. When enables interrupt rising edge nACK. Read/Write. When this effect. When forces SELECTIN signal regardless hardware state machine even mode. Software should make sure that prior entering mode. Read/Write. When this effect. When forces nINIT signal active regardless hardware state machine. Read/Write. When this effect. When forces AUTOFD signal regardless hardware state machine even mode. Software should make sure that prior entering mode. Read/Write. When this effect. When forces STROBE signal regardless hardware state machine even mode. Software should make sure that prior entering mode.
CFIFO Parallel Port Data FIFO (Mode 011) This mode only defined forward direction. hardware standard parallel port protocol used transmit bytes written DMAed, from system this FIFO, peripheral. Transfers FIFO bytes aligned. ECPDFIFO Data FIFO (Mode 011) When (Device Control Register) hardware parallel port protocol used transmit bytes written DMAed from system this FIFO, peripheral. Transfer FIFO bytes aligned. When data from peripheral read under automatic hardware handshake from into FIFO.
MicroTFIFO Test Mode (Mode 110) Data read, written DMAed from system this FIFO direction.
Data TFIFO will transmitted parallel port lines using hardware protocol handshake, However, data TFIFO displayed parallel port data lines. TFIFO will stall when overwritten underrun. Data will simply re-written over-run. full empty bits must always keep track correct FIFO state. TFIFO will transfer data maximum rate that software generated performance metrics. Data PWords always read from head TFIFO regardless value direction bit. FIFO size interrupt threshold determined writing PWords checking full service interrupt bits. CNFGA Configuration Resister (Mode 111) This read only register. CNFGB Configuration Register (Mode 111) Description Reserved. Always Read only. value interrupt line determines possible conflicts. Default Reserved. Always
Extended Control Register Description Read/Write. When 000, standard parallel port mode selected. this mode FIFO reset common collector drivers used control lines. Setting direction will tri-state output drivers this mode. When 001, PS/2 parallel port mode selected. This same standard parallel mode except that direction used tri-state data lines reading data register returns value data lines value data register. When 010, parallel port FIFO mode selected. This same standard parallel port mode except that PWords written DMAed FIFO. FIFO data automatically transmitted using standard parallel port protocol. Note that this mode only useful when direction drivers have active pull-ups. When 011, parallel port mode selected. forward direction PWords placed into ECPDFIFO bytes written ECPAFIFO placed single FIFO transmitted automatically peripheral using protocol. reverse direction bytes moved from parallel port packed into PWords ECPDFIFO. When 110, test mode selected. When 111, configuration register accessible 0x400 0x401. When 100, reserved.
MicroSection 2087 Description
Table Clock Interface Name CLKSRC SYSCLK Type Description System clock source. input clock from CMOS oscillator clock chip. Peripheral clock. This clock derived from either X14M CLKSRC provide system clock source Bus. System input clock. input clock buffer from either CLKX1 CLKX2 feedback CLKI. 14.318 crystal input. CLKX1 CLKSRC divided CLKX2 CLKSRC divided
CLKI
X14M CLKX1 CLKX2
Table Reset Interface Name PWRGD CPURST RESETDRV Type Description "Power Good" signal from power supply. must stabled least 1ms. reset output. System reset. Active high. This reset signal devices reset initialize system logic upon power-up during line voltage. This signal deasserted phase
MicroTable Interface Name ADS# M/-IO D/-C W/-R RDY# BRDY# HITM# FLUSH# EADS# Type
Description ADS# driven directly ADS# pin. asserted cycle. When high, indicates current cycle memory access cycle. cycle when low. indicates whether current cycle data control cycle. indicates whether current cycle read write cycle. This ready signal CPU. becomes input local cycle. indicates data (read/write) cycle ready. Asserted indicate snoop cycle modified line needs written back. When this pulled during power indicates valid external address been driven onto processor address pins used inquire cycle. this pulled high during power becomes slot signal through transceiver. used force mask real mode applications. hold request. This cache output enable signal /KTOEN.
LA20 GA20 PHOLD /KTGOE
MicroTable Interface contd. Name HLDA KEN# SMIACT# SMIADS# SMI# STPCLK# SUSPACK# A2-A25, 59-68 72,73 78-90 153-162 164-169 94-97 Type
Description indicates that granted control response PHOLD. indicates that current cycle cacheable. indicates that system management mode after SMI# being served CPU. used invoke system management mode (SMM). indicates request stop clock power management control. This suspend acknowledge signal used support Cyrix CPU. These input during cycles. These become output during cache cycle. data bus. These used indicate which byte lanes cycle accessing Non-Maskable Interrupt. connects CPU. Interrupt indicates valid interrupt request asserted. Numeric Coprocessor Error. indicates coprocessor error. Ignore Error. indicates last transfer multiple transfer cycle. indicates that requests 16-bit data transfer (not 32-bit transfer). This multifunction pin, when Register one, this becomes /LBA sense existence local peripherals When zero, this Coprocessor Ready input 2087.
D0-15 BE#[3:0] INTR NPERR IGNNE# CPUBZY# BLAST# NPEREQ BS16# /READYO /LBA
MicroTable Power Management Cache DRAM Multiplex Interface Name PWRCNTL0 KWEB PWRCNTL1 KOEB PWRCNTL2 MDLATCH PWRCNTL3 DAC2 PWRCNTL4 DRQ1 PWRCNTL5 DRQ3 PWRCNTL6 DRQ6 PWRCNTL7 DRQ7 ACPWR PAR0 ALARM PAR1 LBAT1# PAR2 Type
Description notebook mode, this power control pin. desktop mode, this becomes cache write enable bank notebook mode, this power control pin. desktop mode, this becomes cache output enable bank notebook mode, this power control pin. desktop mode, this becomes latch support posted write function. notebook mode, this power control pin. desktop mode, this becomes DAC2. notebook mode, this power control pin. desktop mode, this becomes request notebook mode, this power control pin. desktop mode, this becomes request notebook mode, this power control pin. desktop mode, this becomes request notebook mode, this power control pin. desktop mode, this becomes request notebook mode, this power input. ACPWR active high pin. desktop mode, this becomes parity check notebook mode, this alarm input. ALARM active high pin. desktop mode, this becomes parity check notebook mode, this battery input. LBAT# active pin. desktop mode, this becomes parity check
MicroTable Power Management Cache DRAM Multiplex Interface contd. EXTSYS# PAR3 EXTSMI1 IOCHK STPGNT# IRQ13 SUSPMOD# IRQ15 DACK0 DAC0 DACK5 DAC1
notebook mode, this external system event. EXTSYS# active pin. desktop mode, this becomes parity check notebook mode, this external signal. EXTSMI1 high edge triggered. desktop mode, this becomes check signal. notebook mode, this output zero grant cycle. desktop mode, this becomes interrupt notebook mode, this indicates that system enters suspend mode. desktop mode, this becomes interrupt notebook mode, this acknowledge desktop mode, this becomes DAC0. notebook mode, this acknowledge desktop mode, this becomes DAC1.
Note: DAC1-DAC2 strapping condition during power-on will ACC2087 either desktop notebook mode. PIN# DESKTOP MODE DAC2 DAC1 PAR0 PAR1 PAR2 PAR3 KWEA KOEA KWEB KOEB MDLATCH IRQ13 IRQ15 DAC0 DAC1 DAC2 DRQ1 DRQ3 DRQ6 DRQ7 IOCHK NOTEBOOK MODE1 DAC2 DAC1 ACPWR ALARM BATLOW EXTSYS PWRCNTL0 PWRCNTL1 PWRCNTL2 STPGNT SUSPEND DACK0 DACK5 PWRCNTL3 PWRCNTL4 PWRCNTL5 PWRCNTL6 PWRCNTL7 EXTSMI1 NOTEBOOK MODE2 DAC2 DAC1 ACPWR ALARM BATLOW EXTSYS PWRCNTL0 PWRCNTL1 PWRCNTL2 STPGNT SUSPEND DAC0 DAC1 DAC2 DRQ1 DRQ3 DRQ6 DRQ7 IOCHK
Table Dedicated Power Management Interface Name EXTSMI0 SRBTN# Type Description This indicates external input. EXTSMI0 high edge triggered. This suspend/resume input button. high edge triggered.
MicroTable Dedicated Cache Interface Name DTYWE# KTGWE# KRMOE# KRMWE# TGLA2 TGLA3 TAG0 ROMCS# TAG1 CS8042# TAG2 RTCDS# TAG3 RTCWR# TAG4 HCS0# TAG5 HCS1# TAG6 IENH# TAG7 IENL# TAG8
WRPWRCLT1#
Type
TAG9 RDIDX21# MA10 DIRTY
Description This used dirty write back enable write enable level write back cache implementation. This indicates cache output enable SRAM. Active low. This indicates cache write enable. Active low. This toggles Address This toggle Address This multiplexed pin. cache cycle this When memory cycle, this DRAM Address When cycle, this output enable. This multiplexed pin. cache cycle this When memory cycle, this DRAM Address When cycle, this keyboard chip select. This multiplexed pin. cache cycle this When memory cycle, this DRAM Address When cycle, this Real Time Clock This multiplexed pin. cache cycle this When memory cycle, this DRAM Address When cycle, this Real Time Clock This multiplexed pin. cache cycle this This DRAM Address cycles, HCS0# active addresses 1F0h-1F7h 170h-177h. This multiplexed pin. cache cycle this This DRAM Address cycles, HCS1# active addresses 3F6h-3F7h 376h-377h. This multiplexed pin. cache cycle this DRAM cycles, this DRAM Address cycles, this Transceiver High Byte Enable. This multiplexed pin. cache cycle this DRAM cycles, this DRAM Address cycles, this Transceiver Byte Enable. This multiplexed pin. cache cycle this DRAM cycle this DRAM Address cycle, this will asserted when configuration register written. This multiplexed pin. cache cycle this DRAM cycle this DRAM Address cycle, this will asserted when configuration register with index read. This multiplexed pin. This DRAM Address cache cycles, this becomes dirty Write Back Cache indicate whether data SRAM clean not.
MicroTable DRAM Interface Name RAS0#RAS3# CAS0#CAS3# WEN# MDIR# 119,120 122,124 115-118 Type Description DRAM address strobe DRAM Banks 0-3.
DRAM column address strobe. These signals each byte shared banks. This indicates DRAM write enable. This used direction control posted write operation.
Table Interface Name IRQ5 IRQ7 RTCINT# IRQ9-11 IRQ14 DRQ0 DRQ5 SA0, SBHE# 222-224 132,133 Type Description Interrupt request from expansion bus. Active high. Interrupt request from expansion bus. Active high. Interrupt from RTC. Interrupt request from expansion bus. Active high. Interrupt request from expansion bus. Active high. Request line. Active high. Request line. Active high. System Address Bit. SA0-SA1 least significant bits address. System High Byte Enable. Active low. When HLDA inactive, SBHE# will output which decoded from byte enable signals BE#0-3 from CPU. When HLDA active, SBHE# will output mode input Master mode. Master mode, used decode byte enable signal. Address latch enable. Memory Read command. Active low. When HLDA inactive, MEMR# will output pin, activated only when current cycle memory read cycle that referenced local DRAM. When HLDA active, MEMR# will output mode will input master mode driven master. Moreover, aligned 16-bit memory transfer with 8-bit device, MEMR# will activated twice before current cycle.
BALE MEMR#
MicroTable Interface contd. Name MEMW# Type
IOR#
IOW#
SMEMR#
SMEMW#
MEMCS16#
ZWS#
IOCS16#
Description Memory Write Command. Active low. When HLDA inactive, MEMW# will output pin, activated only when current cycle memory write cycle that referenced local DRAM. When HLDA active, MEMW# will output mode will input master mode driven master. Moreover, aligned 16-bit memory transfer with 8-bit device, MEMW# will activated twice before current cycle. read strobe. Read Command. Active low. When HLDA inactive, IOR# acts output signal active read cycle. When HLDA active, IOR# will output mode will input master mode driven master. write strobe. Write Command. Active low. When HLDA inactive, IOW# acts output signal active write cycle. When HLDA active, IOW# will output mode will input master mode driven master. System Memory Read Command. Active low. SMEMR# active current cycle memory read cycle with address location below first megabyte. SMEMR# derived from MEMR# tristated when accessed above location. needs external pull high resistor. System Memory Write Command. Active low. SMEMW# active current cycle memory write cycle with address location below first megabyte. SMEMW# derived from MEMW# tristated when accessed above location. needs external pull high resistor. input indicate memory 16-bit chip select. master cycle, output local function enabled otherwise. Zero wait state. Active low. This signal driven when device wants complete cycle zero wait state. normal mode, input indicate 16-bit chip select. master cycle, output local function enabled otherwise.
MicroTable Interface contd. Name IOCHRDY Type
REF#
MASTER#
SPEAKER RTCAS ENMAX# ROM8 XDIR# SD0-15
SDDIR#
175-182 184,185 187-192
Description channel Ready from Expansion bus. Active high. IOCHRDY used slow device extend access cycle time. 2087 will sample IOCHRDY MHz. sample data will insert wait state into current cycle. Note that current cycle aligned 16-bit data transfer with 8-bit device, cycle will split into subcycles each which needs sample high state IOCHRDY before terminating subcycle. After second sample high state IOCHRDY, whole cycle will also terminated. master cycle, output. hold acknowledge. When asserted, devices ignore address allow transfers take place. Active high. Refresh Cycle. Active Low. This signal goes slot indicate that refresh cycle ongoing. slot memory this refresh. Master Input. Active low. MASTER# indicates 2087 that current cycle controlled master from expansion slot. Output drive speaker. When high, indicates terminal count channel reached. Address strobe 146818 Real Time Clock. Falling edge causes address latched 146818. enable. This also selects power pulled high pulled ROM. This direction control. System data bus.
This transceiver direction control D16-D21 SD0-SD15.
MicroTable Keyboard/Mouse Interface Name Type ENSDL# ENKBD ENSDH# M486 KBCLK KBRST# KBDATA KGA20 MSCLK KBINT MSDATA IRQ12
Description This enables transceiver SD0-SD7 D16-D23. When pulled this enables internal keyboard when pulled down, this disables internal keyboard. This enables transceiver SD8-SD15 D24-D31. When pulled high, this mode select when pulled low, this mode select. When internal keyboard enabled, works keyboard controller clock pin. Otherwise works keyboard reset input. When internal keyboard enabled, works keyboard data pin. Otherwise works keyboard GA20 input. When internal keyboard enabled, works mouse clock keyboard interrupt generated internal keyboard controller. Otherwise works keyboard interrupt input. When internal keyboard enabled, works mouse data mouse interrupt IRQ2 generated internal keyboard controller. Otherwise works IRQ12 input.
Table 3-10 Interface Name X24M MO0# DRQ2# MO1# DACK2# IRQ6 ENFDC FDCWE# FDCDIR# HEAD# WRDATA# STEP# INDEX# TRK0#
Type
Description 24MHz input FDC. When internal floppy disk enabled, MOTOR output DRQ2 generated internal FDC. Otherwise DRQ2 input. (open drain) 24mA. When internal floppy disk enabled, MOTOR output DACK2# generated internal FDC. Otherwise DACK2# output. (Open drain) 24mA. When internal floppy disk enable, works disk select output IRQ6 generated internal FDC. Otherwise works IRQ6 input. Open drain (24mA) Pull high enable internal floppy disk controller. Disk select output. 24mA open drain. Write Enable. When causes write operation floppy disk drive. open drain output. 24ma. Direction head stepper motor. open drain output. Logic outward motion. Logic inward motion. 24ma. Head select. Open drain output. Determines which disk drive head active. Logic Side Logic Side 24ma. Write Data. Logic open drain. Writes precompensated serial data selected FDD. open drain output. 24ma. STEP# output pulses. Active open drain output. Produces pulse programmable rate move head another cylinder. 24ma. Active Schmitt input from disk drive. Senses head positioning over beginning track marked index hole. Schmitt trigger. Track Active Schmitt input from disk drive. Signals that head positioned over outermost track. Schmitt trigger.
MicroTable 3-10 Interface contd. Name Type
Description
RDDATA# DSKCHG#
RWC#
Write Protected. Active Schmitt input from disk drive indicates that diskette write protected. Schmitt trigger. Read data input. Signals read from microprocessor. Schmitt trigger. Diskette change. This signal active power-on when diskette removed. remains active until STEP# pulse received with diskette place. Reduced write current. 24ma. 500KB 250, 300KB
Table 3-11 COM1 Interface Name IRQ4 ENCOM1 DTR1# RTS1# CTS1# DSR1# DCD1# RI1# Type Description Pull high enable internal COM1 otherwise will disable internal COM1. When enable, works serial data IRQ4 generated internal COM1. Otherwise works IRQ4 input. Data Terminal Ready. 4ma. Request Send. 4ma. Serial Data Clear Send. Data Ready. Data Carrier Detected. Ring Indicator.
Table 3-12 COM2 Interface Name IRQ3 ENCOM2 DTR2# ENLPT RTS2# ENIDE CTS2# DSR2# DCD2# RI2# Type Description Pull high enable internal COM2. Serial data IRQ3 generated internal COM2. Otherwise works IRQ3 input. Pull high enable parallel port. Data Terminal Ready. Pull high enable internal IDE. Otherwise works Request Send. 4ma. Serial Data Clear Send. Data Ready. Data Carrier Detected. Ring Indicator.
MicroTable 3-13 LPT1 Interface Name STB# ATFD# INIT# SLIN# LPTERR# LPTBZY SLCT LPTACK# PD0-PD7 18-21 237, 239-241 Type Description Data Parallel port Strobe. Parallel port Autofeed. Parallel port Initialize. Parallel port Select. Parallel port Error. Parallel port Busy. Parallel port Selected. Parallel port Paper. Parallel port Acknowledge Signal from printer Parallel port data bus.
Micro
2087 Numerical List
Name
RDDATA# RWC# STEP# FDCWE# FDCIR# X24M HEAD# R12# DTR2# RTS2# CTS2# DSR2# DCD2# DCD1# DSR1# CTS1# LPTBZY SLCT LPTACK# LPTERR# CPURST ENABUS# SYSCLK PHOLD KEN# RDY# DTYWE# CPUBZY# INTR M/-IO D/-C W/-R BRDY# TGLA2 TGLA3 CLKI CLKX2 CLKX1 PWRCTL2 MDIR# KRMOE# KRMWE# PWRCTL1 PWRCTL0 KTGOE#
Name
CLKSRC ADS# NPERR NPEREQ PWRGD GA20 HITM# BE0# BE1# BE2# BE3# LA20 WEN# MA0, TAG0 MA1, TAG1 MA2,TAG2 MA3, TAG3 MA4, TAG4 MA5, TAG5 MA6, TAG6 MA7, TAG7 MA8, TAG8 TMA9, TAG9 DIRTY CAS0# CAS1# CAS2# CAS3# RAS0# RAS1#
Name
RAS2# RAS3# STPCLK# SMI# LBA# HLDA MASTER# EXTSMI1 IOCHRDY SMIACT# IOCS16# MEMCS16# EXTSMI0 SRBTN# ZWS# X14M MSDATA MSCLK KBDATA KBCLK ENMAX# DAC0 DAC1 PWRCNTL3 ACPWR ALARM ENSDL# ENSDH# LBAT# EXTSYS#
Name
SD10 SD11 SD12 SD13 SD14 SD15 SDDIR# XDIR# IOR# IOW# BALE DRQ0 PWRCTL4 PWRCTL5 DRQ5 PWRCTL6 PWRCTL7 SBHE# MEMR# MEMW# RESETDRV REF# SMEMR# SMEMW# RTCAS IRQ5 IRQ7 RTCINT# IRQ9 IRQ10 IRQ11 STPGNT# IRQ14 SUSPMOD# SUSPACK# SPEAKER SLIN# STB# ATFD# INIT#
Micro2087 Numerical List contd.
Name RTS1# DTR1# Name RI1# Name MO0# MO1# WRDATA#
Name DSKCHG# TRK0# INDEX#
Note:
2087 Desktop Notebook Multiplexed Summary
Notebook Mode During power pull-down DAC0 pull-up DAC1 will configure ACC2086 notebook mode. Desktop Mode During power pull-down both DAC0 DAC1 will configure ACC2086 desktop mode. DAC0 DAC1 PAR0 PAR2 PAR3 EVEN EVEN EVEN LATCH IRQ13 IRQ15 DAC0 DAC1 DAC2 DRQ1 DRQ3 DRQ6 DRQ7 DAC0 DAC1 POWER PWRCTL0 PWRCTL1 PWRCTL2 STOP SUSPEND DACK0 DACK5 PWRCTL3 PWRCTL4 PWRCTL5 PWRCTL6 PWRCTL7 EXTSMI1
2087 Pins Status Various Types
Note: 2087 supports level write back write through microprocessors. (KTGOE) Pull down Pull down Pull Pull (ENMAX#) Pull down Pull Pull down Pull Type P24D (Misc.) other write back Regular Regular
Micro
2087 Numerical List with Multiplexed pins Power Plane Summary
Voltage
Name
RDDATA# RWC# STEP# FDCWE# FDCIR# X24M HEAD# R12# TX2, IRQ3, ENCOM2 DTR2#, ENLPT RTS2#, ENIDE CTS2# DSR2# DCD2# DCD1# DSR1# CTS1# LPTBZY SLCT LPTACK# LPTERR# CPURST
Voltage
Name
CLKSRC ADS# NPERR NPEREQ, BLAST# PWRGD
Voltage
Name
RAS2# RAS3# STPCLK# SMI# LBA#, READY0# HLDA MASTER# EXTSMI1, IOCHK IOCHRDY SMIACT#, SMIADS# IOCS16# MEMCS16# EXTSMI0 SRBTN# ZWS# X14M MSDATA, IRQ12 MSCLK, KBINT KBDATA, KGA20 KBCLK, KBRST# ENMAX# DAC0, DACK0 DAC1, DACK5 PWRCNTL3, DAC2
Micro2087 Numerical List with Multiplexed pins Power Plane Summary contd.
Voltage
Name
ENABUS# SYSCLK PHOLD KEN# RDY# DTYWE#, KTWE# CPUBZY#, IGNNE# INTR M/-IO D/-C W/-R BRDY#, CPUPEREQ TGLA2 TGLA3 CLKI CLKX2 CLKX1 PWRCTL2, MDLATCH MDIR# KRMOE# KRMWE# PWRCTL1, KOEB PWRCTL0, KWEB KTGOE#
Voltage
Name
GA20 HITM#, FLUSH# BE0# BE1# BE2# BE3# LA20, EADS# WEN# MA0, TAG0, ROMCS# MA1, TAG1, CS8042# MA2,TAG2, RTCDS# MA3, TAG3, RTCWR# MA4, TAG4, HCS0# MA5, TAG5, HCS1# MA6, TAG6, IENH# MA7, TAG7, IENL# MA8, TAG8 MA9, TAG9 RDIDX21# DIRTY, MA10 CAS0# CAS1# CAS2# CAS3# RAS0# RAS1#
Voltage
Name
ACPWR, PAR0 ALARM, PAR1 ENSDL#, ENKBD ENSDH#, M486 LBAT#, PAR2 EXTSYS#, PAR3
Micro2087 Numerical List with Multiplexed pins Power Plane Summary contd.
Voltage
Name
SD10 SD11 SD12 SD13 SD14 SD15 SDDIR# XDIR# IOR# IOW# BALE DRQ0 PWRCTL4, DRQ1 PWRCTL5, DRQ3 DRQ5
Voltage
Name
PWRCTL6, DRQ6 PWRCTL7, DRQ7 SBHE# MEMR# MEMW# RESETDRV REF# SMEMR# SMEMW# RTCAS IRQ5 IRQ7 RTCINT# IRQ9 IRQ10 IRQ11 STPGNT#, IRQ13 IRQ14 SUSPMOD#, IRQ15 SUSPACK# SPEAKER
Voltage
Name
SLIN# STB# ATFD# INIT# RTS1# DTR1# TX1, IRQ4, ENCOM1 RI1# DS0, IRQ6 DS1, ENFDC MO0#, DRQ2# MO1#, DACK2 WRDATA# DSKCHG# TRK0# INDEX#
MicroSection ACC2087 Register Settings
configuration registers ACC2087 programmed with indirect addressing scheme using adddresses address contains write/read configuration index register. selects corresponding configuration register accessed address write value "E8" into configuration register 2Ah, configuration index register address must first written with value "2a," then register address with value :E8." reserved unused bits should written zero unless otherwise indicated (don't care). Memory Configuration Setup Register
Default
Function When this enables remap memory within range memory address above actual installed memory size. When zero BIOS will located 0F0000-0FFFFF. When BIOS will extended from 0E0000-0FFFFF. When zero BIOS will located 0F0000-0FFFFF. When BIOS will extended from 0E0000-0FFFFF. When this enables include C0000-C7FFF video BIOS. These bits memory configuration bits 3-0. These four bits plus bits Register 12h, memory option. Refer following table memory options.
Memory Options Option Memory Configuration 543210 000000 000100 000111 001001 010000 010001 010010 010011 010100 010101 010110 010111 011000 011001 100000 100001 100010 100011 Bank Bank Bank Bank Total Memory
256K 256K 256K 256K 256K 256K 256K 256K 256K 256K
256K 256K 256K 256K 256K 256K
256K 256K
256K
256K
MicroMemory Options continued. Option Memory Bank Bank Bank Configuration 543210 100100 100101 100110 100111 101000 101001 110000 512K 110001 512K 512K 110010 512K 512K 512K 110011 512K 512K 512K 110100 512K 110101 512K 512K 110110 512K 512K 110111 512K 111000 512K 512K 111001 512K 512K 000010 256K 256K 000110 256K 256K 000001 256K 111100 111101 111110 111111 Memory configuration bits located Register 12h, bits Dram Setup Register
Default
Bank
Total Memory
512K
Function Reserved. When this disables time out. When zero this enables time out. Reserved.
Shadow Setup Register
Default
Function This must one. When this enables shadow area cacheable. When this places shadow segment into read only, write protect mode. When this enables shadow segment F0000-FFFFF. When this enables shadow segment E0000-EFFFF. When this enables shadow segment D0000-DFFFF. When this enables shadow segment C8000-CFFFF. When this enables shadow segment C0000-C7FFF.
MicroDRAM, Coprocessor Parity Setup Register
Default
Function Reserved. When this enables before refresh. Reserved. When this disables parity check. When numeric processor operates wait state. When zero numeric processor operates wait states. When this disables numeric processor's sequencer. When this disables access Weitek 3167 coprocessor. access Weitek will become cycles. When this disables access processor. access will become cycles.
Cache Setup Register
Default
Function When this enables post write. When this enables memory write wait with cache operation page cycle. When zero this enables memory write wait with cache operation page cycle. When this enables cache read wait state. When zero this enables cache read zero wait state. When this enables DRAM read burst mode. When this enables cache read burst mode update internal cache. These bits cache line size follows: Line Size When this enables 2087 cache controller.
Power Select Slow Refresh Register
Default
Function This read only bit. When read one, this indicates 8-bit installed. When read zero, this indicates 16-bit installed. This read only bit. When read one, indicates mode selected. When read zero, indicates mode selected. This read only bit. When read zero indicates Level write through CPU. When read indicates Lever write back CPU. Reserved. When this enables read from instead
MicroPower Select Slow Refresh Register
Default
Function Reserved. Bits select slow refresh divisor (Read/Write) follows: Bits Divided (Default) These bits must one.
Clock Source Select Register
Default
Function When Reg. these bits select divisor from CLKSRC digital delay time. Bits Clock Source (Default) Select clock source clock. 2087 supports three clock sources clock. SYSCLK half clock. When zero (default), SYSCLK derived from X14M1 (14.318 MHz). When bits one, SYSCLK derived from X24M MHz). When zero, CLKSRC provides clock source. addition, bits divisor divide down CLKSRC SYSCLK. Bits 4321 clock source 0XXXX X14M1, default. 11XXX X24M 10000 CLKSRC/5 10001 CLKSRC/3 10010 CLKSRC/2.5 10011 CLKSRC/1.5 10100 CLKSRC/1 10101 CLKSRC/4 10110 CLKSRC/1 10111 CLKSRC/2
MicroSleep Mode Control Register
Default
Function Reserved. When this enables sleep mode. sleep mode enabled, system clock source will switched from CLKSRC clock which divided down sleep mode frequency. These bits select divisor divide clock source sleep mode clock. Bits Divisor Sleep Mode Clock (Default)16 0.25MHz 0.125
Non-cacheable range DRAM setup Register
Default
Function Reserved. When this memory). Reserved.
Non-cacheable range default address>32Mb address>16Mb address>8Mb address>4Mb
enables 512K base memory. Default zero (640K base
High Address Register
Default
Function When this will convert ROMOE ROMCS flash EPROM support. When this EADS# synchronized with clock activated only Clock period Level write through CPU. When zero this disables (KEN always deasserted) normal operation. Reserved. zero Reserved. Must one.
MicroHigh Address Register
Default
Function When latches will held until last half clock increase hold time. When this enables address cycle. When this enables address cycle.
Page Mode Setup Register
Default
Function precharge time. Bits precharge time When this delay cycles write cycle. When zero delay time cycles When this precharge time cycles write cycles. When zero precharge time cycle. These bits define width read cycle time. Bits width read cycle These bits define width write cycle. Bits width write cycle
Non-cacheable Range (Registers 0Ch-11h) Non-cacheable block Register
Default
Function When this enables non-cacheable block address A17. When this enables non-cacheable block address A16. When this enables non-cacheable block address A15.
MicroNon-cacheable block Register
Default
Function When this enables non-cacheable block address A14. These bits enable non-cacheable block size follows: Non-cacheable Block size select Bits Addr. Non-cacheable compared block size cacheable (default) 128K 256K 512K disable cache
3210 0000 don't care 0001 14-25 0010 15-25 0011 16-25 0100 17-25 0101 18-25 0110 19-25 0111 20-25 1000 21-25 1001 22-25 1010 23-25 1011 24-25 1100 1101 1111 Non-cacheable block Register
Default
Function When this enables non-cacheable block 1address A25. When this enables non-cacheable block address A24. When this enables non-cacheable block address A23. When this enables non-cacheable block address A22. When this enables non-cacheable block address A21. When this enables non-cacheable block address A20. When this enables non-cacheable block address A19. When this enables non-cacheable block address A18.
Non-cacheable block Register
Default
Function When this enables non-cacheable block address A17. When this enables non-cacheable block address A16. When this enables non-cacheable block address A15.
MicroNon-cacheable block Register
Default
Function When this enables non-cacheable block address A14. These bits non-cacheable block size follows: Non-cacheable Block size select Bits Addr. Non-cacheable compared block size cacheable (default) 128K 256K 512K disable cache
3210 0000 don't care 0001 14-25 0010 15-25 0011 16-25 0100 17-25 0101 18-25 0110 19-25 0111 20-25 1000 21-25 1001 22-25 1010 23-25 1011 24-25 1100 1101 1111 Non-cacheable block Register
Default
Function When this enables non-cacheable block address A25. When this enables non-cacheable block address A24. When this enables non-cacheable block address A23. When this enables non-cacheable block address A22. When this enables non-cacheable block address A21. When this enables non-cacheable block address A20. When this enables non-cacheable block address A19. When this enables non-cacheable block address A18.
MicroNon-cacheable block Register
Default
Function When this enables non-cacheable block address A17. When this enables non-cacheable block address A16. When this enables non-cacheable block address A15. When this enables non-cacheable block address A14. These bits non-cacheable block size. Non-cacheable Block size select Bits Addr. compared Non-cacheable block size cacheable (default) 128K 256K 512K disable cache
3210 0000 don't care 0001 14-25 0010 15-25 0011 16-25 0100 17-25 0101 18-25 0110 19-25 0111 20-25 1000 21-25 1001 22-25 1010 23-25 1011 24-25 1100 1101 1111
MicroNon-cacheable block Register
Default
Function When this enables non-cacheable block address A25. When this enables non-cacheable block address A24. When this enables non-cacheable block address A23. When this enables non-cacheable block address A22. When this enables non-cacheable block address A21. When this enables non-cacheable block address A20. When this enables non-cacheable block address A19. When this enables non-cacheable block address A18.
DRAM, Size, Turbo Control Register
Default
Function When delay time cycles read cycles. When zero delay time cycles. When precharge time cycles read cycle. This conjunction with Register sets size middle BIOS. Reg. Reg. Middle size Disable (default) (FF0000 FFFFFF) 256K (FC0000-FFFFFF) 512K (F80000-FFFFFF) When this enables Turbo (pin switch operation speed between Turbo clock (CLKSRC) Sleep mode clock (defined Register bits 2-0). When zero Turbo will toggle operation speed between Turbo clock (CLKSRC) Normal clock. Reserved. When this enables 4Mx4 DRAM supported option. These bits memory configuration bits Refer memory configuration table Register
DRAM Bank Relocate Control Register
Default
Function SELBNK31 SELBNK30 SELBNK21 SELBNK20 SELBNK11 SELBNK10
MicroDRAM Bank Relocate Control Register
Default
Function SELBNK01 SELBNK00 SELBNK01 SELBNK11 SELBNK21 SELBNK31 SELBNK00 SELBNK10 SELBNK20 SELBNK30 RAS0# redirect bank (default) RAS1# redirect bank (default) RAS2# redirect bank (default) RAS3# redirect bank (default)
Cycle Control Register
Default
Function When this disables BS16# output. When this enables cache write cycle zero wait state. Reserved. When this enables cycle, wait state. When this enables cycle, wait state. Reserved. When this disables cycle.
Control Register
Default
Function When this enable hold time. When this enable slow recovery time. Default zero. Recovery control Recovery control Recovery control
MicroControl Register
Default
Function Recovery control Recovery control Recovery control access
Recovery time 0(default)
access
Recovery time (default)
Note: unit Recovery time cycle. Refresh DRAM Setup Register
Default
Function Reserved. Must one. When this enables wait cycle. These bits refresh burst count control bits. Rate refresh request (Default)
MicroRegister
Default
Function These bits extend width write cycle activating earlier. Width Extension extension. (Default) cycle earlier These bits extend width read cycle activating earlier. Width Extension extension. (Default) cycle earlier
Suspend Mode Control Register
Default
Function Reserved. Reserved. Must zero. When this forces data level drives data during 5Volt Suspend mode. Reserved.
DRAM, Control Register
Default
Function When this enables X-2-2-2 cache read burst cycle. When this adds extra wait state cycle. When this adds wait state DRAM cycles. Level write back implemented cache write wait state will one. Level write through implemented post write wait state will one. Reserved. Reserved. When this enables hidden burst refresh. When this disables standard refresh.
MicroDRAM Setup Register
Default
Function These bits define burst refresh active cycle width. Default Bits Cycle width These bits define burst refresh precharge cycle width. Default Bits Cycle width Reserved. These three bits define burst refresh count. Default Bits Burst number
ADS#, Setup Register
Default
cycle times
Function When this enables ADS# delay. Default systems, zero systems. When this disables internal cache. When zero this enables internal cache. Reserved. Enable cache always miss initialization. Normal Always Always miss Reserved. When delay line cycle times. When zero delay line cycle times. When this enables fast uses clock generate CAS. When zero uses clock source.
MicroRegister
Default
Function Reserved. When this enables local bus. When this disables RAS3 output. When zero this enables RAS3 output. When this disables RAS2 output. When zero this enables RAS2 output. When this disables RAS1 output. When zero this enables RAS1 output. This works conjunction with Register 1Ch, turbo normal speed according following table through software (integrated keyboard) control: Reg. Reg. System Speed Normal Turbo Turbo Normal
Register Defaul Function Reserved. This reads status turbo allow integrated keyboard control turbo normal speed. Reserved. These read only version bits.
Register Defaul Function When internal keyboard enabled. Default controlled ENSOL# ENKBD# pulling high (enable internal keyboard), pulling (disable internal keyboard). Reserved. When this color select signal internal keyboard. When this signal Keyboard/Mouse swap. Reserved. When this enables dirty check. This always non-dirty.
MicroRegister
Default
Function When this disables DRAM page mode operation write back mode. Cache size control bit. Cache size 128K 256K 512K When this enables write back cache mode. Cacheable DRAM range control bit. 32-K cache Cacheable DRAM range 0-3FFFFF single 0-7FFFFF 0-FFFFFF 0-1FFFFFF 64-K cache Cacheable DRAM range 0-7FFFFF single 0-FFFFFF 0-1FFFFFF 0-3FFFFFF 128-K cache Cacheable DRAM range 0-FFFFFF single 0-1FFFFFF 0-3FFFFFF 256-K cache Cacheable DRAM range 0-1FFFFFF single 0-3FFFFFF 512-K cache Cacheable DRAM range time, uses only single tag. Note: DRAM size larger than cacheable DRAM size, should Register specify non-cacheable DRAM range.
MicroRegister
Default
Function Reserved. Reserved. This must zero. When this enables segment 3000h. When along with one, this will enable Intel CPU. When this enables Local Bus. When this enables segment F000h. When this enables segment 6000h. Reserved.
Stop Clock Protocol Register
Default
Function When this clock recovery time select STPSEL1. When this clock recovery time select STPSEL0. Default zero. Time Duty Cycle STPSEL1 STPSEL0 18.5 When this disables clock recovery time, i.e., STPCLK# deasserted immediately after STPGRNT# asserted. When this enables recovery time microseconds. Default millisecond range. Default zero. When this enables alternative de-turbo. This bypasses TURBO Reg. When one, along with Register having been system will normal mode. When this enables Stop Clock Protocol.
Power Control Register Register
Default
Function Power control 8-15. External hardware latch required these bits power control power devices.
Local Registers (25h-26h) Local Control Register
Default
Function When ADS# will used instead EADS# Memory Write. Both ADS# EADS# active during memory write. Reserved.
MicroLocal Control Register
Default
Function This option available only one. When one, this enables checking block both this must both one. When one, this enables checking When this will blocked detected before second When one, this enables internal latch signal.
Local Control Register
Default
Function Reserved. This must zero. When KEN# deasserted during SMIACT#. When FLUSH# asserted after leaving SMM. When this tri-states BS16# during Local cycles. When warning tone from will generated irrespective status When both keyboard reset fast reset blocked from SMI# active till clocks after SMIACT# deasserted. When STPCLK# will pulsed periodically SMM. time defined using Register 20h, bits listed below: Time Duty Cycle STPSEL1 STPSEL0 1/32 1/32 1/16 1/16 Period Time cycle Reserved. 35.6 7.76
Power Control Registers (27h-29h) Power Control Register Register
Default
Function Power control 7-0. External hardware latch required these bits power control power devices.
MicroPower Control Register Register
Default
Function When this enables include D8000-DFFFF. When this enables include D0000-D7FFF. When this enables include C8000-CFFFF. When this enables local video include B0000-BFFFF. When this enables local video include A0000-AFFFF. When more wait state will inserted before start cycle. When Read cycle will wait state less after command. Default more wait state inserted after command guarantee data hold time high speed operation.
Power Control Register Register
Default
Function Reserved. When will turbo speed SELSPEED (reg. one. When zero will normal speed SELSPEED one. SELSPEED zero, this will affect speed. When SOFTTURB (reg. will determine speed, irrespective hardware software current setting. When local memory cycle will trigger VRAM timers EXTVRAM (reg. one. Reserved. When TURBO becomes SUSPACK# (from CPU). Reserved. When Registers 54-5F 76-7F accessed.
High Speed Throttle Register
Default
Function When high speed throttle mode will enabled. These bits select high speed throttle duty cycle Turbo: normal Disabled (Default) Reserved.
MicroHigh Speed Throttle Register
Default
Function high transition this will assert STPCLK# till INTR occurs. Select high speed throttle clock Clock Selected 32ms (Default)
Speed Throttle Register
Default
Function When speed throttle mode will enabled. These bits select speed throttle duty cycle Normal: STPCLK# keep asserted Disabled (Default) Reserved. Reserved. This must zero. These bits select speed throttle clock. Clock selected 32ms
Miscellaneous Register
Default
Function Reserved. zero When one, HOLD will asserted when STPCLK# asserted. When one, FLUSH# will asserted when CPURDY# asserted runs normal speed. When one, CLKSRC will stopped suspend mode. When one, leakage control function will enabled suspend mode. When one, internal modules will have their clocks stopped save power functions modules use. When module will stopped there cycle. Reserved.
MicroScratch Register Register 2Dh,
2087 provides scratch registers that allow system designer save some flags these registers instead saving system RAM. Register
Default
Function When this selects base address mapping. Segment 3000h segment B000h. Segment 6000h segment A000h. Segment C000h segment A000h. Segment D000h segment B000h. Segment F000h segment B000h. When segment D0000h-DFFFFh becomes space. When segment C0000h-CFFFFh becomes space. When segment D8000h-DFFFFh becomes part BIOS. Reserved. When D0000h-DFFFFh becomes Local RAM. When C0000h-CFFFFh becomes Local RAM.
Local Setup Register
Default
Function These bits command width local read cycle Command width When BALE driven during local cycle. When local cycle supported. When zero only local cycle supported. When drive access will local cycle. When drive access will local cycle.
MicroLocal Setup Register
Default
Function These bits recovery time local cycle. Default must one. Recovery time These bits command width local write cycles. Default must one. Command width
MicroLocal HITM# Setup Register
Default
Function When these bits selects HITM# sample time. Bits HITM# Sample Time clocks clocks clocks Reserved. When this zero Register 31h, bits will command width both Local read write cycles. When this then Register 30h, bits controls local read cycle width; Register 31h, bits controls local write cycle width. When these bits define hold time local cycles. Bits Hold time (cycles) When these bits define setup time local cycles. Bits Setup time (cycles)
MicroThermal Control Register
Default
Function When this enables satuate When this enables satuate When this enables satuate When this enables satuate Reserved. When this enables segment counting. When this enables temperature control.
Thermal Control Register
Default
Function When this enables limit When this enables limit When this enables limit When this enables limit When this enables high limit When this enables high limit When this enables high limit When this enables high limit
Thermal Control Register
Default
Function When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter
Thermal Control Register
Default
Function When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter When this enables temperature emulation counter
MicroDRAM Cache Setup Register
Default
Function Reserved. Reserved. This must zero. When zero DRAM burst write enabled. When zero cache burst write enabled. When along with Reg. one, cache burst write x-2-2-2 cycles enabled. Note: cache burst write only supported with write back implementation. Doze Mode Count Register
Default
Function These bits time period that will returned turbo speed after interrupt acknowledge cycle. Time period (default) These bits timeout period system event doze timer. Timeout Disable (default) 1/32 1/16 These bits timeout period VRAM doze timer Timeout Disable (default)
MicroCount Register
Default
Function These bits timeout period local standby idle timer Timeout Disable (default) These bits timeout period local standby idle timer Timeout Disable (default)
MicroCount Register
Default
Function These bits timeout period VRAM idle timer Timeout Disable (default) These bits timeout period keyboard idle timer Timeout Disable (default)
MicroGlobal Standby Auto Suspend Register
Default
Function These bits timeout period auto suspend idle timer Timeout Disable (default) These bits timeout period global standby idle timer Timeout Disable (default)
MicroButton Battery Count Register
Default
Function These bits timeout period battery suspend warning timer Timeout Disable (default) These bits timeout period button suspend warning timer Timeout Disable (default)
MicroGlobal Control Register
Default
Function When power enabled. When software enabled. When external source enabled. When external source enabled. When suspend mode enabled. Default When global standby mode enabled. When doze mode enabled. When local standby mode enabled.
Global Control Register
Default
Function When SMI# will deasserted. When trigger signals local standby global standby idle timers will disabled. When battery status will generate warning tone. When clock will returned turbo speed period time after interrupt acknowledge cycle. When SMI# will asserted ENSFT (reg. set. When SUSPEND# will asserted when IN5VSP (reg. set. Reserved. When clock will stopped when IN5VSP (reg. set.
Local Standby Control Register
Default
Function When IRQ8 will trigger doze mode VRAM timer. When IRQ0 (timer ticker) will trigger doze mode VRAM timer. When doze mode system event timer will always timed out, irrespective programmed co
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