MICRO 2051nt PENTIUM-CLASS SINGLE CHIP SOLUTION NOTEBOOK APPLICATIONS
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2051nt
MICRO 2051nt PENTIUM-CLASS SINGLE CHIP SOLUTION NOTEBOOK APPLICATIONS
DATA BOOK ADVANCED INFORMATION
JANUARY 1997 Revision
Microelectronics Corporation, 2500 Augustine Drive, Santa Clara, 95054 Phone: (408) 980-0622 Fax: (408) 980-0626
Micro
2051nt
Microelectronics Corporation 2500 Augustine Drive, Santa Clara, 95054 Phone: (408) 980-0622 Fax: (408) 980-0626 Copyright 1996 Microelectronics Corporation. rights reserved. 520210 Rev. January 1997 Copyright part this publication reproduced, transmitted, transcribed, stored retrieval system, translated into language computer language, form means, electronic, mechanical, magnetic, optical, chemical, manual, otherwise, without prior written permission Microelectronics Corp, 2500 Augustine Drive, Santa Clara, 95054. Disclaimer Microelectronics Corp. makes representations warranties with respect design documentation herein described especially disclaims implied warranties merchantability fitness particular purpose. Further, Microelectronics Corp. reserves right revise design associated documentation make changes from time time content without obligation Microelectronics Corp. notify person such revisions changes. Trademarks Single Chip Solution registered trademark Microelectronics Corp. other trademarks copyrights property their respective holders.
Microelectronics Corporation, 2500 Augustine Drive, Santa Clara, 95054 Phone: (408) 980-0622 Fax: (408) 980-0626
Micro
2051nt
Table Contents
Title Introduction Micro 2051nt Single Chip Solution Description Micro 2051nt Single Chip Solution Features Micro 2051nt Block Diagram Functional Description Cache DRAM Interface Posted Write/Pre-fetch Buffers Clock Power Management Modes 2.6.1 Fully-On 2.6.2 Standby 2.6.3 Suspend 2.6.4 Doze Idle Timers 2.7.1 Global-StandBy Timer 2.7.2 Auto-Suspend 2.7.3 Local-Standby Timers 2.7.4 Doze Timers 2.7.5 Warning Timers SMM/SMIs Thermal Control 2.10 Battery Management 2.11 Power 2.12 Mobile PC/PCI 2.13 CLKRUN# 2.14 Device Shadowing Micro Specifications Description Table Clock Interface Table Interface Table Cache Interface Table DRAM Interface Table Interface Table Reset Interface Table Interface Table ISA/IRQ Interface Table ISA/XD Interface Table 3-10 Real time Clock Interface Table 3-11 Address Buffers Decodes Interface Page
Micro
2051nt
Title
Page
Table 3-12 PC/PCI Interface Table 3-13 Interface Table 3-14 Misc. Interface Micro 2051nt Numerical Arrangement Cache) Micro 2051nt Alphabetical Arrangement Cache) Micro 2051nt Summary Table Multiplex Pins Micro 2051nt Power Plane Summany Table Micro 2051nt Shadow Register Application
Micro 2051nt Register Settings Device Function Configuration 4.1.1 Range Control 4.1.2 Address Memory Configuration 4.2.1 DRAM Configuration 4.2.2 Cache Configuration Power Management 4.3.1 Suspend Control 4.3.2 GPIO Device Function Configuration 4.4.1 Configuration 4.4.2 Chip Select Functions 4.4.3 Peripheral Selection Device Function Configuration 4.5.1 Control Standard Configuration 4.6.1 Registers 4.6.2 VRAM Power Control 4.6.3 Doze Mode Control 4.6.4 Warning Timers 4.6.5 General Chip Select 4.6.6 Standby Control 4.6.7 Suspend Control 4.6.8 Battery Control 4.6.9 Thermal Control Through Software Emulation 4.6.10 STOP Clock Control Interrupt Controller Register 4.7.1 IRQ7-IRQ3 Edge/Level Control Register 4.7.2 IRQ15-IRQ9 Edge/Level Control Register
Micro 2051nt Specifications
Micro
Title
2051nt
Page Micro 2051nt Specifications
Timing Diagrams 6.1.1 Propagation Delay 6.1.2 Valid Delay from Rising Clock Edge 6.1.3 Setup Hold Times 6.1.4 Float Delay 6.1.5 Clock High Timers Period 6.1.6 Pulse Width 6.1.7 Output Output Delay Signals Timing 6.2.1 CLOCK Timing 6.2.2.CPU Interface Timing 6.2.3 Asynchronous Cache Interface Timing 6.2.4 Synchronous Cache Interface Timing 6.2.5 Fast Page Mode DRAM Interface Timing 6.2.6 Interface Timing 6.2.7 Interface Timing Functional Timing Diagram 6.3.1 Reset Timing 6.3.2 Shutdown Timing 6.3.3 16-Bit Access Timing 6.3.4 8-Bit Access Timing 6.3.5 Fast Page Mode DRAM Access Timing-Read Cycle 6.3.6 Fast Page Mode Access Timing-Write Cycle 6.3.7 Page-Write Missed Cycle Timing 6.3.8 Page-Read Missed Cycle Timing 6.3.9 Asynchronous SRAM Burst Read Cycle (3-2-2-2) 6.3.10 Asynchronous SRAM Burst Write Cycle (4-2-2-2) 6.3.11 Pipeline Synchronous SRAM Burst Read Cycle 6.3.12 Pipeline Synchronous SRAM Burst Write Cycle (3-1-1-1) 6.3.13 CPU-to-PCI Single Read 6.3.14 CPU-to-PCI Single Write, Write Buffer 6.3.15 CPU-to-PCI Multiple Write, Write-to-Buffer, Burst Write122 Micro 2051nt Diagram 7.1.1 Micro 2051nt 7.1.2 Micro 2051nt 7.1.3 Micro 2051nt Mechanical Data View Side View 7.1.4 Micro 2051nt Mechanical Data View 7.1.5 Package Dimensions
Appendix List Sales Representatives
Micro
2051nt
Micro 2051nt Single Chip Solution Notebook Applications
Section Introduction
Description Micro 2051nt, Single Chip Solution true 64-bit high performance notebook solution support Intel Pentium, Cyrix microprocessors. rich feature Micro 2051nt includes: level write-back cache controller, DRAM controller, interface, interface, Micro Power Management control. integrated level cache controller supports different types SRAM such burst, pipeline burst, standard asynchronous SRAM. Extended Data Output (EDO, Fast Page Mode DRAM supported integrated DRAM controller. built-in interface synchronous asynchronous mode with mobile/PCI support docking designs. Micro Power Management allows system power consumption controlled various operation modes such Power-on suspend, Power-down suspend, Standby, Doze. whole system partitioned into four different power planes: interface level cache interface, DRAM interface, interface, interface. Every power plane, except (which always 5.0V) independently configured either 3.3V 5.0V. external level shifter required. Features Supports Intel P54C, Cyrix Linear burst support 64-bit Pentium class with frequency Micro Power Management Control SMM/SMI support Individual sets system events break events such Global Standby, Local Standby, Suspend, Doze control. Dedicated external trigger inputs such battery monitoring, suspend/resume button, power. Software Warning Timer Patented 'Adaptive Thermal Control' with auto-control generation Shadow Registers suspend disk Suspend DRAM CPU/PCI/ISA individually suspend/powered-down Stop clock protocol, STPCLK# suspend suspend Warm Docking Mobile PC/PCI CLKRUN# protocol reduce power consumption Serialized interrupt protocol, SIN#/SOUT# interrupt routing docking design Serialized protocol routing docking design
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2051nt
2051nt Features (continued)
Synchronous/asynchronous Synchronous clock CPUCLK/2 Asynchronous clock Four masters Converts back back sequential memory writes burst writes Bytes merge memory write Eight Dwords deep posted write buffers Four Dwords pre-fetch buffers read from memory DRAM posting Qwords deep from DRAM pre-fetched buffers Qwords deep Pre-snoop capability DRAM with bandwidth MB/s Built-in DRAM controller Five banks DRAM, 512MB main memory Self-Refresh DRAM support Fast Page Mode DRAM Five lines Symmetrical/Asymmetrical DRAMs 64-bit data path memory 64-bit DRAM option individual bank Four Qword posted write buffers x-1-1-1 DRAM write cycles Support DRAM Built-in level cache controller Direct mapped write back/write through Burst, pipelined burst, standard SRAM Cache read/write x-1-1-1-1-1 with pipelined burst SRAM Built-in full-blown interface Integrated 8254x1, 8259x2, 8237x2 Programmable speed Independent edge/level triggered interrupt controller Optional Type-F X-bus support chip select decode Flash EPROM support Dedicated cycles option free Integrated Fast interface Enhanced Support master/DMA mode Built-in Dwords posted write buffer Built-in Dwords pre-fetched buffer Four independently programmable register sets timing control Built-in 64-bit data path
Micro
Block Diagram
2051nt
DRAM CACHE
Status
2051nt
Keyboard Data, PS/2 Mouse Enhanced Power Management Control
EPROM Super 32-bit Audio
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2051nt
Section Functional Description
Cache direct level cache controller incorporated support 2MBytes SRAM using either burst, pipelined burst, standard SRAM. dynamic write-back/write-through algorithm implemented optimize bandwidth between cache main memory. Alternatively, cache 3-1-1-1-1-1-1-1 burst transfer achieved using pipelined burst SRAM. Using standard SRAM, 3-2-2-2 cycles achieved. DRAM Interface DRAM controller optimized support standard fast page mode Extended Data (EDO). 512MBytes memory space supported with lines. Both, symmetrical asymmetrical addressing DRAMs supported. memory data path either 32-bit, 64-bit, mixed. Four Qwords buffers implemented support 3-1-1-1 posted write cycles. With 60ns DRAM, x-2-2-2 burst read sequence achieved Mhz. pseudo mode also available standard DRAM achieve x-3-3-3 burst read sequences. This 32-bit interface with Rev. compliant support four master devices addition host DMA/master requests with either fixed rotated priority scheme. initiated write cycles, controller supports byte/word/Dword merge will convert sequential write into burst sequence. Pre-fetch functions also supported initiated read cycles. DRAM burst access reach X-1-1-1-1-1-1-1 32-bit during both read write cycles. Posted Write/Pre-fetch Buffers 4-Qword write buffer implemented main memory writes. Another 4-Qword buffer also implemented CPU-to-PCI writes. pre-fetch buffer PCI-to-main memory write buffer operate concurrently. pre-fetch buffer with DRAM posted write buffer, forms 8-Qword buffer provide PCI-to-main memory transfer. Clock Both clock (CPUCLKO) clock (PCICLKO) derived from clock source, CLKSRC. fully-on mode, CPUCLKO defined CLKSRC/1, PCICLKO defined CLKSRC/2. During operation, both CPUCLKO PCICLKO scaled, modulated, stopped independently.
Micro
2051nt
Power Management Modes Micro Power Management core provides four major power management modes, Fully-On, Standby, Suspend, Doze. Every mode associated timers different system events used monitor trigger sources. transition between Fully-On, Standby, Suspend fully programmable through routines Doze mode enabled during Fully-On well Standby mode. Doze mode, once enabled, will dynamically conserve power without system intervention. Dedicated input/output pins also available further facilitate system design, including external inputs, suspend input, power on/off sequencing, etc. This increased flexibility allows system designers fully customize diversify their products. 2.6.1 Fully-On default condition after power Fully-On. running full speed peripherals powered-up. Doze function enabled from this mode conserve power when selected idle condition detected. 2.6.2 Standby Standby mode indicates that system need full power, thus operated lower speed. Additionally, peripheral devices selected powered down further power savings. system enter this mode when pre-defined system events occur pre-programmed period time. pre-defined break event bring system back Fully-On mode. Register section 4.6.6 herein shows specific details regarding programming Standby function. 2.6.3 Suspend Three suspend modes supported: Freeze, Power-On-Suspend, Power-Down-Suspend (SuspendTo-Disk, 0V-Suspend). Freeze mode, devices still powered will enter individual standby modes clocks will stopped. complexity system design dramatically reduced since power plane partitioning leakage control required. data restoration power-on sequencing needed since devices still retain their contents provide fastest resume process. Power-On-Suspend also provides fast resume process consumes minimum power keeping only necessary devices powered. Power-hungry devices, such CPU, SRAM, some peripheral devices turned off. Power-Down-Suspend mode will save system contents into disk power down devices except RTC. This mode provides maximum power savings since very little power consumed longer restart time required. System designers implement this mode deepest suspend mode, enable only when battery exhausted. Register section 4.6.7 herein shows specific details regarding programming Suspend function. 2.6.4 Doze When idle condition been detected, will into low-power consumption state. STPCLK# asserted stays STOP-GRANT-STATE. information programming Doze Mode control, refer register section 4.6.3.
Micro
Idle Timers
2051nt
2.7.1 Global-StandBy Timer After pre-programmed period time, pre-selected system events occur, generated. system designers decide either conserve mode directly into suspend modes. Standby mode used, Auto-Suspend-Timer also enabled force system into suspend mode after pre-programmed period idle time. pre-selected break event will generate another wake system. 2.7.2 Auto-Suspend Timer Auto-Suspend Timer when programmed enabled, will generate idleness occurs programmable period time. 2.7.3 Local-StandBy Timers Four timers available monitor peripheral activities, including VRAM, keyboard, general chip select general chip select VRAM/keyboard timers monitor video buffer access user activities. proprietary Video-Idle-Filter incorporated filter real video idleness. General chip select general chip select timers (GCS [0:1]) programmed monitor access specific range. activity observed during pre-programmed period time, SMIs will generated. preselected break event occur will generate another associated local suspend set. 2.7.4 Doze Timers Three timers used monitor timer tick, system events, user activities decide idle state. 2.7.5 Warning Timers function except global standby mode, local standby mode, auto suspend mode, qualified with warning timer avoid interrupts during other previously requested functions. SMM/SMIs addition timer-generated SMIs, both Soft-SMI External-SMIs also implemented. Soft-SMIs activated through software commands. External-SMIs generated dedicated button/switch combination keystrokes. Those pins include general-purpose inputs, EXTSMI#[0:2], specialpurpose inputs, SRBTN# (Suspend/Resume Button), BATLOW0# (Low Battery), ACPWR Power).
Micro
Thermal Control
2051nt
Closed-loop open-loop thermal control techniques used alleviate temperature problems. external thermally coupled circuit used automatically enable built-in clock throttling function. clock throttling function also enabled open-loop solution. Micro's patented Adaptive Thermal Control embedded Micro 2051nt used eliminate external thermal coupling provide pseudo-closed-loop solution. properly adjusting high temperature threshold threshold, over-heat warning zone defined clock throttling function will automatically enabled when emulated temperature value falls within this range disabled exit. also generated option when entering exiting temperature critical zone. 2.10 Battery Management battery status pin, BATLOW0# provided battery exhaustion processing. When BATLOW0# asserted, SMI# will asserted after optionally pre-programmed POWER-LEFTOVER time. warning tone enabled through register during routine, warn user exhausting battery power before issued. 2.11 Power ACPWR treated special input. SMI# will asserted when AC-POWER changes state. power management routine BIOS read internal registers know ACPWR condition. 2.12 Mobile PC/PCI PC/PCI protocol supported facilitate mobile docking station design. master/grant pairs, INTx#, non-occupied IRQs DRQs programmed support MHPG architecture. 2.13 CLKRUN# clock controlled through CLKRUN protocol. CLKRUN# de-asserted clock will stopped activities observed. clock stretched slowed down extended cycles. 2.14 Device Shadowing PCI-Docking extention (PD) supports full-blown docking capabilities providing PCI-to-PCI PCI-to-ISA bridge. Alternate devices ports located docking station such alternate keyboard, RTC, FDC, RAMDAC programmed either primary secondary functions. access primary functions programmed overshadow secondary functions.
Micro
2051nt
Section Specifications
2051nt Description
Table Clock Interface
Name CPUCLKI KCLK PCICLKO
Type
CPUCLKO PCICLKI CLKSRC
SYSCLK PWR3
Description clock input. Cache (advance) clock cache write. KCLK's faster than Host clocks. Used Asynchronous SRAM only. Clock device core logic state machine. This clock should separate buffer provide clock core logic devices. provides clock core logics CPU. This clock should separate buffer provide clock core logics CPU. clock input 2051nt. System clock source. input clock from CMOS oscillator clock chip. CLKSRC provides clock source CPUCLKO PCICLKO. 14.318 input clock from external clock source. used clock reference. When Standard Configuration Register one, provides clock bus. This multifunction pin. default this becomes PWR3 (power control power management function.
Table Interface Name /ADS M/-IO D/-C W/-R Type Description /ADS driven directly ADS# pin. asserted cycle. When high, indicates current cycle memory access cycle. cycle when low. indicates whether current cycle data control cycle. indicates whether current cycle read write cycle.
Micro
2051nt
Table Interface contd.
/BRDY /HIT-M /EADS /BOFF /CACHE /KEN /LOCK /SMIACT A[3:31] D[0:63] /BE[0:7] INTR /A20M /FERR /IGNNE
indicates data read/write cycle ready. Asserted indicate that snoop cycle modified line needs written back. indicates valid external address been driven onto processor address pins used inquiry cycle. used back current cycle. indicates system controller ready accept cycle although data transfers current cycle have completed. /CACHE asserted indicate internal cacheability cycle (for read), indicate burst writeback cycle (for write). response CACHE#, asserted CPU, /KEN asserted transform cycle into burst line fill cycle. indicates current cycle locked. indicates that system management mode after /SMI being served CPU. These input during cycles. They become output during snoop cycle. Data bus. These used indicate which byte lanes cycle accessing. Non-Maskable Interrupt. connects CPU. indicates valid interrupt request asserted. Gate A20. Numeric Coprocessor Error. indicates coprocessor error. Ignore Error.
Table Multifunction Cache Interface (The level cache disabled power-on default) Name Type TPWROUT0-6 Description When Register output value these signals programmed through Register (device function When level cache enabled, these signals become TAG0-6. addresses used determine cycles (read/write) miss. When Reg. this signal becomes PWROUT4 control pin. When level write back cache enabled, this becomes dirty bit.
TAG0-6 PWROUT4 TAG7
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2051nt
Table Multifunction Cache Interface (The level cache disabled power-on default) contd. Name TPWROUT7 Type Description When Register output value this signal programmed through Register (device function When level cache enabled, will write dirty line back DRAM. value this status input read from Register When level cache enabled, this becomes SRAM write enable. value this status input read from Register When level cache enabled, this becomes DATA SRAM output enable. value this status input pins read from Register 0-7. When level cache enabled, this becomes DATA SRAM write enable. value this status input read from Register When Burst SRAM (either pipe pipe) used, this becomes Burst SRAM/ADV. When level cache enabled, when Asynchronous SRAM used, this becomes burst value this status input read from Register When Burst SRAM (either pipe non-pipe) used, this becomes Burst SRAM/ADSC. When Asynchronous SRAM used, becomes burst value this status input read from Register When cache enabled, this becomes DATA SRAM chip select. When Reg. 82h, configuration register device function one, /KALE becomes power output PWROUT0. value output this programmed from Register When cache enabled, this becomes cache address latch enable.
KCSTS4 /TAGWE KCSTS0 /KOE KWSTS0-7 /KWE0-7 KCSTS2 /ADV
/TKA4 KCSTS3 /ADSC
/TKA3 KCSTS1 /KCS PWROUT0
/KALE
Micro
Name /RAS4-3 PWROUT1-2 Type
2051nt
Table DRAM Interface Description DRAM address selection. When Reg. 82h, configuration register device function bits one, /RAS4-3 becomes power output PWROUT1-2. value output this programmed from Register 1-2. DRAM address selection DRAM column address selection. DRAM write enable. DRAM column address. Memory data bus.
/RAS2-1 /CAS7-0 /WEN MA11-0 MD[0:63]
Table Interface pull-up resistor PCI's required interface signals
Name /FRAME
Type
/TRDY
/IRDY /STOP /DEVSEL /PCILOCK AD[31:0] C/-BE[3:0]
/REQ[3:0] /GNT[3:0] /CLKRUN /SERR /INTA-/INTD
Description driven current master indicate beginning duration transaction. During master cycle, input. output during cycle. indicates target device ready complete data transfer. data transfer completed when target asserting /TRDY master asserting /IRDY rising edge clock. indicates initiator ready data transfer. indicates current target requesting initiator stop current transaction. input, indicates whether device been selected. indicates target device decoded address output. used prevent multiple access same target device same time. 31-0. Parity bus. Parity asserted clock after data phase ensure even parity across AD[31:0] C/BE[7:0]. state C/-BE[3:0] indicates which locations currently-addressed doubleword being addressed number additional bytes transfer. indicates master requests bus. indicates granted master request. used mobile PC/PCI serial interrupt protocol restart clock interrupt received while clock stopped. system error. indicates address parity data errors could cause processor flag error condition. Interrupt request lines from devices.
Micro
Name PWRGD RSTDRV CPURST INIT /PCIRST Type
2051nt
Table Reset Interface Description Power good signal from system power-good circuitry. must stable least 1ms. used reset chip. used reset devices when system powered-up. used reset when system powered-up. INIT asserts indicate shutdown special cycle bus. used reset (for insertion). Connect /PCIRST device's reset pin.
Table Name SA[16:0] LA[23-17] /MASTER
Interface Type Description System address bus. Latcheable address bus. input from active device channel. After /MASTER forced device, must wait system clock period before driving address data lines. should held more than 15ms this result memory loss lack refresh cycle. Indicates valid address bus. BALE used hold address during cycle System byte high enable. /SBHE indicates upper byte transfer (8bit transfer with address even address 16-bit transfer). This multifunction pin, default (Reg. zero), this becomes PWR4 (power control power management function. When Register configuration register equals /SMEMR. indicates read cycle addressed lower memory space. When Register [4,3,2] [1,X,1] becomes programmable chip select (/PCS2). This multifunction pin, default (Reg. zero), this becomes PWR2 (power control power managment function. When Register configuration register one, this /SMEMW. indicates write cycle addressed lower memory space. When Register [4,0] [1,1] becomes programmable chip select (/PCS3). commands memory place valid data data bus. commands memory accept data from data bus. commands device place valid data data bus. Commands device accept data from data bus. Enables 16-bit memory access channel. Enables 16-bit access channel.
BALE /SBHE PWR4
/SMEMR
/PCS2 PWR2
/SMEMW
/PCS3 /MEMR /MEMW /IOR /IOW /MCS16 /IOCS16
Micro
Table Name /ZWS Type
2051nt
Interface contd.
IOCHK IOCHRDY X32K
Description When device requires zero wait state, /ZWS will assert. causes cycle terminate. zero wait state effect during 16bit cycle. Indicates error condition from device causes system generate CPU. causes wait state(s) asserted memory accesses. suspend mode, this program become 32KHz clock input power management module DRAM refresh state machine. input, causes refresh cycle from master device. output, initiates refresh cycle DRAMs. 16-bit System data bus. request input lines used peripherals obtain service. Transfer completed. controller actived when byte word transfer count channel been exhausted. Indicates that service been granted request line peripherals. These signals multiplexed with power control bits power management control signals. When Register configuration register one: /DACK7 becomes PWR9 /DACK6 becomes PWR8 /DACK3 becomes PWR7 /DACK1 becomes PWR6 /DACK0 becomes PWR5 Address enable transfer. inactive when external master controls system bus.
/REF SD[15:0] DRQ7-0 /DACK7-0
PWR9-5
Table Name IRQ1
ISA/IRQ Interface Type Description When internal keyboard disabled, Reg. 68h, equals zero, this used IRQ1 input external keyboard controller (default). When Reg. 68h, configuration register device function one, internal keyboard enabled, this keyboard lock signal. Interrupt request. When internal keyboard disabled, Reg. 68h, equals zero, this interrupt request line PS/2 mouse (default). When internal keyboard enabled, this mouse data line. (Reg. 68h, configuration register device function one).
KEYLOCK
IRQ3-15 IRQ12
MSDATA
Micro
Table Name /KBCS Type
2051nt
ISA/XD Interface Description Keyboard chip select (default). When internal keyboard disabled, Reg. 68h, configuration register device function equals zero. When internal keyboard enabled, this mouse clock. When internal keyboard disabled, Reg. 68h, equals zero, this used keyboard gate (default). When Reg. 68h, configuration register device function one, internal keyboard enabled, this keyboard data. When internal keyboard disabled, Reg. 68h, equals zero, this used keyboard reset (default). When Reg. 68h, configuration register device function one, internal keyboard enabled, this keyboard clock. Real time Clock Interface Type Description Real timer clock address strobe used multiplex external real time clock plus peripheral device. Real time clock read/write used indicate read write mode plus device. Real time clock data strobe used control bi-directional ext. RTC.
MSCLK KBGA20
KBDATA
/KBRST
KBCLK
Table 3-10 Name RTCAS /RTCWR /RTCDS
Table 3-11 Name /XDIR
Address Buffers Decodes Interface Type Description controls direction data transfer between peripheral channel. When low, should drive signals toward bus. When high, should drive toward bus. used generate XDIR during read cycle.
/ROMCS Table 3-12 Name /SOUT /SIN
PC/PCI Interface Type
Description Serial out. Mobile serial interrupt handshaking. Serial Mobile serial interrupt handshaking.
Micro
Table 3-13 Name /STPCLK /SMI PWR0 /LTCH0 Type
2051nt
Interface Description Indicates request switch clock power management control. Causes processor enter system managment mode once recognized. default, this power control When external latch used support power controls 0-7, this signal will used control 8-bit external latch. When Register bits {1:0], becomes PCS0, programmable chip select default, this power control When external latch used support power control bits 8-15, this signal will used control 8-bit external latch. When Register zero, indicates that system DOZE mode. When Register bits one, becomes PCS1, programmable chip select Battery status provided battery exhaustion processing. /SMI will asserted when /BATLOW0 changes state. Three external pins provided external devices that required special system handling. /SMI will asserted when they change state. /EXTSMI0-2 edge triggered signals programmed either rising edge falling-edge trigger. Suspend/Resume button implemented system into suspend mode from normal mode resume back from suspend mode. generated when button pressed. /SRBTN rising edge trigger. Power implemented report system power status. /SMI will asserted when ACPWR changes state. external system event used external device trigger source break/system event. Core logic will generate once /EXTSYS triggered. /EXTSYS rising edge trigger. /SUSP will driven when system enters suspend mode. These general purpose signal. They output input programming Reg. 85h-87h.
/PCS0 PWR1 /LTCH1
/DOZE
/PCS1
/BATLOW0 /EXTSMI0-2
/SRBTN
ACPWR /EXTSYS
/SUSP GPIO0-2,
Table 3-14 Name SPKR
Miscellaneous Type Description Gates speaker data timer drive internal speaker.
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2051nt
2051nt Numerical List (with cache)
Name /KWE7 /KWE3 TAG4 /TAGWE /KCS AHOLD /BOFF /A20M /BE4 /STPCLK /IDEDACK /KWE6 /KWE2 TAG7 TAG3 /TKA3/ADSC# /KOE /KEN /SMIACT /EADS /BE0 /BE5 /SMI PWRGD IDEDRQ PWR1 Name /KWE5 /KWE1 TAG6 TAG2 /TKA4/ADSV# /FERR /BRDY /LOCK /HIT-M /BE1 /BE6 INIT /SUSP /EXTSYS PWR0 KCLK /KWE4 /KWE0 TAG5 TAG1 CPUCLKI /ADS /BE2 /BE7 INTR /IGNNE /EXTSMI2 /SRBTN ACPWR Name TAG0 KALE /CACHE /BE3 CPURST /IRQ8 /BATLOW0 /EXTSMI0 /EXTSMI1 SPKR RTCAS /RTCWR /RTCDS /KBRST SMCLK SMDATA /ROMCS /XDIR IRQ1 /KBCS KBGA20 Name /ZWS DRQ2 IRQ9 RSTDRV CLKSRC /SMEMR /SMEMW /DACK1 DRQ3 /DACK3 /IOR /IOW IRQ4 IRQ5 IRQ6 IRQ7 DRQ1 /MCS16 BALE /DACK2 IRQ3 /CAS0 IRQ12 IRQ11 IRQ10 /IOCS16 /CAS4 /CAS3 /CAS2 /CAS1
Micro
Name DRQ0 /DACK0 IRQ14 IRQ15 /RAS0 /CAS7 /CAS6 /CAS5 DRQ6 /DACK6 DRQ5 /DACK5 /WEN /RAS4 /RAS3 /RAS2 /RAS1 CPUCLKO PCICLKO /MASTER DRQ7 /DACK7 SD11 SD12 SD13 SD14 SD15 SYSCLK /MEMW SD10 MA11 MA10 LA18 LA17 /MEMR REF# /32K
2051nt
2051nt Numerical List contd.
AA25 AA26 AA27 AA28 AA29 AB25 AB26 AB27 AB28 AB29 AC25 AC26 AC27 AC28 AC29 AD25 AD26 AD27 AD28 AD29 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 Name LA22 LA21 LA20 LA19 /SBHE LA23 MD13 MD12 MD11 MD10 MD17 MD16 MD15 MD14 SA10 MD21 MD20 MD19 MD18 MD41 MD62 /CLKRUN /STOP /CBE2 AD20 AE26 AE27 AE28 AE29 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AG10 AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 Name SA14 SA13 SA12 SA11 MD24 MD23 MD22 MD33 MD37 MD42 MD46 MD50 MD54 MD58 MD63 AD12 /CBE1 /DEVSEL AD16 AD21 AD24 PCICLKI AD31 /REQ3 /GNT3 /INTB IOCHRDY SA16 SA15 MD26 MD25 MD30 MD34 MD38 MD43 MD47 MD51 MD55 MD59 /TREQ AD13 /TRDY AD17 AD22 AD25 AD28 /REQ0 /GNT0 /PCIRST /INTA IOCHCK AG28 AG29 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 Name MD27 MD28 MD31 MD35 MD39 MD44 MD48 MD52 MD56 MD60 /TGNT AD10 AD14 /SERR /IRDY AD18 AD23 AD26 AD29 /REQ1 /GNT1 /INTD /SOUT MD29 MD32 MD36 MD40 MD45 MD49 MD53 MD57 MD61 /CBE0 AD11 AD15 /PCILOCK /FRAME AD19 /CBE3 AD27 AD30 /REQ2 /GNT2 /INTC /SIN
Micro
/A20M ACPWR AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AF12 AG12 AH12 AJ12 AE13 AF13 AG13 AH13 AF14 AG14 AH14 AJ14 AF15 AG15 AH15 AJ15 AF18 AG18 AH18 AJ18 AE19 AF19 AG19 AH19 AF20 AG20 AH20 AJ20
2051nt
2051nt Alphabetical List (with cache)
Name AD28 AD29 AD30 AD31 /ADS AHOLD BALE /BATLOW0 /BE0 /BE1 /BE2 /BE3 /BE4 /BE5 /BE6 /BE7 /BOFF /BRDY /CACHE /CAS0 /CAS1 /CAS2 /CAS3 /CAS4 /CAS5 /CAS6 /CAS7 /CBE0 /CBE1 /CBE2 /CBE3 /CLKRUN CLKSRC CPUCLKI CPUCLKO CPURST AG21 AH21 AJ21 AF22 AF27 AJ13 AF16 AE18 AJ19 AE12 Name /DACK0 /DACK1 /DACK2 /DACK3 /DACK5 /DACK6 /DACK7 /DEVSEL DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 /EADS /EXTSMI0 AF17 Name /EXTSMI1 /EXTSMI2 /EXTSYS /FERR /FRAME /GNT0 /GNT1 /GNT2 /GNT3 /HIT-M /IDEDACK IDEDRQ /IGNNE INIT /INTA /INTB /INTC /INTD INTR IOCHCK IOCHRDY /IOCS16 /IOR /IOW /IRDY IRQ1 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 KALE /KBCS KBGA20 /KBRST /KCS KCLK /KEN /KOE /KWE0 /KWE1 /KWE2 /KWE3 /KWE4 /KWE5 /KWE6 /KWE7 LA17 LA18 LA19 LA20 LA21 LA22 AJ17 AG23 AH23 AJ23 AF24 AG25 AF25 AJ24 AH24 AG26 AF26 AH17 AA29 AA28 AA27 AA26
Micro
Name LA23 /LOCK MA10 MA11 /MASTER /MCS16 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 AB29
2051nt
2051nt Alphabetical List contd.
Name MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 /MEMR /MEMW PCICLKI PCICLKO /PCILOCK /PCIRST PWRGD PWR0 PWR1 /RAS0 /RAS1 /RAS2 /RAS3 /RAS4 REF# /32K /REQ0 /REQ1 /REQ2 /REQ3 RSTDRV RTCAS /RTCDS /RTCWR /ROMCS AF10 AG10 AH10 AJ10 AE11 AF11 AG16 AF21 AJ16 AG24 AG22 AH22 AJ22 AF23 AB27 AB26 AC29 AC28 AC27 AC26 Name SA10 SA11 SA12 SA13 SA14 SA15 SA16 /SBHE SD10 SD11 SD12 SD13 SD14 SD15 /SERR /SIN SMCLK SMDATA /SMEMR /SMEMW /SMIACT /SMI /SOUT SPKR /SRBTN /STOP /STPCLK /SUSP SYSCLK TAG0 TAG1 TAG2 TAG3 TAG4 TAG5 TAG6 TAG7 /TAGWE /TGNT /TKA3/ADSC# /TKA4/ADSV# AD29 AD28 AD27 AD26 AD25 AE29 AE28 AE27 AE26 AF29 AF28 AB28 AG29 AG28 AH28 AJ28 AJ27 AH27 AJ26 AH26 AH16 AJ25 AH25 AE17 AH11 AJ11 Name /TRDY /TREQ /WEN /XDIR /ZWS AG17 AG11 A1,A29,B1, B2,C3,D4, E5,E7,E9, E15,E21,E23, E25,G5,G25, J5,J25,R5, R25,AA5, AA25,AC5, AC25,AE5, AE7,AE9, AE15,AE21, AE23,AE25, AJ1,AJ29 E6,E8,E10, E16,E20,E22, F5,F25,H5, H25,K5,K25, P5,T25,Y5, Y25,AB5, AB25,AD5,E8 AE10,AE14, AE20,AE22, AE24 E14,P25, T5,AE16
Micro
Signal Name /KOE KCSTS0 /KCS KCSTS1 KALE PWROUT0 /TKA4 /ADSV KCSTS2 /TKA3 /ADSC KCSTS3 /TAGWE KCSTS4 TAG0 TPWROUT0 TAG1 TPWROUT1 TAG2 TPWROUT2 TAG3 TPWROUT3 TAG4 TPWROUT4 TAG5 TPWRO5 TAG6 TPWROUT6 TAG7 PWROUT4 TPWROUT7 /RAS3 PWROUT2
2051nt
Summary Table Micro 2051nt Multiplex Pins
Description Cache output enable Status input Cache chip select Status input Cache address latch enable Power output Asyn. SRAM Burst SRAM Status input Asyn. SRAM Burst SRAM Status input write enable Status input (Tag) power output (Tag) power output (Tag) power output (Tag) power output (Tag) power output (Tag) power output (Tag) power output Power output Cache Dirty (Tag) power output bank Power output Related Register When cache enabled (Reg. 74h, 75h) Reg. 88h, cache disable When cache enabled (Reg. 74h, 75h) Reg. 88h, When cache enabled (Reg. 74h, 75h) Reg. 82h, Reg. 74h, select Asyn. SRAM Reg. 74h, select Burst SRAM Reg. 88h, Reg. 74h, select Asyn. SRAM Reg. 74h, select Burst SRAM Reg. 88h, When cache enabled (Reg. 74h, 75h) Reg. 88h, When cache enabled (Reg. 74h, 75h) Reg. 8Ah, When cache enabled (Reg. 74h, 75h) Reg. 8Ah, When cache enabled (Reg. 74h, 75h) Reg. 8Ah, When cache enabled (Reg. 74h, 75h) Reg. 8Ah, When cache enabled (Reg. 74h, 75h) Reg. 8Ah, When cache enabled (Reg. 74h, 75h) Reg. 8Ah, When cache enabled (Reg. 74h, 75h) Reg. 8Ah, When cache enabled (Reg. 74h, 75h) Reg. 82h, When cache enabled (Reg. 74h, 75h) Reg. 8Ah, Power default Reg. 82h,
Micro
Signal Name /KWE0 KWSTS0 /KWE1 KWSTS1 /KWE2 KWSTS2 /KWE3 KWSTS3 /KWE4 KWSTS4 /KWE5 KWSTS5 /KWE6 KWSTS6 /KWE7 KWSTS7
PWR1 /LATCH1 /DOZE /PCS1 PWR0 /LATCH0 /PCS0 /DACK7 PWR9 /DACK6 PWR8 /DACK0 PWR5 IRQ12 MSDATA /DACK1 PWR6 /DACK3 PWR7
2051nt
Micro 2051nt Multiplex Pins contd.
Description Cache write enable (Cache) Status input Cache write enable (Cache) Status input Cache write enable (Cache) Status input Cache write enable (Cache) Status input Cache write enable (Cache) Status input Cache write enable (Cache) Status input Cache write enable (Cache) Status input Cache write enable (Cache) Status input
Power output External latch control PWR8-15 Doze General chip select Power output External latch control PWR0-7 General chip select acknowledge channel Power output acknowledge channel Power output acknowledge channel Power output Interrupt Mouse data acknowledge channel Power output acknowledge channel Power output
Related Register When cache enabled (Reg. 74h, 75h) Reg. 89h, When cache enabled (Reg. 74h, 75h) Reg. 89h, When cache enabled (Reg. 74h, 75h) Reg. 89h, When cache enabled (Reg. 74h, 75h) Reg. 89h, When cache enabled (Reg. 74h, 75h) Reg. 89h, When cache enabled (Reg. 74h, 75h) Reg. 89h, When cache enabled (Reg. 74h, 75h) Reg. 89h, When cache enabled (Reg. 74h, 75h) Reg. 89h,
Power default Reg. Reg. Reg. Reg. Reg. Reg. Power default Reg. Reg. Reg. Reg. Power default Regi. Power default Reg. Power default Reg. Power default Reg. 68h, Power default Reg. Power default Reg.
Micro
2051nt
Micro 2051nt Multiplex Pins contd.
Signal Name
PWR4 /SMEMR /PCS2 PWR2 /SMEMW /PCS3 IRQ1 /KEYLOCK /KBCS MSCLK KBGA20 KBDATA /KBRST KBCLK PWR3 SYSCLK /RAS4 PWROUT1 X32K /REF /IDEDACK PWROUT3 /TREQ GPIO0 /TGNT GPIO1 GPIO2 SMDATA GPIO5 SMCLK GPIO6 IDEDRQ GPIO7
Description
Power output System memory read Programmable chip select Power output System memory write Programmable chip select Interrupt Keylock Keyboard chip select Mouse clock Keyboard GA20 Keyboard data Keyboard reset Keyboard clock Power output System clock bank Power output 32KHz Clock Source DRAM refresh master Power protocol General purpose protocol General purpose protocol General purpose
Related Register
Power default Reg. Reg. Reg. Power default. Reg. Reg. Reg. Power default Reg. 68h, Power default Reg. 68h, Power default Reg. 68h, Power default Reg. 68h, Power default Reg. Power default Reg. 82h, Reg. 81h, Power default Reserved. Reserved. Power default Reserved. Power default Reserved. Power default Reserved. Power default Reserved Power default Reserved Power default Reserved. Reserved. Power default
AG11
AH11
AJ11
master General purpose
Micro
2051nt
Micro 2051nt Power Plane Summary Table
3.3V 5.0V Signal Group CPU, Cache Names D0-63, /STPCLK, /IGNNE, INIT, /SMI, NMI, INTR, A3-31, CPURST, /BE0-7, /A20M, /HIT-M, /EADS, /ADS, /LOCK, /SMIACT, /BOFF, /NA, /BRDY, /KEN, AHOLD, /CACHE, MIO, /FERR, /KOE, /KCS, KALE, CPUCLKI, /TKA4, TKA3, /TAGWE, TAG0-7, DTY, /KWE0-7, KCLK /CAS0-7, /RAS0-7, MA0-11MD0-63, GPIO0-2, /CLKRUN, AD0-31, /CBE0-3, PAR, /SERR, /PCILOCK, /STOP, /DEVSEL, /TRDY, /IRDY, /FRAME, /REQ0-3, /GNT0-3, /PCIRST, /INTA-D, /SOUT, /SIN IOCHCK, SD0-15, IOCHRDY, AEN, SA0-16, /SBHE, LA17-23, /MEMR, REF#/32K, SYSCLK, /MEMW, CPUCLKO, PCICLKO, /MASTER, /DACK0-3, /DACK5-7, DRQ0-3, DRQ5-7, IRQ1, IRQ3-12, IRQ14-15, /IOCS16, /MCS16, BALE, /IOR, /IOW, CLKSRC, 14M, /SMEMR, /SMEMW, /ZWS, RSTDRV, /XDIR, /KBCS, KBGA20, /KBRST, SMCLK, SMDATA, /ROMCS, SPKR, RTCAS, /RTCWR, /RTCDS, /BATLOW0, /EXTSMI0-2, /SRBTN, ACPWR, /EXTSYS, PWROUT0, PWROUT1, IDEDRQ, /IDEDACK, /SUSP, PWRGD
Number E10, E16, E20, E22,
AB5, AD5, AE8, AE10, AE14, AE20, AE22, AE24
3.3V 5.0V 3.3V 5.0V
DRAM
F25, H25, K25, T25, Y25, AB25
3.3V 5.0V
ISA,
N15, P14-P16, R13-R17, T14-T16,
Thermal Grounding
Micro
2051nt
Shadow Register Application
Micro 2051nt Shadow Registers readable writeable support Intel type shadow register. addition, Micro 2051nt register readable further support power saving feature Micro 2051nt. Through shadow registers, Micro 2051nt powered current state suspended disk. Thus, device then powered back same state before last power off. This suspend resume capability minimizes system's battery power consumption thus enhances power management capabilities. Micro 2051nt Shadow Registers description listed below: Micro 2051nt Shadow Registers originally Write-Only standard. shadow mechanism makes them readable through 0F2h 0F3h indexing scheme. some registers that contain bytes have only index assigned, following sequence recommended: 0F2h, INDX 0F3h Ensure sequence would broken Output index, clear byte pointer, point byte Save somewhere High byte, byte pointer will change stay high byte
Note: write 0F2h with index 0Axh will clear byte pointer which will pointer byte. first read from 0F3h after writing index will pointer high byte. Only byte pointer shared paired register sets. first read from 0F3h will return byte second read will return high byte. those registers that bits, status unused bits reserved. Software needs mask these bits when they restored. base address registers, word count registers, channel mode registers channel mask registers, values read back from shadow registers original values loaded. values read back from shadow registers timer count original values loaded.
Micro
Register Name
2051nt
Micro 2051nt Shadow Registers Summary Mnemonic SHDMA0BA SHDMA0WC SHDMA1BA SHDMA1WC SHDMA2BA SHDMA2WC SHDMA3BA SHDMA3WC SHDMA0MOD SHDMA1MOD SHDMA2MOD SHDMA3MOD SHDMAMSK1 SHINT1ICW2 SHINT1ICW4 SHINT1OCW3 SHNMIMASK SHT1CH0CL SHT1CH0CH SHT1CH1CL SHT1CH1CH SHT1CH2CL SHT1CH2CH SHDMA4BA SHDMA4WC SHDMA5BA SHDMA5WC SHDMA6BA SHDMA6WC SHDMA7BA SHDMA7WC SHDMA4MOD SHDMA5MOD SHDMA6MOD SHDMA7MOD SHDMAMSK2 SHINT2ICW2 SHINT2ICW4 SHINT2OCW3 Original Address 0C0h 0C2h 0C4h 0C6h 0C8h 0CAh 0CCh 0CEh 0D6h 0D6h 0D6h 0D6h 0DEh 0A1h 0A1h 0A0h Index 0A0H 0A1h 0A2h 0A3h 0A4h 0A5h 0A6h 0A7h 0C0h 0C1h 0C2h 0C3h 0C4h 0D0h 0D1h 0D2h 0D6h 0CAh 0CBh 0CCh 0CDh 0CEh 0CFh 0A8h 0A9h 0AAh 0ABh 0ACh 0ADh 0AEh 0AFh 0C5h 0C6h 0C7h 0C8h 0C9h 0D3h 0D4h 0D5h Comment bytes bytes bytes bytes bytes bytes bytes bytes byte byte byte byte byte byte byte byte byte byte byte byte byte byte byte bytes bytes bytes bytes bytes bytes bytes bytes byte byte byte byte byte byte byte byte
Base Address Count Base Address Count Base Address Count Base Address Count Mode Mode Mode Mode CNTLR Mask Reg. PIC1 ICW2 PIC1 ICW4 PIC1 OCW3 Mask index CNTR CNTR high CNTR CNTR high CNTR CNTR high Base Address Count Base Address Count Base Address Count Base Address Count Mode Mode Mode CH7Mode CNTLR Mask Reg. PIC2 ICW2 PIC2 ICWW4 PIC2 OCW3
Micro
Section
2051nt
2051nt Register Settings
Micro 2051nt internal registers accessed through configuration space standard configuration space. integrated CPU, PCI, Cache, DRAM, control functions fully programmable through these internal configuration registers. Configuration Register:
configuration space divided into three functions: device function device function device function configuration registers. device function contains standard port registers, interface registers, cache control registers, DRAM control registers, clock, power management control registers. These registers accessible host CPU. first DWORD location (CF8h) references CONFIG_ADDRESS read/write register. second DWORD address (CFCh) references CONFIG_DATA register. access these internal registers, write value into CONFIG_ADDRESS that specifies bus, device that bus, configuration register that device being accessed. read write device function configuration registers will appear cycle. device function contains configuration registers device function contains interface configuration registers. These registers accessible host CPU. first DWORD location (CF8h) references CONFIG_ADDRESS read/write register. second DWORD address (CFCh) references CONFIG_DATA register. access these internal registers, write value into CONFIG_ADDRESS that specifies bus, device that bus, configuration register device being accessed. read write CONFIG_DATA will then access registers being specified. Standard Configuration Register: standard configuration register contains complete power management control registers. These registers programmed with indirect addressing scheme using addresses selects corresponding configuration register accessed address example, write value "E8" into configuration index register address must first written with value "1h," then register address with value "E8".
Micro
Standard Ports
2051nt
Device Function Configuration Registers:
Vendor Register 15-0
Default
10AA
Function Micro vendor identification
Device Register 15-0
Default
2051nt
Function Micro device identification
Command Register 15-0
Default
0004
Function local specification command register. (bits R/W)
Status Register 15-0
Default
2200
Function local specification status register. (bits 10-15 R/W)
Revision Register
Default
Function local specification revision register, default code indicates Host bridge.
Cache Code Register 22-0
Default
060000
Function local specification class code register, default 060000 code indicates bridge device.
Cache Line Size Register
Default
Function local specification cache line size register
Latency Timer Register
Default
Function 8-bit register that controls data burst time bus. Default value clock cycles.
Header Type Register
Default
Function local specification header type register
Micro
BIST Register
2051nt
Default
Function Reserved local built-in self test (BIST)
Specification Register
Default
Function Reserved local specification
4.1.1 Wait State Control Cycle (Registers 40h-43h) Register
Default
Function used. When wait state will asserted between successive /IRDY cycle. When /FRAME will delayed clock. When first /IRDY will delayed clock.
Register
Default
Function Reserved. When wait state will added 16-bit data following first 16-bit word during read. Reserved. When wait state will added lead cycle first 16-bit word during read. Reserved. When wait state will added 16-bit word following first 16-bit word during write. Reserved. When wait state will added lead cycle first 16-bit word during write.
Register
Default
Function Reserved. zero will returned read. When signal will asserted into cycle. When signal will asserted second guarantee appropriate sample period cycle. zero, will asserted during first Reserved. zero will returned read. enable byte merge mode. When wait state will added last 16-bit word during read.
Micro
Register
2051nt
Default
Function Reserved. zero will returned when these bits read.
Prefetch Range Control Registers (44h 49h) Prefetch Range Size (Registers 44h, 45h) Register
Default
Function This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range
Register
Default
Function This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range
Prefetch Range Size (Registers 46h, 47h) Register
Default
Function This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range
Micro
Register
2051nt
Default
Function This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range This when selects base address prefetch range
Prefetch Range Selection Register
Default
00000
Function When one, segment A0000h B0000h will selected prefetch range. Reserved. zero will returned when these bits read. Prefetch size range Bits
43210
Address Range don't care A16-A31 A17-A31 A18-A31 A19-A31 A20-A31 A21-A31 A22-A31 A23-A31 A24-A31 A25-A31 A26-A31 A27-A31 A28-A31 A29-A31 A30-A31
Prefetch Size Prefetchable range disabled (default). 128K 256K 512K 128M 256M 512M range prefetchable Undefined
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 others
Micro
2051nt
Prefetch Range Selection Register
Default
00000
Function Reserved. zero will returned when these bits read. Prefetch size range Bits
43210
Address Compared don't care A16-A31 A17-A31 A18-A31 A19-A31 A20-A31 A21-A31 A22-A31 A23-A31 A24-A31 A25-A31 A26-A31 A27-A31 A28-A31 A29-A31 A30-A31
Prefetch Size Prefetchable range disabled (default). 128K 256K 512K 128M 256M 512M range prefetchable Undefined
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 others
Post Write Range (Registers 4Ch, 4Dh) Register
Default
Function This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range
Micro
Register
2051nt
Default
Function This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range
Post Write Range (Registers 4Eh, 4Fh) Register
Default
Function This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range
Register
Default
Function This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range This when selects base address post write range
Micro
2051nt
Post Write Range Selection Register
Default
00000
Function When segments A000h B000h will selected post write range Reserved. zero will returned when these bits read. Post write size range Bits
43210
Address Range don't care A16-A31 A17-A31 A18-A31 A19-A31 A20-A31 A21-A31 A22-A31 A23-A31 A24-A31 A25-A31 A26-A31 A27-A31 A28-A31 A29-A31 A30-A31
Post Write Size Post writeable range disabled (default). 128K 256K 512K 128M 256M 512M range post writeable Undefined
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 others
Micro
2051nt
Post Write Range Selection Register
Default
00000
Function Reserved. zero will returned when these bits read. Post write size range Bits
43210
Address Compared don't care A16-A31 A17-A31 A18-A31 A19-A31 A20-A31 A21-A31 A22-A31 A23-A31 A24-A31 A25-A31 A26-A31 A27-A31 A28-A31 A29-A31 A30-A31
Post Write Size Post writeable range disabled (default). 128K 256K 512K 128M 256M 512M range post writeable Undefined
00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 others
4.1.2 Burstable Address (Registers 52h, 53h) Register
Default
Function This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address Reserved. zero will returned when these bits read. When primary burstable address enabled.
Micro
Register
2051nt
Default
Function This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address
Burstable Address (Registers 54h, 55h) Register
Default
Function This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address Reserved. zero will returned when these bits read. When burstable address enabled.
Register
Default
Function This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address This when selects base address burstable address
Micro
2051nt
Clock Mode Register
Default
Function Reserved. clock mode select. Bits Clock Mode Asynchronous mode (default mode) Synchronous mode Synchronized clock clock
Feature Control Register
Default
Function Reserved. When cycle will retried when write FIFO busy. When /DEVSEL asserted immediately after /FRAME sampled without wait state. Reserved. When zero memory accesses disconnected each cache line. When snoop performed next cache line while current line being accessed. When snoop write backs during memory reads pass data through bus. When zero data written back memory then read from memory.
Memory Configuration DRAM Options Control Register
Default
Function Reserved. When linear burst mode will enabled support Cyrix CPU. When DRAM posted write buffer will enabled. When fast pipeline mode will enabled. When DRAM read will complete before write posted buffers. When write back cache posted write back buffer will enabled. When DRAM data flow will delayed wait state. When signal will generated during access memory this access burstabled.
Micro
2051nt
4.2.1 DRAM Size (Registers 5Fh-63h) Micro 2051nt supports rows DRAM. Each either bits bits wide. DRAM Size Registers define lower addresses each row. Configuration Register 5Fh, Configuration Register 60h, Configuration Register 61h, Configuration Register 62h, Configuration Register 63h,
Default
Function This when selects base address DRAM size appropriate bank, specified above. This selects base address DRAM size. This selects base address DRAM size. This selects base address DRAM size. This selects base address DRAM size. This selects base address DRAM size. This selects base address DRAM size. This selects base address DRAM size.
DRAM Type (Registers 64h-67h) These registers identify types DRAM (EDO fast page mode; 32bit 64bit default); symmetric asymmetric) used each ROW. system BIOS should programmed accordingly. Register
Default
Function Reserved. When bank DRAM, this zero. When bank DRAM, this zero. When bank DRAM, this zero. When bank DRAM, this zero. When bank DRAM, this zero.
configured DRAM. Fast Page mode configured DRAM. Fast Page mode configured DRAM. Fast Page mode configured DRAM. Fast Page mode configured DRAM. Fast Page mode
Micro
Register
2051nt
Default
Function Reserved. When bank configured 32-bit DRAM. When bank configured 32-bit DRAM. When bank configured 32-bit DRAM. When bank configured 32-bit DRAM. When bank configured 32-bit DRAM.
Register
Default
Function Reserved. When one, bank configured 12x12 symmetric DRAM. When one, bank configured 12x12 symmetric DRAM. When one, bank configured 12x12 symmetric DRAM. When one, bank configured 12x12 symmetric DRAM. When one, bank configured 12x12 symmetric DRAM.
Register
Default
Function Reserved. When bank configured 12x9 asymmetric DRAM. When bank configured 12x9 asymmetric DRAM. When bank configured 12x9 asymmetric DRAM. When bank configured 12x9 asymmetric DRAM. When bank configured 12x9 asymmetric DRAM.
Micro
2051nt
DRAM Timing (Registers 6Bh) These registers provide configuration characteristics. Register
Default
Function Burst refresh precharge cycle width. Bits Cycle Width Burst refresh active cycle width. Bits Cycle Width When burst refresh will enabled. Burst refresh count select. Bits Burst Number
Micro
Register
2051nt
Default
Function precharge select Fast Page mode memory. Bits Precharge When delay time cycles read. When zero, delay cycles. When delay time cycles write. When zero, delay cycles. precharge select read cycle fast page mode DRAM. Bits Precharge width select read cycle fast page mode DRAM. Bits Width
Register
Default
Function Reserved. enable long precharge detection. When will activated cycle earlier read cycle. When will activated cycle earlier write cycle. When precharge will write back cycle. equals when zero. When precharge write cycle precharge when zero fast page mode DRAM. width select write cycle. Bits Width Write
Micro
Register
2051nt
Default
Function DRAM precharge read cycle. Bits Precharge DRAM width read cycle. Bits Width Reserved. This selects DRAM precharge write cycle. When equals equals when zero. DRAM width write cycle. Bits Width
Shadow Control (Registers 6Fh) Register
Default
Function When shadow write segment CC000-CFFFF enabled When shadow read segment CC000-CFFFF enabled. When shadow write segment C8000-CBFFF enabled. When shadow read segment C8000-CBFFF enabled. When shadow write segment C4000-C7FFF enabled. When shadow read segment C4000-C7FFF enabled. When shadow write segment C0000-C3FFF enabled. When shadow read segment C0000-C3FFF enabled.
Micro
Register
2051nt
Function When shadow write segment DC000-DFFFF enabled When shadow read segment DC000-DFFFF enabled. When shadow write segment D8000-DBFFF enabled. When shadow read segment D8000-DBFFF enabled. When shadow write segment D4000-D7FFF enabled. When shadow read segment D4000-D7FFF enabled. When shadow write segment D0000-D3FFF enabled. When shadow read segment D0000-D3FFF enabled.
Default
Register
Default
Function When shadow write segment EC000-EFFFF enabled When shadow read segment EC000-EFFFF enabled. When shadow write segment E8000-EBFFF enabled. When shadow read segment E8000-EBFFF enabled. When shadow write segment E4000-E7FFF enabled. When shadow read segment E4000-E7FFF enabled. When shadow read segment E0000-E3FFF enabled. When shadow read segment E0000-E3FFF enabled.
Register
Default
Function When shadow write segment FC000-FFFFF enabled When shadow read segment FC000-FFFFF enabled. When shadow write segment F8000-FBFFF enabled. When shadow read segment F8000-FBFFF enabled. When shadow write segment F4000-F7FFF enabled. When shadow read segment F4000-F7FFF enabled. When shadow write segment F0000-F3FFF enabled. When shadow read segment F0000-F3FFF enabled.
DRAM Bank Relocation (Registers 70h-72h) Register
Default
Function Reserved. DRAM bank relocation bank DRAM bank relocation bank DRAM bank relocation bank Reserved. DRAM bank relocation bank DRAM bank relocation bank DRAM bank relocation bank
Example: default, DRAM's banks relocated, i.e., bank stays bank bank stays bank etc. relocate bank bank Register 70h, 010.
Micro
Register
2051nt
Default
Function Reserved. These bits select DRAM bank relocation bank Reserved. These bits select DRAM bank relocation bank
Register
Default
Function When segment 80000 segment 90000 readabled. When segment 80000 segment 90000 writeabled. When segment 80000 segment 90000 cacheabled. Segment 80000h 90000h should always cacheable. When remap function will enabled. When latch will asserted clock earlier support earlier /CAS. These bits select DRAM bank relocation bank
Setup Register
Default
Function Reserved. zero will returned when these bits read. initialize space. When space will segment 30000h. When space will segment A0000h. When space will segment B0000h.
4.2.2 Cache Micro 2051nt control asynchronous, burst, pipeline burst SRAM. Register 74h-76h select configure application cache. Cache Type Register
Default
Function Reserved. When this enables TAG7. When Asynchronous SRAM cache selected. When non-pipe Burst SRAM cache selected. When Pipeline burst SRAM cache selected.
Micro
2051nt
Function When external will ignored When cache will always cache initialization. When zero, cache will always miss. When data cache will forced non-dirty state. This selects advanced cache clock (KCLK) writes cache (3ns-8ns faster). When write-back implementation selected. When zero, write-through selected. cache size select. Bits Cache Size 128K 256K 512K Undefined Undefined
Cache Initialization Register
Default
Burst Timing Cache Timing Register (for asynchronous cache)
Default
Function Reserved. When one, cache burst read cycle x-2-2-2. When zero, x-3-3-3 cache burst read selected. When one, cache burst write cycle x-2-2-2. When zero, x-3-3-3 cache burst write selected. Wait state select burst read lead-off cycle. Bits Lead-Off Cycle Reserved. 3-x-x-x 4-x-x-x 4-x-x-x Wait state select burst write lead-off cycle. Bits Lead-Off Cycle Reserved. 3-x-x-x 4-x-x-x 4-x-x-x
Micro
Register
2051nt
Shadow Cache Control (Registers 77h-78h)
Default
Function When shadow segment DC000-DFFFF cacheable. When shadow segment D8000-DBFFF cacheable. When shadow segment D4000-D7FFF cacheable. When shadow segment D0000-D3FFF cacheable. When shadow segment CC000-CFFFF cacheable. When shadow segment C8000-CBFFF cacheable. When shadow segment C4000-C7FFF cacheable. When shadow segment C0000-C3FFF cacheable.
Register
Default
Function When shadow segment FC000-FFFFF cacheable. When shadow segment F8000-FBFFF cacheable. When shadow segment F4000-F7FFF cacheable. When shadow segment F0000-F3FFF cacheable. When shadow segment EC000-EFFFF cacheable. When shadow segment E8000-EBFFF cacheable. When shadow segment E4000-E7FFF cacheable. When shadow segment E0000-E3FFF cacheable.
Micro
2051nt
Non-cacheable Range (Registers 79h-7Ch) These registers select lower address non-cacheable range range size. Non-cacheable Range Size Register
Default
Function This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range Sets non-cacheable range size follows: Bits Addr. Compared Non-cacheable Range Size 3210 0000 don't care cacheable (default) 0001 16-27 0010 17-27 128K 0011 18-27 256K 0100 19-27 512K 0101 20-27 0110 21-27 0111 22-27 1000 23-27 1001 24-27 1010 25-27 1011 26-27 1100 128M 1101-1111 Undefined Example: non-cacheable range size A20-A27 will used comparison addresses. non-cacheable range starts 16MB boundary, then base address needs one. base address below will treated 0's.
Non-cacheable Range Address Register
Default
Function This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range
Micro
Non-cacheable Range
2051nt
Non-cacheable Range Size Register
Default
Function This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range Sets non-cacheable range size follows: Bits Addr. Compared Non-cacheable Range Size 3210 0000 don't care cacheable (default) 0001 16-27 0010 17-27 128K 0011 18-27 256K 0100 19-27 512K 0101 20-27 0110 21-27 0111 22-27 1000 23-27 1001 24-27 1010 25-27 1011 26-27 1100 128M 1101-1111 Undefined Example: non-cacheable range size A20-A27 will used comparison addresses. non-cacheable range starts 16MB boundary, then base address needs one. base address below will treated 0's.
Non-cacheable Range Address Register
Default
Function This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range This selects starting base address non-cacheable range
Micro
Power Mangement
2051nt
Micro Power Management offers four operation modes: Fully-on, Suspend, Doze, Standby. Registers 80h, 81h, 82h, 83h, 84h, 85h, 86h, 87h, 88h, 89h, provide configuration options optimize power management features notebook applications. 4.3.1 Suspend Control (Registers 80h, 81h) When system enters suspend mode, i.e, auto suspend timer times-out (reg. refer page /SRBTN asserted, CPU, PCI, interfaces will driven that their devices powered-off programming registers 81h. Register Function Reserved. this along with one, 2051nt will drive output interface signals that CPU's power powered-off. this along with one, 2051nt will drive output interface signals that device's power powered-off. this along with one, 2051nt will drive output interface signals that device's power powered-off. When this Register 41h, one, power suspend enabled. Note: Register 80h-81h located north bridge. Since power management control block located south bridge, register (page should also configured control CPU, interfaces. Register
Default
Default
Function This selects refresh source DRAM when system suspend mode. this one, 32KHz clock source selected handle DRAM refresh. refresh request selected when this zero. this enable self-refresh DRAM where 32KHz clock will used handle DRAM refresh. this zero, /CAS before /RAS (normal DRAM) refresh will used. These bits select slow refresh rate during power-on suspend mode. Bits Slow Refresh Rate 15us (assuming 32KHz reference clock) 30us 60us 120us Reserved. Reserved internal testing. These bits select recovery time (resume) from suspend mode. Bits Recovery Time (assuming reference clock) 16ms 32ms 64ms
Micro
2051nt
Function Reserved. this when cache disabled, [6:0] becomes output signal (see Reg. 8Ah). When TAG7 becomes PWROUT4 (pin B10), output signal. value output Reg. 84h, Reserved. When /RAS3 becomes PWROUT2 (pin U3), output signal. value output Register 84h, When /RAS4 becomes PWROUT1 (pin U2), output signal. value output Register 84h, When KALE becomes PWROUT0 (pin E12), output signal. value output Register 84h,
Power Output Control Register
Default
Power Output Control Register This register control output level (0/1 off/ PWROUT [2.0] signals when system entered suspend mode. These signals used (with external power transistor) turn external device such CPU, PCI, power, etc. power-on default value PWROUT [2.0] signals (on).
Default
Function Reserved. zero. When register 80h, allow 2051nt drive output interface signals low, PWROUT2 signal becomes (off) when this one. When register 80h, allow 2051nt drive output interface signals low, PWROUT1 signal becomes (off) when this one. When register 80h, allow 2051nt drive output interface signals low, PWROUT0 signal becomes (off) when this one. Reserved. zero When register 80h, allow 2051nt drive output interface signals low, PWROUT2 signal becomes (off) when this one. When register 80h, allow 2051nt drive output interface signals low, PWROUT1 signal becomes (off) when this one. When register 80h, allow 2051nt drive output interface signals low, PWROUT0 signal becomes (off) when this one.
Power Output Control Register
Default
Function Reserved. zero. When Reg. 82h, [4:0] one, value output this bit. (Default Writing zero will make PWROUT4 equal zero. Reserved. zero. When Reg. 82h, [4:0] one, value output this bit. (Default Writing zero will make PWROUT2 equal zero. When Reg. 82h, [4:0] one, value output this bit. (Default Writing zero will make PWROUT1 equal zero. When Reg. 82h, [4:0] one, value output this bit. (Default Writing zero will make PWROUT0 equal zero.
Micro
2051nt
4.3.2 GPIO, General Purpose Control (Registers 85h-87h) GPIO [7:5] (pins B28, G27, G28) GPIO [2:0] (pins AJ11, AH11, AG11) general purpose pins. Their direction individually controlled Register 86h, bits [7:5], [2:0]. these bits indicates output. values output Register 85h, bits [7:5] bits [2:0]. While input mode, their values read Register 87h, bits [7:5] bits [2:0]. Register 85h, General Purpose Output Port
Default
Function value written this GPIO7 output pin. value written this GPIO6 output pin. value written this GPIO5 output pin. Reserved. value written this GPIO2 output pin. value written this GPIO1 output pin. value written this GPIO0 output pin.
Register 86h, General Purpose Port
Default
Function When this indicates GPIO7 output pin. GPIO7 becomes input. When this indicates GPIO6 output pin. GPIO6 becomes input. When this indicates GPIO5 output pin. GPIO5 becomes input. Reserved. When this indicates GPIO2 output pin. GPIO2 becomes input. When this indicates GPIO1 output pin. GPIO1 becomes input. When this indicates GPIO0 output pin. GPIO0 becomes input.
then then then
then then then
Register 87h, General Purpose Input Port
Default
Function state GPIO7 input read through this bit. state GPIO6 input read through this bit. state GPIO5 input read through this bit. Reserved. state GPIO2 input read through this bit. state GPIO1 input read through this bit. state GPIO0 input read through this bit.
Micro
2051nt
Status Input (register 88h-89h) status input register read only register. used read status other device time. Register
Default
Function Reserved. KCSTS [4:0] (/TAGWE, /TKA3, /TKA4, /KCS, /KOE). When cache disabled (Register 74h, bits 000), these input signals their values read from these bits accordingly).
Configuration Register
Default
Function KWSTS [7:0] /KWE [7:0]. When cache disabled (Register 74h, bits 000), these signals their values read from these bits accordingly).
Power Output Register
Default
Function TPWROUT [7:0] DTY, [6:0]. When Register 82h, DTY, [6:0] becomes output signals. values output bits accordingly.
Device Function Configuration Registers (PCI ISA):
Standard Ports Vendor Register (function 15-0
Default
10AA
Function Micro vendor Identification
Device Register (function 15-0
Default
5842
Function Micro device I.D.
Command Register (function 15-0
Default
000C
Function local specification command register. Only bits R/W.
Micro
15-0
2051nt
Status Register (function
Default
0400
Function local specification status register
Revision Register (function
Default
Function local specification revision register
Class Code Register (function 22-0
Default
060100
Function local specification class code register
Header Type Register (function
Default
Function local specification header type register
Interrupt Line Register (function
Default
Function local specification interupt line register
Interrupt Register (function
Default
Function local specification interrupt register
Note: other registers (PCI Standard) between read only with default value
Micro
2051nt
Interrupt Route Control Registers /INTA, /INTB, /INTC, /INTD
Default
Function /INT(A, interrupt routing enable. Reserved. /INT(A, interrupt routing select. Bits 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Routing Reserved Reserved Reserved IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Reserved IRQ9 IRQ10 IRQ11 IRQ12 Reserved IRQ14 IRQ15
Micro
Note:
2051nt
4.4.1 Memory Region This register sets memory range which MASTER memory cycles forwarded PCI. range from 0C0000h 0FFFFF accessed MASTER.
Register
Default
Function Reserved. enable segment 0B0000h Memory region. enable segment 0A0000h Memory region. enable 512K base memory option. (default 640K) Memory region select. Bits 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Memory Region Below Below Below Below Below Below Below Below Below Below Below Below Below Below Below Below
Setup Register
Default
Function Reserved. enable /ROMCS memory write. enable include address range FFFE0000-FFFEFFFF. enable include address range FFFD0000-FFFDFFFF. enable include address range FFFC0000-FFFCFFFF. enable include address range 000E0000-000EFFFF. enable include address range 000D0000-000DFFFF. enable include address range 000C0000-000CFFFF.
Micro
2051nt
Function this enable fast positive decode function. When this will defaulted slow positive decode. When this will positive decode. default subtractive decode when this When this 8237 controller will positive decode. 8237 default subtractive decode when this When this 8254 timer will positive decode. 8254 default subtractive decode when this When this 8259 interrupt controller will positive decode. 8259 default subtractive decode when this When this space will positive decode. space default subtractive decode when this Subtractive decode time selection. Bits Decode Time Slow Medium Fast
Decode Control Register
Default
Recovery Control Register
Default
Function Reserved. When this slow recovery time will selected. 16-bit recovery time selection. Recovery time 8-bit recovery time selection. Recovery time
Note: unit recovery MHz.
Micro
2051nt
Keyboard Control Register
Default
Function enable internal keyboard controller. disable internal keyboard controller mouse port, i.e, multiplex pins MSDATA becomes IRQ12, MSCLK becomes /KBCS This selects color/mono switch internal keyboard controller. enable refresh (default disable.) enable zero wait 16-bit cycle. This enable Device Function Default disabled. Reserved. Reserved.
Clock Control Register
Default
Function Keyboard clock source select. Bits Clock Source Clock divided Clock divided Clock divided Clock divided When this PCICLK CLKSRC divided PCICLK CLKSRC divided when clock source select. Bits 43210 0XXXX 11XXX 10000 10001 10010 10011 10100 10101 10110 10111 Clock Source X14M (default) PCICLK divided CLKSRC divided CLKSRC divided CLKSRC divided CLKSRC divided CLKSRC divided CLKSRC divided CLKSRC divided CLKSRC divided
Micro
2051nt
4.4.2 Programmable Chip Select (Register 6Ch-73h) Micro 2051nt provides four programmable chip select signals, PCS[3:0], support external devices. addresses PCSx decoded through register 6Ch-73h. Programmable Chip Select (PCS0) Register Note:
Default
Function When one, along with multiplex configuration Register bits [1:0], PCS0 (pin C29) logic enabled. This used qualify PCS0 with IOW. This used qualify PCS0 with IOR. This PCS0 address SA9. This PCS0 address SA8. This PCS0 address SA7. This PCS0 address SA6. This PCS0 address SA5.
both bits set, either will activate chip select. both bits programmable chip select will address decoding only, qualified with command. (Default)
Programmable Chip Select (PCS0) Register
Default
Function This PCS0 address SA4. This PCS0 address SA3. This PCS0 address SA2. This PCS0 address SA1. When this enables comparison with PCS0 SA4. When this enables comparison with PCS0 SA3. When this enables comparison with PCS0 SA2. When this enables comparison with PCS0 SA1.
Programmable Chip Select (PCS1) Register Note:
Default
Function When along with multiplex configuration register bits [3:2] [1:1], PCS1 (pin B29) logic enabled. This enables programmable chip select qualified with IOW. This enables programmable chip select qualified with IOR. This PCS1 address SA9. This PCS1 address SA8. This PCS1 address SA7. This PCS1 address SA6. This PCS1 address SA5.
both bits set, either will activate chip select. both bits programmable chip select will address decode only, qualified with command.
Micro
2051nt
Function This PCS1 address SA4. This PCS1 address SA3. This PCS1 address SA2. This PCS1 address SA1. When this enables comparison with PCS1 SA4. When this enables comparison with PCS1 SA3. When this enables comparison with PCS1 SA2. When this enables comparison with PCS1 SA1.
Programmable Chip Select (PCS1) Register
Default
Programmable Chip Select (PCS2) Register Note:
Default
Function When along with multiplex configuration register bits [4,3,2] [1,0,1], PCS2 (pin K28) logic enabled. This used qualify PCS2 with IOW. This used qualify PCS2 with IOR. This PCS2 address SA9. This PCS2 address SA8. This PCS2 address SA7. This PCS2 address SA6. This PCS2 address SA5.
both bits set, either will activate chip select. both bits programmable chip select will address decoding only, qualified with command. (Default)
Programmable Chip Select (PCS2) Register
Default
Function This PCS2 address SA4. This PCS2 address SA3. This PCS2 address SA2. This PCS2 address SA1. When this enables comparison with PCS2 SA4. When this enables comparison with PCS2 SA3. When this enables comparison with PCS2 SA2. When this enables comparison with PCS2 SA1.
Micro
Note:
2051nt
Programmable Chip Select (PCS3) Register
Default
Function When along with multiplex configuration register bits [4,0] [1,1], PCS3 (K29) logic enabled. This used qualify PCS3 with IOW. This used qualify PCS3 with IOR. This PCS3 address SA9. This PCS3 address SA8. This PCS3 address SA7. This PCS3 address SA6. This PCS3 address SA5.
both bits either will activate chip select. both bits programmable chip select will address decoding only, qualified with command. (Default)
Programmable Chip Select (PCS3) Register
Default
Function This PCS3 address SA4. This PCS3 address SA3. This PCS3 address SA2. This PCS3 address SA1. When this enables comparison with PCS3 SA4. When this enables comparison with PCS3 SA3. When this enables comparison with PCS3 SA2. When this enables comparison with PCS3 SA1.
Misc. Register
Default
Function Reserved. When read from instead (When Micro Super controller use.) enable /CLKRUN protocol. enable Mobile Serial Interrupt Protocol. enable Mobile Protocol.
/REQ /GNT Control Register (Mobile PC/PCI) Register
Default
Function /REQ1 /GNT1 control registers. /REQ0 /GNT0 control registers.
/REQ /GNT Control Register (Mobile PC/PCI) Register
Default
Function /REQ3 /GNT3 control registers. /REQ2 /GNT2 control registers.
Micro
2051nt
4.4.3 Positive Decoded (Registers 78h-7Dh) 2051nt allows peripherals' addresses configured positive decoded agents complete docking design. Docking Enable Peripherals (Positive Decode) Windows Register
Default
Function Reserved. When address 278h-27Fh 678h-67Bh (for LPT3) will positive decoded. When address 378-37F 778h-77Bh (for LPT2) will positive decoded. When address 3BCh-3BFh 7BCh-7BFh (for LPT1) will positive decoded. When address A79h Plug Play device) will positive decoded. When address 200h-207h (for Joystick) will positive decoded. When special cycle interrupt acknowledge cycle will claimed on-board block where interrupt controller resides. When Micro 2051nt will subtractive decode. Micro 2051nt defaulted subtractive decode when zero (Certain windows positive decode programming Registers 78h-7Dh).
Peripherals (Positive Decode) Windows Register
Default
Function When GCS3 will positive decoded. When GCS2 will positive decoded. When GCS1 will positive decoded. When GCS0 will positive decoded. When address 2E8h-2EFh (for decoded. When address 3E8h-3EFh (for decoded. When address 2F8h-2FFh (for decoded. When address 3F8h-3FFh (for decoded.
will positive will positive will positive will positive
Micro
2051nt
Peripherals (Positive Decode) Windows Register
Default
Function When address 092h (for Port will positive decoded. When address 060h 064h (for 8742) will positive decoded. When address 070h 078h 071h 079h (for RTC) will positive decoded. When address PCS1 (programmable chip select will positive decoded. When address PCS0 (programmable chip select will positive decoded. When address 370h-375h 377h (for secondary FDC) will positive decoded. When address 3F0h-3F5h 3F7h (for primary FDC) will positive decoded. When address 3E0h-3E1h (for PCMCIA device) will positive decoded.
Peripherals (Positive Decode) Windows Register
Default
Function When programmable memory range CC000h-CFFFFh will positive decoded. When programmable memory range C8000h-CBFFFh will positive decoded. When programmable memory range C4000h-C7FFFh will positive decoded. When programmable memory range C0000h-C3FFFh will positive decoded. When address 4D0h 4D1h (for edge/level select) will positive decoded. When address 0F2h 0F3h (for Micro configuration register setting) will positive decoded. When address 0F0h (for co-processor) will positive decoded. When address 061h (for Port will positive decoded.
Micro
2051nt
Peripherals (Positive Decode) Windows Register
Default
Function When programmable memory range EC000h-EFFFFh will positive decoded. When programmable memory range E8000h-EBFFFh will positive decoded. When programmable memory range E4000h-E7FFFh will positive decoded. When programmable memory range E0000h-E3FFFh will positive decoded. When programmable memory range DC000h-DFFFFh will positive decoded. When programmable memory range D8000h-DBFFFh will positive decoded. When programmable memory range D4000h-D3FFFh will positive decoded. When programmable memory range D0000h-D3FFFh will positive decoded.
Peripherals (Positive Decode) Windows Register
Default
Function peripheral positive decoded windows setting (for Sound Blaster). Bits Disable address 210h address 220h address 230h address 240h address 250h address 260h Disable When address 388h-38Bh (for synthesizer) will positive decoded. Peripheral Positive Decoded Windows setting (for Midi UART) Bits address 300h address 310h address 320h address 330h When Midi Uart positive decode window enabled. When address 201h (for audio setup base) will positive decoded.
Micro
2051nt
Device Function1 Configuration Register (IDE Interface):
Standard Ports Vendor Register (function 15-0
Default
10AA
Function Micro vendor identification
Device Register (function 15-0
Default
5842
Function Micro device I.D.
Command Register (function 15-0
Default
0000
Function local specification command register. Only bits R/W.
Status Register (function 15-0
Default
0280
Function local specification status register
Revision Register (function
Default
Function local specification revision register
Class Code Register (function 22-0
Default
010100
Function local specification class code register
Header Type Register (function
Default
Function local specification header type register
Interrupt Line Register (function
Default
Function local specification interupt line register
Interrupt Register (function
Default
Function local specification interrupt register
Note: other registers (PCI Standard) between read only with default value
Micro
2051nt
4.5.1 Control Register
Default
Function /DEVSEL fast timing. When zero /DEVSEL will asserted clocks after /FRAME asserted. When /DEVSEL will asserted clock after /FRAME asserted. Reserved. Read Prefetch Buffer select. Bits Prefetch Buffer (32/16 access) Disabled DWORD/WORD Deep DWORD/WORD Deep DWORD/WORD Deep enable posted write feature function. Fast 8-bit port timing. When zero, access 8-bit port will standard timing. When access 8-bit port will timing defined Reg. 43h. select address 170-177, 376h secondary IDE. select address 1F0-1F7, 3F6h primary IDE.
8-bit Timing Control, Recovery Time Command Width Register
Default
Function Command recovery time select 8-bit access. Bits 7654 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Recovery time (cycles)
Micro
2051nt
8-bit Timing Control, Recovery Time Command Width Register
Default
Function Command width select 8-bit access. Bits 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Command Width (cycles)
8-Bit Timing Control, Hold Time Setup Time Register
Default
Function Reserved. Data hold time 8-bit access select. Bits Hold Time (cycles) Address setup time 8-bit access select. Bits Setup Time (cycles)
Micro
2051nt
Primary Drive Timing Control, Command Width Registers (1F0, drive (1F0, drive (170, drive (170, drive
Default
Function width select primary (1F0) drives secondary (170) drives Bits Command Width 7654 (cycles) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 width select primary (1F0) drives secondary (170) drives Bits Command Width 3210 (cycles) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Micro
2051nt
Primary Drive Timing Control, Recovery Time Register (1F0, drive (1F0, drive (170, drive (170, drive
Default
Function recovery time primary (1F0) drive secondary (170) drives Bits Recovery time 7654 (cycles) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 recovery time primary (1F0) drive secondary (170) drives Bits 3210 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Recovery Time (cycles)
Micro
2051nt
Timing Control, Setup Time Register
Default
Function Address setup time secondary (170) drive Bits Setup Time (cycles) Address setup time secondary (170) drive Bits Setup Time (cycles) Address setup time primary (1F0), drive Bits Setup Time (cycles) Address setup time primary (1F0), drive Bits Setup Time (cycles)
Micro
2051nt
Timing Control, Hold Time Register
Default
Function Data hold time secondary (170) drive Bits Hold Time (cycles) Data hold time secondary (170) drive Bits Hold Time (cycles) Data hold time primary (1F0), drive Bits Hold Time (cycles) Data hold time primary (1F0), drive Bits Hold Time (cycles)
Micro
2051nt
Standard Configuration Registers (Power Management Mode): 4.6.1 System Management Interrupt (SMI) Enable Enable Register
Default
Function When this /SMI will generate when general purpose timer expired. /SMI will generated when general purpose timer expired this When this /ACPWR input cause occur. this then transitions /ACPWR input will cause SMI. When this will occur when emulate temperature (defined reg. 50h-53h) reached high limit. this then will generated when temperature reached high limit. When this (software) will occur. Writing this register 3Eh, will cause occur. When this EXTSMI[0.2] input pins cause SMI's occur. this then transitions EXTSMI[0. inputs will cause SMI's (which control register [0.2]. When this transition /SRBTN input bin, auto suspend timer expired (control register 40h,41h, 43h), battery timer expired (control register 45h) will cause SMI's occur. this SMI's will occur under suspend mode. When this will occur when global standby timer expired (control register 30h-35h). this will occur when global standby timer expired. When this SMI's will occur when local standby timer expired (control register 2Bh-2Eh). this will occur when local standby timer expired.
Source Register
Default
Function When read, indicates requested from serial mobile PCI. Reserved. When read, indicates generated from general purpose timer When read, indicates requested exit from GCS1 L.S. mode. When read, indicates requested enter GCS1 L.S. mode. When read, indicates requested exit from GCS0 L.S. mode. When read, indicates requested enter GCS0 L.S. mode.
Source Register
Default
Function When read, indicates requested from /SRBTN input pin. When read, indicates requested from /BATLOW0 input pin. When read, indicates requested exit from auto Suspend mode. When read, indicates requested enter auto Suspend mode. When read, indicates requested exit from mode. When read, indicates requested enter G.S. mode. When read, indicates requested exit from L.S. mode. When this enables request enter LCD's L.S. mode.
Micro
2051nt
Source Register
Default
Function When read, indicates requested from temperature controller (high limit). When read, indicates requested from temperature controller (low limit). When read, indicates requested from high transition ACPWR input pin. When read, indicates requested from high transition ACPWR input pin. When read, indicates requested from /EXTSMI2 input pin. When read, indicates requested from /EXTSMI1 input pin. When read, indicates requested from /EXTSMI0 input pin. When read, indicates requested from software SMI.
Global Control Register
Default
Function When one, power management control timer will switch from (14.318MHz) external 32KHz (input Y29) clock source. When this disables trigger sources auto suspend timer/battery global standby system event timer. These bits used select function multiplexed C29. Bits Function Power Control (default) /LTCH0 (for power control 0-7) /PCS0 (programmable chip select Reserved. These bits used select function multiplexed B29. Bits Function Power Control (default) /LTCH1 (for power control 8-15) /DOZE (pin) /PCS1 (programmable chip select This used select function multiplexed C28. When EXTSYS, external system event input pin. When becomes external sensor input pin, i.e., when this asserted (from external source such thermal sensor) throttle mode will enabled automatically. When occurs, 2051nt will keep /SMI signal until clear. Therefor this needs before jumping handler allow another service.
Micro
2051nt
Global Control Register
Default
Function power suspend, CPU, PCI, interface will driven (refer register 41h) that their power turn off. Micro 2051nt will generate CPURST upon resume. Therefore this used select reset period upon resume from power-on suspend. Bits Reset Period (default) Function multiplexed DACKx/PWRx When one, DACK7 becomes PWR9, DACK6 becomes PWR8, DACK3 becomes PWR7, DACK1 becomes PRW6, DACK0 becomes PWR5. These bits select function multiplexed K28. Bits Function power control (default) /SMEMR /PCS2 other Reserved When PWR3 output becomes SYSCLK. These bits select function multiplexed K29. Bits Function PWR2 (default) /SMEMW /PCS3 other Reserved
4.6.2 VRAM Range Registers (8h, Register
Default
Function This selects VRAM range. This selects VRAM range. This selects VRAM range. This selects VRAM range. This selects VRAM range. This selects VRAM range. This selects VRAM range. This selects VRAM range.
Micro
Register
2051nt
Default
Function Reserved. This selects VRAM range. This selects VRAM range. This selects VRAM range. This selects VRAM range. This selects VRAM range. This selects VRAM range. This selects VRAM range.
VRAM Range Control Register
Default
Function Reserved. VRAM size select. Addr. Compared 3210 0000 Disable VRAM range 0001 A17-A31 0010 A18-A31 0011 A19-A31 0100 A20-A31 0101 A21-A31 0110 A22-A31 0111 A23-A31 1000 A24-A31 1001 A25-A31 1010 A26-A31 1011 A27-A31 1100 A28-A31 1101 A29-A31 1110 A30-A31 1111
VRAM Size
128K 256K 512K 128M 256M 512M
PWRC0 Register
Default
Function When this enables power control When this enables power control When this enables power control When this enables power control When this enables power control When this enables power control When this enables power control When this enables power control
Micro
PWRC1 Register
2051nt
Default
Function When this enables power control When this enables power control When this enables power control When this enables power control When this enables power control When this enables power control When this enables power control When this enables power control
Note: Power Control external latch required along with latch control signal provide eight power control signals. Scratch Registers Micro 2051nt contains 8-bits scratch registers which used software purposes (for example, used save some flags these registers instead system RAM). 4.6.3 Doze Mode Three timers used monitor activities IRQ0 IRQ8, VRAM access, system events doze mode. When these timers expired, /STPCLK will generated stop grant state. Doze Mode Control Register
Default
Function When this increases time-out period VRAM doze timer factor When this enables DOZE mode state machine. When this IRQ8 will affect timers [3:1]. When this IRQ0 will affect timers [3:1]. Time-out period selection IRQ0/8 doze timer. Bits Time-out Period (Doze timer will never expire). Reserved.
Note:* When both IRQ8 IRQ0 disabled (bit [5:4] equal system will, depending system event VRAM doze timer (register [6:4] 2:0]), enter doze mode.
Micro
2051nt
Doze Mode Control Register
Default
Function When this VRAM doze timer will by-passed. system depends register [3:1] register [2:0] enter doze mode. Timeout period selection VRAM doze timer. Bits (Doze timer will never expire). When this System Event doze timer will by-passed. system depends register [3:1] register [6:4] enter doze mode Timeout period selection SYSTEM EVENT doze timer. Bits (Doze timer will never expire) 1/32 sec. 2/32 sec. 3/32 sec. 4/32 sec. 5/32 sec. 6/32 sec. 7/32 sec.
Register
Default
Function Reserved. When this increases timeout period system event Doze timer factor When this increases timeout period Doze timer factor
Micro
2051nt
Doze Mode System Event Timer Trigger Source (Registers 13h-16h) there activity selected trigger source, Doze Mode System Event timer will reset recounted again. Source Register
Default
Function When this IRQ10 will selected trigger source. When this IRQ9 will selected trigger source. When this IRQ7 will selected trigger source. When this IRQ6 will selected trigger source. When this IRQ5 will selected trigger source. When this IRQ4 will selected trigger source. When this IRQ3 will selected trigger source. When this IRQ1 will selected trigger source.
Source Register
Default
Function Reserved. When this EXTSYS input will selected trigger source. When this requested will selected trigger source. When this IRQ15 will selected trigger source. When this IRQ14 will selected trigger source. When this IRQ13 will selected trigger source. When this IRQ12 will selected trigger source. When this IRQ11 will selected trigger source.
Source Register
Default
Function When this address will selected trigger source. When this address will selected trigger source. When this adddress will selected trigger source. When this hard disk access will selected trigger source. When this GCS3 will selected trigger source. When this GCS2 will selected trigger source. When this GCS1 will selected trigger source. When this GCS0 will selected trigger source.
Source Register
Default
Function When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source.
Micro
2051nt
Function Reserved. Timeout period select warning timer. Default Bits 3210 (the warning timer will never expire)
4.6.4 Warning Timer Count Register
Default
Warning Timer Bypass Register
Default
Function When this Micro 2051nt will generate /SMI active state ACPWR right away instead waiting warning timer expire before generate /SMI. When this Micro 2051nt will generate /SMI upon emulate temperature reached high/low limit (defined reg. 50h-53h) right away instead waiting warning timer expire before generate /SMI. When this Micro 2051nt will generate /SMI active state software right away instead waiting warning timer expire before generate /SMI. When this Micro 2051nt will generate /SMI active state EXTSMI2 right away instead waiting warning timer expire before generate /SMI. When this Micro 2051nt will generate /SMI active state EXTSMI1 right away instead waiting warning timer expire before generate /SMI. When this Micro 2051nt will generate /SMI active state EXTSMI0 right away instead waiting warning timer expire before generate /SMI. When this Micro 2051nt will generate /SMI upon /BATLOW0 timer expired right away instead waiting warning timer expire before generate /SMI. When this Micro 2051nt will generate /SMI active state /SRBNT right away instead waiting warning timer expire before generate /SMI.
Micro
Register
2051nt
Warning Trigger Bypass
Default
Function Reserved. When this Micro 2051nt will generate /SMI upon general purpose timer expired right away instead waiting warning timer expire before generate /SMI.
Warning Timer Trigger Source (Registers 1Bh-1Eh) there activity selected trigger source, warning timer will reset re-count again. Source Register
Default
Function When this IRQ10 will selected trigger source. When this IRQ9 will selected trigger source. When this IRQ7 will selected trigger source. When this IRQ6 will selected trigger source. When this IRQ5 will selected trigger source. When this IRQ4 will selected trigger source. When this IRQ3 will selected trigger source. When this IRQ1 will selected trigger source.
Source Register
Default
Function Reserved. When this EXTSYS input will selected trigger source. When this requests will selected trigger source. When this IRQ15 will selected trigger source. When this IRQ14 will selected trigger source. When this IRQ13 will selected trigger source. When this IRQ12 will selected trigger source. When this IRQ11 will selected trigger source.
Micro
2051nt
Source Register
Default
Function When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this hard disk access will selected trigger source. When this GCS3 will selected trigger source. When this GCS2 will selected trigger source. When this GCS1 will selected trigger source. When this GCS0 will selected trigger source.
Source Register
Default
Function When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source. When this address will selected trigger source.
4.6.5 General Chip Select (Registers 20h-29h) Local Standby Control Register
Default
Function Reserved. When active state programmable GCS1 will cause occur. will occur this When active state programmable GCS0 will cause occur. will occur this active GCS1 state machine. When this GCS1 function will disabled. active GCS0 state machine. When this GCS0 function will disable.
Micro
2051nt
GCS0 Byte Address Register
Default
Function When this enables SA7. When this enables SA6. When this enables SA5. When this enables SA4. When this enables SA3. When this enables SA2. When this enables SA1. When this enables SA0.
GCS0 High Byte Address Register
Default
Function When this enables read. When this enables write. When this masks SA3. When this masks SA2. When this masks SA1. When this masks SA0. When this enables SA9. When this enables SA8.
GCS1 Byte Address Register
Default
Function When this enables SA7. When this enables SA6. When this enables SA5. When this enables SA4. When this enables SA3. When this enables SA2. When this enables SA1. When this enables SA0.
GCS1 High Byte Address Register
Default
Function When this enables read. When this enables write. When this masks SA3. When this masks SA2. When this masks SA1. When this masks SA0. When this enables SA9. When this enables SA8.
Micro
2051nt
GCS2 Byte Address Register
Default
Function When this enables SA7. When this enables SA6. When this enables SA5. When this enables SA4. When this enables SA3. When this enables SA2. When this enables SA1. When this enables SA0.
GCS2 High Byte Address Register
Default
Function When this enables read. When this enables write. When this masks SA3. When this masks SA2. When this masks SA1. When this masks SA0. When this enables SA9. When this enables SA8.
GCS3 Byte Address Register
Default
Function When this enables SA7. When this enables SA6. When this enables SA5. When this enables SA4. When this enables SA3. When this enables SA2. When this enables SA1. When this enables SA0.
GCS3 High Byte Address Register
Default
Function When this enables read. When this enables write. When this masks SA3. When this masks SA2. When this masks SA1. When this masks SA0. When this enables SA9. When this enables SA8.
Micro
General Chip Select
2051nt
GCS0 GCS1 Count Register
Default
Function Timeout period selection GCS1 local standby idle timer Bits 7654 (GCS1 timer will never expire) Timeout period selection GCS0 local standby idle timer Bits 3210 (GCS0 timer will never expire)
Micro
2051nt
GCS2 GCS3 Count Register
Default
Function Timeout period selection GCS3 local standby idle timer Bits 7654 Disable Timeout period selection GCS2 local standby idle timer Bits 3210 Disable
Micro
2051nt
4.6.6 Local Standby Control Register
Default
Function Reserved When this disables VRAM (LCD VRAM idle timer will always timed out, irrespective programmed count). When this IRQ12 will selected trigger source keyboard idle timer. When this IRQ4 will selected trigger source keyboard idle timer. When this IRQ3 will selected trigger source keyboard idle timer. When this IRQ1 will selected trigger source keyboard idle timer. local standby state machine enabled when this
Local Standby Control Register
Default
Function Reserved. When this selects VRAM write break event. When this selects IRQ12 break event. When this selects IRQ4 break event. When this selects IRQ3 break event. When this selects IRQ1 break event. When this activity selected break event will cause exit local standby occur. this /SMI will assert when break event occur. Therefore system will always stays standby mode.
Micro
2051nt
Keyboard VRAM Count Register
Default
Function Timeout period selection keyboard idle timer Bits 7654 (LCD keyboard idle timer will never expire) Timeout period selection VRAM idle timer. Bits 3210 (LCD VRAM idle timer will never expire) sec. sec. sec. sec. sec. sec. sec. sec. sec. sec. sec. sec. sec. sec.
Micro
2051nt
Function Reserved When this VRAM write will selected break event. When this global standby VRAM timer will by-passed. system will depend global standby system event timer enter global standby mode. When this system will enter standby mode when both VRAM system event timers expired. When this transition selected global standby break event will cause occur. this /SMI will assert when break event occur.
Global Standby Control Register
Default
Global Standby System Event VRAM Count Register
Default
Function Timeout period selection Global Standby system event idle timer Bits 7654 (system event timer will never expire) Timerout period selection Global Standby VRAM idle timer. Bits 3210 (VRAM timer will never expire) sec. sec. sec. sec. sec. sec. sec. sec. sec. sec. sec. sec. sec. sec.
Micro
2051nt
Global Standby System Event Timer Trigger Source (Register 32h-35h) there activity selected trigger source, global standby system event timer will reset recount again. Source Register
Default
Function When IRQ10 will selected trigger source G.S. system event timer. When IRQ9 will selected trigger source G.S. system event timer. When IRQ7 will selected trigger source G.S. system event timer. When IRQ6 will selected trigger source G.S. system event timer. When IRQ5 will selected trigger source G.S. system event timer. When IRQ4 will selected trigger source G.S. system event timer. When IRQ3 will selected trigger source G.S. system event timer. When IRQ1 will selected trigger source G.S. system event timer.
Source Register
Default
Function Reserved. When EXTSYS input will selected trigger source G.S. system event timer. When request will selected trigger source G.S. system event timer. When IRQ15 will selected trigger source G.S. system event timer. When IRQ14 will selected trigger source G.S. system event timer. When IRQ13 will selected trigger source G.S. system event timer. When IRQ12 will selected trigger source G.S. system event timer. When IRQ11 will selected trigger source G.S. system event timer.
Micro
2051nt
Global Standby System Event Timer Trigger Source Source Register
Default
Function When base address 278h will selected trigger source G.S. system event timer. When base address 240h selected trigger source G.S. system event timer. When base address 220h will selected trigger source G.S. system event timer. When (base address 1F0h 170h) will selected trigger source G.S. system event timer. When GCS3 will selected trigger source G.S. system event timer. When GCS2 will selected trigger source G.S. system event timer. When GCS1 will selected trigger source G.S. system event timer. When GCS0 will selected trigger source G.S. system event timer.
Global Standby System Event Timer Trigger Source Source Register
Default
Function When base address 3F8h will selected trigger source system event timer. When base address 3E8h will selected trigger source system event timer. When base address 3BCh will selected trigger source system event timer. When base address will selected trigger source system event timer. When base address will selected trigger source system event timer. When base address will selected trigger source system event timer. When base address will selected trigger source system event timer. When base address will selected trigger source system event timer.
G.S. G.S. G.S. G.S. G.S. G.S. G.S. G.S.
Micro
2051nt
Global Standby Break Event (Registers 37h-3Ah) Break Register
Default
Function When IRQ10 will selected G.S. break event When IRQ9 will selected G.S. break event When IRQ7 will selected G.S. break event When IRQ6 will selected G.S. break event. When IRQ5 will selected G.S. break event When IRQ4 will selected G.S. break event When IRQ3 will selected G.S. break event When IRQ1 selected G.S. break event
Break Register
Default
Function Reserved. When EXTSYS will selected G.S. break event. When request will selected G.S. break event. When IRQ15 will selected G.S. break event. When IRQ14 will selected G.S. break event. When IRQ13 will selected G.S. break event. When IRQ12 will selected G.S. break event. When IRQ11 will selected G.S. break event.
Break Register
Default
Function When base address 278h will selected G.S. break event. When base address 240h will selected G.S. break event. When base address 220h will selected G.S. break event. When (base address 1F0h 170h) will selected G.S. break event. When base address GCS3 will selected G.S. break event When base address GCS2 will selected G.S. break event When base address GCS1 will selected G.S. break event. When base address GCS0 will selected G.S. break event.
Global Standby Break Event Break Register
Default
Function When base address 3F8h will selected G.S. break event. When base address 3E8h will selected G.S. break event. When base address 3BCh will selected G.S. break event. When base address will selected G.S. break event. When base address will selected G.S. break eve
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