128Kx8 Super Power Voltage CMOS Static CMOS SRAM Revision Hi

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128Kx8 Super Power Voltage CMOS Static CMOS SRAM Revision Hi

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K6F1008V2C Family
128Kx8 Super Power Voltage CMOS Static
CMOS SRAM
Revision History
Revision
History
Initial Draft Revise Changed Package Type 48(36)-TBGA-6.00x7.00 32-TSOP1-0813.4F Finalize
Draft Data
November 2001 December 2001
Remark
Preliminary Preliminary
June 2002
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves right change specifications products. SAMSUNG Electronics will answer your questions. have questions, please contact SAMSUNG branch offices.
Revision June 2002
K6F1008V2C Family
CMOS SRAM
128Kx8 Super Power Voltage CMOS Static
FEATURES
GENERAL DESCRIPTION
K6F1008V2C families fabricated SAMSUNGs advanced full CMOS process technology. families support industrial temperature range have various package types user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
Process Technology: Full CMOS Organization: 128K Power Supply Voltage: 3.0~3.6V Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 32-TSOP1-0813.4F
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed Standby (ISB1, Typ.) 0.5µA2) Operating (ICC1, Max) Type
K6F1008V2C-F
Industrial(-40~85°C)
3.0~3.6V
551)/70ns
32-TSOP1-0813.4F
parameter measured with 30pF test load. Typical values measured VCC=3.3V, TA=25°C 100% tested.
DESCRIPTION
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
32-sTSOP Type1-Forward
select
Memory array 1024 rows columns
I/O1 I/O8
Data cont
Circuit Column select
Data cont
Name
Function
Name
Function
CS1, Chip Select Inputs A0~A16 Output Enable Input Write Enable Input Address Inputs
I/O1~I/O8 Data Inputs/Outputs Power Ground Connection
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision June 2002
K6F1008V2C Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F1008V2C-YF55 K6F1008V2C-YF70 Function
CMOS SRAM
32-sTSOP1-F, 55ns, 3.3V 32-sTSOP1-F, 70ns, 3.3V
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout
Mode Deselected Deselected Output Disabled Read Write
Power Standby Standby Active Active Active
means dont care (Must high states)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT TSTG Ratings -0.2 VCC+0.3V -0.2 4.0V Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted within recommended operating condition. Exposure absolute maximum rating conditions extended period affect reliability.
Revision June 2002
K6F1008V2C Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage
Note TA=-40 85°C, otherwise specified Overshoot: Vcc+2.0V case pulse width 20ns. Undershoot: -2.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
CMOS SRAM
Symbol
-0.3
Vcc+0.3
Unit
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Average operating current Symbol ICC1 ICC2 Output voltage Output high voltage Standby Current(CMOS) ISB1 VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL, VIO=Vss
Cycle time=1µs, 100%duty, IO=0mA, 0.2V, Vcc-0.2V, IN0.2V VINVCC-0.2V Cycle time=Min, 100% duty, IIO=0mA, =VIL, CS2=VIH, VIN=VIH
Test Conditions
Unit
IOL=2.1mA IOH=-1.0mA CS1Vcc-0.2V, CS2Vcc-0.2V CS20.2V, Other inputs=0~Vcc
Typical values measured VCC=3.3V, TA=25°C 100% tested. Super power product=1µA with special handling.
Revision June 2002
K6F1008V2C Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Test Input/Output Reference)
Input pulse level: 2.2V Input rising falling time: Input output reference voltage: 1.5V Output load (See right): 100pF+1TTL 30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance R1=3070, =3150 V=2.8V
CHARACTERISTICS (Vcc=3.0~3.6V, Industrial product:TA=-40 85°C)
Speed Bins Parameter List Symbol Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Read Chip Select Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Write Cycle Time Chip Select Write Address Set-up Time Address Valid Write Write Write Pulse Width Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z
parameter measured with 30pF test load.
55ns
70ns
Units
tOLZ tOHZ tWHZ
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR CS1Vcc-0.2V
Test Condition
Unit
Vcc=1.5V, CS1Vcc-0.2V1) data retention waveform
Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) CS20.2V(CS2 controlled)
Revision June 2002
K6F1008V2C Family
TIMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
Address Data Previous Data Valid
CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than (Min.) both given device from device device interconnection.
Revision June 2002
K6F1008V2C Family
TIMING WAVEFORM WRITE CYCLE(1)
Controlled)
CMOS SRAM
Address tCW(2) tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
TIMING WAVEFORM WRITE CYCLE(2) (CS1
Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision June 2002
K6F1008V2C Family
TIMING WAVEFORM WRITE CYCLE(3) (CS2 Controlled)
Address tAS(3) tCW(2) tWP(1) Data Data Valid tCW(2) tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap high write begins latest transition among going low, going high going write ends earliest transition among going high, going going high, measured from begining write write. measured from going from going high write. measured from address valid beginning write. measured from write address change. tWR1 applied case write ends with going high tWR2 applied case write ends with going low.
DATA RETENTION WAVE FORM
controlled
3.0V tSDR Data Retention Mode tRDR
2.2V CS1VCC 0.2V
controlled
3.0V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision June 2002
K6F1008V2C Family
PACKAGE DIMENSIONS
THIN SMALL OUTLINE PACKAGE TYPE (0813.4F)
CMOS SRAM
Units: millimeters(inches)
0.20 0.008
+0.10 -0.05 +0.004 -0.002
13.40 ±0.20 0.528 ±0.008
0.10 0.004
8.40 0.331 8.00 0.315
0.25 0.010
0.50 0.0197
1.00 ±0.10 0.039 ±0.004
0.25 0.010
11.80 ±0.10 0.465 ±0.004
+0.10 -0.05 0.006 +0.004 -0.002
0.15
0.05 0.002 1.20 0.047
0.45~0.75 0.018~0.030
0.50 0.020
Revision June 2002

128Kx8 Super Power Voltage CMOS Static CMOS SRAM Revision Hi

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