Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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K6F1616T6B Family
Super Power Voltage Full CMOS Static
CMOS SRAM
Revision History
Revision History
Initial draft Revised Changed Isb1(max.) from 25uA 15uA Finalized Added Package Type '48-TBGA 7.00x7.00'
Draft Date
2003 June 2003
Remark
Preliminary Preliminary
August 2003
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision August 2003
K6F1616T6B Family
FEATURES
Process Technology: Full CMOS Organization: Power Supply Voltage: 2.7~3.6V Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 48-TSOP1-1220F, 48-TBGA 7.00x7.00
CMOS SRAM
GENERAL DESCRIPTION
K6F1616T6B families fabricated SAMSUNGs advanced full CMOS process technology. families support industrial operating temperature ranges. families also support data retention voltage battery back-up operation with data retention current.
Super Power Voltage Full CMOS Static
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed Standby (ISB1, Typ.) 5µA2) Operating (ICC1, Max) Type 48-TSOP1-1220F 48-TBGA 7.00x7.00
K6F1616T6B-F
Industrial(-40~85°C)
2.7~3.6V
551)/70ns
parameter measured with 30pF test load. Typical value measured VCC=3.3V, TA=25°C 100% tested.
DESCRIPTION
I/O16 I/O8 I/O15 I/O7 I/O14 I/O6 I/O13 I/O5 I/O12 I/O4 I/O11 I/O3 I/O10 I/O2 I/O9 I/O1
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
Addresses
48-TSOP1-1220F
select
Memory Cell Array
I/O1~I/O8
Data cont Data cont Data cont
Circuit Column select
I/O9~I/O16
Column Addresses
I/O9
I/O1
I/O10
I/O11
I/O2
I/O3
Control Logic
I/O12
I/O4
I/O13
I/O5
Name
I/O15 I/O14 I/O6 I/O7
Function
Name
Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) Connection
CS1, Chip Select Inputs Output Enable Input Write Enable Input Address Inputs
I/O16
I/O8
A0~A19
I/O1~I/O16 Data Inputs/Outputs
48-TBGA: View (Ball Down)
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision August 2003
K6F1616T6B Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F1616T6B-TF55 K6F1616T6B-TF70 K6F1616T6B-EF55 K6F1616T6B-EF70 Function
CMOS SRAM
48-TSOP1-1220F, 55ns, 3.0V/3.3V 48-TSOP1-1220F, 70ns, 3.0V/3.3V 48-TBGA, 55ns, 3.0V/3.3V 48-TBGA, 70ns, 3.0V/3.3V
FUNCTIONAL DESCRIPTION
I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Standby Active Active Active Active Active Active Active Active
means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT TSTG Ratings -0.2 VCC+0.3V(Max. 4.2V) -0.2 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision August 2003
K6F1616T6B Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol -0.23) 3.0/3.3
CMOS SRAM
Vcc+0.22) Unit
Note: TA=-40 85°C, otherwise specified Overshoot: VCC+2.0V case pulse width 20ns. Undershoot: -2.0V case pulse width 20ns. Overshoot Undershoot sampled, 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current
Symbol
Test Conditions VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL LB=UB=VIH, VIO=Vss Cycle time=1µs, 100%duty, IIO=0mA, CS10.2V, LB0.2V or/and UB0.2V, CS2Vcc-0.2V, VIN0.2V VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL 2.1mA -1.0mA Other input =0~Vcc CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0VCS20.2V(CS2 controlled) 70ns 55ns
Typ1)
Unit
ICC1
Average operating current ICC2 Output voltage Output high voltage Standby Current (CMOS) ISB1
Typical values measured VCC=3.3V, TA=25°C 100% tested.
Revision August 2003
K6F1616T6B Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Input/Output Reference)
Input pulse level: 0.2V Vcc-0.2V Input rising falling time: Input output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance R1=3070, R2=3150 V=2.8V
CHARACTERISTICS (Vcc=2.7~3.6V, TA=-40 85°C)
Speed Bins Parameter List Symbol Read cycle time Address access time Chip select output Output enable valid output valid data output Read Chip select low-Z output Output enable low-Z output enable low-Z output Output hold from address change Chip disable high-Z output disable high-Z output disable high-Z output Write cycle time Chip select write Address set-up time Address valid write Write pulse width Write Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z valid write tOLZ tBLZ tOHZ tBHZ tWHZ 55ns 70ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V VIN0V
1.02)
Unit
Vcc=1.5V, CS1Vcc-0.2V1), VIN0V data retention waveform
CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0CS20.2V(CS2 controlled) Typical value measured TA=25°C 100% tested.
Revision August 2003
K6F1616T6B Family
TIMING DIAGRAMS
CMOS SRAM
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, or/and LB=VIL)
Address Data Previous Data Valid Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address
tBHZ tOLZ tBLZ Data
High-Z
tOHZ Data Valid
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision August 2003
K6F1616T6B Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWR(4)
CMOS SRAM
tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid High-Z
TIMING WAVEFORM WRITE CYCLE(2) (CS1 Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision August 2003
K6F1616T6B Family
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends with going high.
DATA RETENTION WAVEFORM
controlled
2.7V tSDR Data Retention Mode tRDR
2.2V CS1VCC 0.2V
controlled
2.7V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision August 2003
K6F1616T6B Family
PACKAGE DIMENSIONS
48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) TSOP1 1220F
CMOS SRAM
Unit :mm/Inch
20.00±0.20 0.787±0.008
0.008-0.001
+0.07
+0.003
0.20 -0.03
0.25 0.010 12.40 0.488
0.50 0.0197
1.00±0.05 0.039±0.002 1.20 0.047MAX 0.05 0.002
0.25 0.010
0.125 -0.035
0~8'C
0.45~0.75 0.018~0.030
0.50 0.020
0.005-0.001
+0.003
18.40±0.10 0.724±0.004
+0.075
12.00 0.472
August 2003
0.10 0.004
Revision
K6F1616T6B Family
PACKAGE DIMENSION
BALL TAPE BALL GRID ARRAY(0.75mm ball pitch)
View Bottom View
CMOS SRAM
Unit: millimeters
C1/2
B1/2
Side View
Detail
0.35/Typ.
6.90 6.90 0.40 0.80 0.30
0.75 7.00 3.75 7.00 5.25 0.45 0.90 0.55 0.35
7.10 7.10 0.50 1.00 0.40 Notes. Bump counts: 48(8 column) Bump pitch: (x,y)=(0.75 0.75)(typ.) tolerence ±0.050 unless otherwise specified. Typ: Typical coplanarity: 0.1(Max)
0.55/Typ.
Revision August 2003

Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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