DRIVER CONTROLLER Mar. 2001. Ver. Contents this document sub

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S6B0728
DRIVER CONTROLLER
Mar. 2001. Ver.
Contents this document subject change without notice. part this document reproduced transmitted form means, electronic mechanical, purpose, without express written permission Driver Team. Precautions Light Light characteristics move electrons integrated circuitry semiconductors, therefore change characteristics semiconductor devices when irradiated with light. Consequently, users packages which expose chips external light such COB, COG, must consider effective methods block light from reaching parts surface area, top, bottom sides chip. Follow precautions below when using products. Consider verify protection penetrating light substrate board glass) product design stage. Always test inspect products under environment with penetration light.
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
S6B0728 Specification Revision History Version Change Reference Instruction Setup Flow (refer page Figure Change voltage range Description.(refer page page Original Change supply voltage(VDD) range (2.4 3.6) (refer page Change absolute voltage range VOUT (refer page Change characteristics VOUT, (refer page Change power save mode current power consumption (refer page1) Change charateristics Define value.(refer page Change charateristics Define value.(refer page Change characteristics IDD2,IDDS2 150uA 200uA, 10uA 20uA (refer page Insert Rb/Ra ratio (refer page Change power save mode current condition power consumption (refer page1) Bump align description added (refer page Interface protocol 8080 6800 mode diagram added (refer page Re-sort figure number. Mar.2001 Mar.2000 Jan.2001 Jun.2000 Content Date Sep.1999
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
CONTENTS
INTRODUCTION BLOCK DIAGRAM CONFIGURATION CENTER COORDINATES DESCRIPTION FUNCTIONAL DESCRIPTION MICROPROCESSOR INTERFACE DISPLAY DATA (DDRAM) DISPLAY CIRCUITS DRIVER CIRCUIT POWER SUPPLY CIRCUITS REFERENCE CIRCUIT EXAMPLES.27 RESET CIRCUIT INSTRUCTION DESCRIPTION SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS CHARACTERISTICS CHARACTERISTICS REFERENCE APPLICATIONS MICROPROCESSOR INTERFACE CONNECTIONS BETWEEN S6B0728 PANE
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
INTRODUCTION
S6B0728 driver controller graphic dot-matrix liquid crystal display systems. contains common segment driver circuits. connected directly microprocessor, accepts serial 8-bit parallel display data stores on-chip display data bits. provides highly flexible display section 1-to-1 correspondence between on-chip display data bits panel pixels. performs display data read/write operation with external-operating clock minimize power consumption. addition, because contains power supply circuits necessary drive liquid crystal, possible make display system with fewest components.
FEATURES
Driver Output Circuits common outputs segment outputs
Applicable Duty-ratios Programmable duty ratio 1/16 1/128 Various partial display Partial window moving data scrolling Applicable bias 1/12 Maximum display area
On-chip Display Data Capacity: 16,896 bits data "1": display illuminated data "0": display illuminated
Microprocessor Interface 8-bit parallel bi-directional interface with 6800-series 8080-series Serial interface(only write operation) with 4-pin 3-pin SPI(Serial Peripheral Interface)
On-chip Power Analog Circuit On-chip oscillator circuit Voltage converter (x3, Voltage regulator (temperature coefficient: -0.05%/°C external input) On-chip electronic contrast control function steps) Voltage follower (LCD bias: 1/12)
Operating Voltage Range Supply voltage DD): driving voltage VSS): 15.0 Typ. boosting, 13V, Internal power supply display OFF) Max. (during power save [standby] mode
Power Consumption
Package Type Gold bumped chip
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
BLOCK DIAGRAM
COM127 COM126 SEG131 SEG130 SEG129 SEG2 SEG1 SEG0 COM1 COM0
SEGMENT DRIVER CIRCUITS
COMMON DRIVER CIRCUITS
SEGMENT CONTROLLER
COMMON CONTROLLER
CIRCUIT PAGE ADDRESS CIRCUIT INTRS VEXT VOUT C1C1+ C2C2+ RCIRCUIT COLUMN ADDRESS CIRCUIT OSCILLATOR DISPLAY DATA 16,896 Bits LINE ADDRESS CIRCUIT TIMING GENERATOR CIRCUIT
CIRCUIT INSTRUCTION DECODER REGISTER
HOLDER
STATUS REGISTER
INTERFACE (PARALLEL SERIAL)
Figure Block Diagram
DB6(SCLK) DB7(SID) RW_WR E_RD CS1B RESETB
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
CONFIGURATION
0728
(TOP VIEW)
(0,0)
Figure S6B0728 Chip Configuration Table S6B0728 Dimensions Item Chip size pitch 159, Bumped size 125, 126, 160, 161, 313, 127, 162, 311, Bumped height Figure Bump Align Coordinate
Size 2470
Unit
8740
(Min.) (Min.) (Typ.)
Figure Align Coordinate(With GoldBump)
(-3920, 825)
(-3810, -705) (3870, 783) Align Align
Bump Align
When designing pattern must prohibited this area (ILB Align Key). pattern used routing over this area, happened pattern-short through bumped pattern Align Key.
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
Center Coordinates
Table Center Coordinates [Unit:
NAME
DUMMY DUMMY COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127 TEST1 TEST2 TEST3 CS1B RESETB RW_WR E_RD
-4161 -4081 -4001 -3947 -3893 -3839 -3785 -3731 -3677 -3623 -3569 -3515 -3461 -3407 -3353 -3299 -3245 -3191 -3137 -3083 -3029 -2975 -2921 -2867 -2813 -2759 -2555 -2485 -2415 -2345 -2275 -2205 -2135 -2065 -1995 -1925 -1855 -1785 -1715 -1645 -1575 -1505 -1435 -1365 -1295 -1225 -1155 -1085 -1015 -945
-1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110
NAME
VOUT VOUT C1C1C1+ C2C2C4+ VEXT INTRS
-875 -805 -735 -665 -595 -525 -455 -385 -315 -245 -175 -105 1015 1085 1155 1225 1295 1365 1435 1505 1575 1645 1715 1785 1855 1925 1995 2065 2135 2205 2275 2345 2415 2485 2555
-1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110
NAME
COM63 COM62 COM61 COM60 COM59 COM58 COM57 COM56 COM55 COM54 COM53 COM52 COM51 COM50 COM49 COM48 COM47 COM46 COM45 COM44 COM43 COM42 COM41 COM40 DUMMY DUMMY DUMMY COM39 COM38 COM37 COM36 COM35 COM34 COM33 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17
2759 2813 2867 2921 2975 3029 3083 3137 3191 3245 3299 3353 3407 3461 3515 3569 3623 3677 3731 3785 3839 3893 3947 4001 4081 4161 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4245
-1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -1110 -917 -837 -783 -729 -675 -621 -567 -513 -459 -405 -351 -297 -243 -189 -135
NAME
COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 DUMMY DUMMY DUMMY COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29
4245 4245 4245 4245 4245 4245 4245 4245 4245 4245 4129 4049 3969 3915 3861 3807 3753 3699 3645 3591 3537 3483 3429 3375 3321 3267 3213 3159 3105 3051 2997 2943 2889 2835 2781 2727 2673 2619 2565 2511 2457 2403 2349 2295 2241 2187 2133 2079 2025 1971
1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
Table Center Coordinates (Continued) [Unit:
NAME
SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79
1917 1863 1809 1755 1701 1647 1593 1539 1485 1431 1377 1323 1269 1215 1161 1107 1053 -135 -189 -243 -297 -351 -405 -459 -513 -567 -621 -675 -729
1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110
NAME
SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129
-783 -837 -891 -945 -999 -1053 -1107 -1161 -1215 -1269 -1323 -1377 -1431 -1485 -1539 -1593 -1647 -1701 -1755 -1809 -1863 -1917 -1971 -2025 -2079 -2133 -2187 -2241 -2295 -2349 -2403 -2457 -2511 -2565 -2619 -2673 -2727 -2781 -2835 -2889 -2943 -2997 -3051 -3105 -3159 -3213 -3267 -3321 -3375 -3429
1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110
NAME
SEG130 SEG131 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 DUMMY DUMMY DUMMY COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 DUMMY
-3483 -3537 -3591 -3645 -3699 -3753 -3807 -3861 -3915 -3969 -4049 -4129 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245 -4245
1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 -135 -189 -243 -297 -351 -405 -459 -513 -567 -621 -675 -729 -783 -837 -917
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
DESCRIPTION
Table Power Supply Pins Name Supply Supply Power supply Ground drivers supply voltages voltage determined pixel impedance-converted operational amplifier application. Voltages should have following relationship: When internal power circuit active, these voltages generated following table according state bias. bias bias (N-1)/N (N-2)/N Description
NOTE
Table Driver Supply Pins Name C1-, C2C1+, C3+, C5+, VOUT Description Capacitor negative connection pins used voltage converter Capacitor positive connection pins used voltage converter Voltage converter input/output pin. VOUT Boost level VCI, internal booster Voltage converter input voltage internal booster. voltage adjustment used adjust means external resistors(INTRS "L") Selects external VREF voltage VEXT "L": using external VREF "H": using internal VREF Externally-input reference voltage(VREF) internal voltage regulator. valid only when "L". Internal resistors select used select resistors adjusting voltage level. INTRS "H": internal resistors. INTRS "L": external resistors. external resistive divider control voltage.
VEXT
INTRS
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
Table Microprocessor Interface Pins Name RESETB Description Reset input pin. When RESETB "L", initialization executed. Parallel Serial data input select input Interface mode Parallel Serial Data instruction Data Read Write E_RD RW_WR Write only Serial clock
(DB7)
SCLK (DB6)
*NOTE: When "L", high impedance E_RD RW_WR must fixed either "L". Microprocessor interface(PS "H") Register Select(PS "L") input Interface mode 6800-series mode 8080-series mode 4-Pin mode 3-Pin mode
CS1B
Chip select input pins Data instruction enabled only when CS1B "H". When chip select non-active, high impedance. Register select input "H": display data "L": control data Read Write execution control Type 6800-series RW_WR Description Read/Write control input "H": read "L": write Write enable clock input data latched rising edge signal.
RW_WR
8080-series
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
Table Microprocessor Interface Pins (Continued) Name Read Write execution control type E_RD Description Read Write control input "H": When "H", output status. "L": data latched falling edge signal. Read enable clock input When "L", output status. Description
E_RD
6800-series
8080-series
8-bit bi-directional data that connected standard 8-bit microprocessor data bus. When serial interface selected "L"); DB5: high impedance DB6: serial input clock (SCLK) DB7: serial input data (SID). When chip select active, high impedance.
Table Test Pins Name TEST1 TEST3 Test pins Don't these pins. Description
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
Table driver output pins Name Description segment driver outputs display data signal control output voltage segment driver. Display data SEG0 SEG131 Power save mode Segment driver output voltage Normal display Reverse display
common driver outputs internal scanning data signal control output voltage common driver. Scan data COM0 COM127 Power save mode Common driver output voltage
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
FUNCTIONAL DESCRIPTION
MICROPROCESSOR INTERFACE
Chip Select Input There CS1B pins chip selection. S6B0728 interface with only when CS1B "H". When these pins other combination, E_RD, RW_WR inputs disabled high impedance. And, case serial interface, internal shift register counter reset. Parallel Serial Interface S6B0728 four types interface with MPU, which serial parallel interfaces. This parallel serial interface determined shown Table Table Parallel Serial Interface Mode. Type Parallel CS1B CS1B Interface mode 6800-series mode 8080-series mode 4-Pin mode 3-Pin mode
Serial
CS1B
Parallel Interface "H") 8-bit bi-directional data used parallel interface type selected shown Table type data transfer determined signals E_RD RW_WR shown Table Table Microprocessor Selection Parallel Interface CS1B CS1B CS1B E_RD RW_WR 6800-series 8080-series
Table Parallel Data Transfer Common 6800-series E_RD RW_WR (RW) 8080-series E_RD (/RD) RW_WR (/WR) Description Read display data Write display data Read internal status register Write instruction data
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
CS1B
Command Write Data Write Status Read Data Read
Figure 6800-Series Interface protocol (PS="H", C68="H")
CS1B
Command Write Data Write Status Read Data Read
Figure 8080-Series Interface Protocol (PS="H", C68="L")
Serial Interface "L") Communication with microprocessor occurs clock-synchronized serial peripheral interface when low. When using serial interface, read operations allowed. When chip select inputs valid(CS1B "H"), serial data sent most significant first rising edge serial clock going into processed 8-bit parallel data eighth clock. Since clock signal easy affected external noise caused line length, operation check actual machine recommended. valid, internal 8-bit shift register 3-bit counter reset. serial interface type selected setting shown Table
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
Table Microprocessor Selection Serial Interface Serial interface mode 4-Pin 3-Pin Chip Select CS1B, CS1B, Register Select software Serial Data Clock input
4-Pin Interface "L", "H") 4-pin interface mode, used indicating whether serial data input display instruction data. Data display data when high instruction data when low.
CS1B
SCLK
Figure 4-Pin Timing used)
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
3-Pin Interface "L") 3-Pin Interface mode, pre-defined instruction called Display Data Length, used indicate whether serial data input display instruction data instead pin. data handled instruction data until Display Data Length instruction issued. This Display Data Length instruction consists bytes instruction. first byte instruction enables next instruction valid, data second byte indicates that specified number display data bytes(1 256) transmitted. next byte after display data string handled instruction data. details, refers Figure
Chip Select
CS1B
Serial clock
bytes bytes 00001000 11111100 00001001 bytes bytes display data User's display data
Serial data
10110001 Page
00010000
Column address
Internal Figure Timing used) *NOTES: spite transmission data, CS1B will disable, state terminates abnormally. Next state initialized. number writing display data register value
Busy Flag Busy Flag indicates whether S6B0728 operating not. When read status operation, this device busy status will accept only read status instruction. cycle time correct, microprocessor needs check this flag before each instruction, which improves performance.
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
Data Transfer S6B0728 uses holder internal data data transfer with MPU. When writing data from on-chip RAM, data automatically transferred from holder shown figure when reading data from on-chip MPU, data initial read cycle stored holder (dummy read) reads this stored data from holder next data read cycle shown figure This means that dummy read cycle must inserted between each pair address sets when sequence address sets executed. Therefore, data specified address cannot output with read display data instruction right after address sets, output second read data.
signals
D(N)
D(N+1)
D(N+2)
D(N+3)
Internal signals
HOLDER COLUMN ADDRESS
D(N)
D(N+1)
D(N+2)
D(N+3)
Figure Write Timing
signals
Dummy D(N) D(N+1) D(N+2)
Internal signals
HOLDER COLUMN ADDRESS D(N) D(N+1) D(N+2)
Figure Read Timing
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
DISPLAY DATA (DDRAM)
Display Data stores pixel data LCD. 128-row 132-column addressable array. Each pixel selected when page column addresses specified. rows divided into pages lines. Data read from written lines each page directly through DB7. display data from microprocessor correspond common lines shown figure microprocessor read from write through buffer. Since controller operates independently, data written into same time data being displayed without causing flicker.
COM0 COM1 COM2 COM3 COM4 Display
Display Data
Figure RAM-to-LCD Data Transfer Page Address Circuit This circuit providing page address Display Data shown figure incorporates -bit page address register changed only "Set Page" instruction. Line Address Circuit This circuit assigns DDRAM line address corresponding first line (COM0) display. Therefore, setting line address repeatedly, possible realize screen scrolling page switching without changing contents on-chip shown figure incorporates 7-bit line address register changed only initial display line instruction 7-bit counter circuit. beginning each frame, contents register copied line counter which increased internal latch signal generates Line ddress transferring 132-bit data display data latch circuit. However, display data icons scrolled because access Line Address icons.
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
Column Address Circuit Column Address circuit 8-bit preset counter that provides Column Address Display Data shown figure When Column Address instruction issued, 8-bit [Y7:Y0] updated. And, since this address increased each read write data instruction, microprocessor access display data continuously. However, counter incremented locked non-existing address above 83H. unlocked column address again Column Address instruction. Column Address counter independent page address register. select instruction makes possible invert relationship between Column Address segment outputs. necessary rewrite display data built-in after issuing select instruction. Refer following figure Output Column address [Y7:Y0] Display data panel display
panel display
Figure Relationship between Column Address Segment Outputs
Segment Control Circuit This circuit controls display data display OFF, reverse display entire display instructions without changing data display data RAM.
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
Page Address
Data
Line Address
Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31
Page
Start
1/128 Duty
Page
Page
ADC=0 ADC=1 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
Page
Page
Page
Page
SEG131 SEG130 SEG129 SEG128 SEG127 SEG126
1/104 Duty
Page
COM96 COM97 COM98 COM99 COM100 COM101 COM102 COM103 COM104 COM105 COM106 COM107 COM108 COM109 COM110 COM111 COM112 COM113 COM114 COM115 COM116 COM117 COM118 COM119 COM120 COM121 COM122 COM123 COM124 COM125 COM126 COM127
Column Address Segment Output
Initial start line address
Figure Display Data
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
DISPLAY CIRCUITS
Oscillator This completely on-chip Oscillator frequency nearly independent VDD. This oscillator signal used voltage converter display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals used displaying LCD. internal display clock, generated oscillation clock, generates clock line counter signal display data latch. line address on-chip generated synchronization with display clock (CL) display data latch circuit synchronization latches 132-bit display data with display clock. display data, which read driver, completely independent access display data from microprocessor. display clock generates signal which enables driver make drive waveform, also generates internal common timing signal start signal common driver. frame line changes phase setting internal instruction. Driving waveform internal timing signal shown figure
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
COM0
COM1
SEGn
Figure 2-frame Driving Waveform (Duty Ratio 1/85)
COM0
COM1
SEGn
Figure N-line Inversion Driving Waveform Duty Ratio 1/85)
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
DRIVER CIRCUIT
128-channel common driver 32-channel segment driver configure this driver circuit. This panel driver voltage depends combination display data signal.
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7
COM0
COM1
COM8 COM9 COM10 COM11
COM2
SEG0
COM12 COM13 COM14
SEG1
COM15
SEG2
Figure Segment Common Timing
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
Partial Display S6B0728 realizes partial display function with low-duty driving saving power consumption showing various display duties. show various display duties LCD, driving duty bias programmable instruction. And, built-in power supply circuits controlled instruction adjusting driving voltages
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
Reference example partial display Display duty
-COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
Partial display Partial display duty Initial COM0
-COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23
Moving display Partial display duty Initial COM0
Figure Reference Example Partial Display
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
POWER SUPPLY CIRCUITS
Power Supply circuits generate voltage levels necessary drive liquid crystal driver circuits with low-power consumption fewest components. There voltage converter circuits, voltage regulator circuits, voltage follower circuits. They valid only master operation controlled power control instruction. details, refers "Instruction Description". Table shows referenced combinations using Power Supply circuits. Table Recommended Power Supply Combinations User setup Only internal power supply circuits used Only voltage regulator circuits voltage follower circuits used Only voltage follower circuits used Only external power supply circuits used Power control circuits circuits circuits VOUT
Open
Open
Open
External input External input Open
Open
Open
Open External input
Open External input
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
Voltage Converter Circuits These circuits boost electric potential between times toward positive side boosted voltage outputted from VOUT pin. possible select lower boosting level boosting circuit "Set DC-DC Step-up" instruction. When higher level selected instruction, VOUT voltage valid.
VOUT C1C1+ C2C4+
VOUT C1C1+ C2C4+
VOUT C1C1+ C2C4+
VOUT C1C1+ C2C4+
VOUT C1C1+ C2C4+
VOUT Boost level
Figure Boosting Circuits
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
Voltage Regulator Circuits function internal voltage regulator circuits determine liquid crystal operating voltage, adjusting resistors, within range |V0| |VOUT|. Because VOUT operating voltage operational-amplifier circuits shown figure necessary applied internally externally. 6-1, determine connected internally externally INTRS pin. called voltage electronic volume determined 6-2, where parameter value selected instruction, "Set Reference Voltage Register", within range VREF voltage 25°C shown Table (Eq. 6-1) (Eq. 6-2)
Table VREF Voltage 25°C Temp. coefficient -0.05% External input VREF VEXT
VOUT
Figure Internal Voltage Regulator Circuit
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
Case Using Internal Resistors, (INTRS "H") When INTRS "H", resistor connected internally between connected between determine instructions, "Regulator Resistor Select" "Set Reference Voltage". 3-bit data settings
Table Internal ratio Depending 3-bit Data
Figure shows voltage measured adjusting internal regulator register ratio 6-bit electronic volume registers each temperature coefficient
Voltage 16.00 14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00 Electronic volume register
Figure Voltage Electronic Volume Levels
DRIVER CONTROLLER
PRELIMINARY SPEC. VER.
S6B0728
Case Using External Resistors, (INTRS "L") When INTRS "L", necessary connect external regulator resistor between VSS, between Example: following requirements driver voltage, 6-bit reference voltage register Maximum current flowing From From 1.69 From requirement [uA] (Eq. 6.5) (Eq. 6.4) (Eq. 6.3)
From equations 6.3, 1.69 [M], 8.31
Table shows range depending above requirements. Table Range Electronic volume level 8.10 10.00 11.83
Voltage Follower Circuits VLCD voltage (V0) resistively divided into four voltage levels (V1, V4), these output impedance converted Voltage Follower increasing drive capability. Table shows relationship between level each duty ratio. Table Level bias (N-1)/N (N-1)/N Remarks
S6B0728
PRELIMINARY SPEC. VER.
DRIVER CONTROLLER
REFERENCE CIRCUIT EXAMPLES
0.47
When using internal regulator resistors (INTRS "VDD") When using internal regulator resistors (INTRS "VSS")
VOUT
VOUT
Figure When Using Power Circuits (7-times V/C: V/R: V/F:
When using internal regulator resistors (INTRS "VDD") When using internal regulator resistors (INTRS "VSS")
External VOUT
VOUT
External VOUT
VOUT
Figure When Using some Power Circuits (V/C: OFF, V/R: V/F:
DRIVER CONTROLLER
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External VOUT
VOUT
Figure When Using only Voltage Follower Circuit (V/C: OFF, V/R: OFF, V/F:
VOUT External Figure When Using Power Circuits (V/C: OFF, V/R: OFF, V/F: OFF)
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RESET CIRCUIT
Setting RESETB Reset instruction initialize internal function. When RESETB becomes "L", following procedure occurred. Page address: Column address: Modify-read: Display Off: Initial display line: (first) Initial COM0 register: (COM0) Partial display duty ratio: 1/128 Reverse display Off: (normal) n-line inversion register: (disable) Entire display Off: (normal) Power control register (VC, DC-DC step times converter circuit Regulator resistor select register: (R2, Reference voltage control register: (EV5, EV4, EV3, EV2, EV1, EV0) bias ratio: 1/12 select: (normal) select: (normal) Oscillator status: Power save mode: release When RESET instruction issued, following procedure occurred. Page address: Column address: Modify-read: Initial display line: (first) Regulator resistor select register: (R2, Reference voltage control register (EV5, EV4, EV3, EV2, EV1, EV0) While RESETB reset instruction executed, instruction except read status could accepted. Reset status appears DB4. After becomes "L", instruction accepted. RESETB must connected reset MPU, initialize this same time. initialization RESETB essential before used.
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INSTRUCTION DESCRIPTION
Table Instruction Table Instruction
Read display data Write display data Read status page address column address column address modify-read Reset modify-read Display initial display line register initial COM0 register partial display duty ratio N-line inversion Release N-line inversion Reverse display Entire display Power control Select DC-DC step-up Select regulator resistor electronic volume register Select bias select select Oscillator start power save mode Release power save mode register Reset Test instruction
Don't care Description
Read data from DDRAM Write data into DDRAM
Read data Write data
Read internal status page address column address column address modify-read mode release modify-read mode display display 2-byte instruction specify initial display line realize vertical scrolling 2-byte instruction specify initial COM0 realize window scrolling 2-byte instruction partial display duty ratio 2-byte instruction n-line inversion register Release N-line Inversion mode normal display reverse display normal display entire display Control power circuit operation Select step-up internal voltage converter Select internal resistance ratio regulator resistor 2-byte instruction specify electronic volume register Select bias bi-directional selection normal direction reverse direction bi-directional selection normal direction reverse direction Start built-in oscillator Power save mode Release power save mode register 3-pin serial mode Initialize internal functions operation Don't this instruction.
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Read Display Data 8-bit data from Display Data specified column address page address read this instruction. column address incremented automatically after each this instruction, microprocessor continuously read data from addressed page. dummy read required after loading address into column address register. Display data cannot read through serial interface.
Read data
Write Display Data 8-bit data display data from microprocessor written location specified column address page address. column address incremented automatically that microprocessor continuously write data addressed page.
Write data
Page Address Column Address Data rite Column Column
Page Address Column Address Dummy Data Read Column Column Data Read Column Column
Data Write Continue Optional Status
Data Read Continue Optional Status
Figure Sequence Writing Display Data
Figure Sequence Reading Display Data
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Read Status Indicates internal status S6B0728 BUSY
Flag BUSY
Description device busy when internal operation reset instruction rejected until BUSY goes Low. chip active, chip being busy. Indicates relationship between column address segment driver. reverse direction (SEG131 SEG0), normal direction (SEG0 SEG131) Indicates display status display display Indicates initialization progress RESETB signal chip active, chip being reset.
Page Address Sets Page Address display data from microprocessor into Page Address register. data accessed when Page Address column address specified. Along with column address, Page Address defines address display write read display data. Changing Page Address doesn't effect display status.
Specified page address
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Column Address Sets Column Address display from microprocessor into Column Address register. Along with Column Address, Column ddress defines address display write read display data. When microprocessor reads writes display data from display RAM, Column Addresses automatically incremented. Column Address
Column Address
Selected column address
accessible column
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Modify-Read This instruction stops automatic increment column address read display data instruction, column address still increased write display data instruction. reduces load microprocessor when data specific area repeatedly changed during cursor blinking others. This mode canceled reset Modify-read instruction.
Reset Modify-Read This instruction cancels Modify-read mode, makes column address return initial value just before Modify-read instruction started.
Page Address Column Address Modify-Read Dummy Read Data Read Data Process Data Write
Change Complete Reset Modify-Read Return Column Address
Figure Sequence Cursor Display
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Display Turns Display
display display
Initial Display Line Register Sets line address display determine initial display line using -byte instruction. display data displayed (COM0) panel. Instruction
Instruction
Selected line address
Setting Initial Display Line Start Instruction (2-Byte Instruction Mode Setting)
Instruction (2-Byte Instruction Register Setting) Setting Initial Display Line
Figure Sequence Setting Initial Display Line
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Initial COM0 Register Sets initial (COM) panel using 2-byte instruction. using this instruction, possible realize window moving without change display data. Instruction
Initial COM0 COM0 COM1 COM2 COM125 COM126 COM127
Instruction
Setting Initial COM0 Start Instruction (Mode Setting) Instruction (Initial COM0 Setting) Setting Initial COM0
Figure Sequence Setting Initial COM0
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Partial Display Duty Ratio Sets duty ratio within range realize Partial Display using 2-byte instruction. Instruction
Instruction
partial duty ratio 1/16 1/17 1/127 1/128 operation
Other combinations
Setting Partial Display Start Instruction (Mode Setting)
Instruction (Partial Display Duty Setting) Setting Partial Display
Figure Sequence Setting Partial Display
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N-line Inversion Register Sets inverted line number within range improve display quality controlling phase internal signal using 2-byte instruction. Instruction
Instruction
Selected n-line inversion 0-line inversion (frame inversion) 2-line inversion 3-line inversion 4-line inversion 30-line inversion 31-line inversion 32-line inversion
Setting N-Line Inversion Start Instruction (Mode Setting) Instruction (N-Line Inversion Setting) Setting N-Line Inversion
Figure Sequence Setting Partial Display Release N-line Inversion Returns frame inversion condition from n-line inversion condition.
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Reverse Display Reverses display status panel without rewriting contents display data RAM. (normal) (reverse)
data pixel illuminated pixel illuminated
data pixel illuminated pixel illuminated
Entire Display Forces whole points turned regardless contents display data RAM. this time, contents display data held. This instruction priority over reverse Display instruction. (Normal) (Entire)
data pixel illuminated pixel illuminated
data pixel illuminated pixel illuminated
Power Control Selects eight power circuit functions using -bit register. external power supply part internal power supply functions used simultaneously.
Status internal power supply circuits Internal voltage converter circuit Internal voltage converter circuit
Internal voltage regulator circuit Internal voltage regulator circuit Internal voltage follower circuit Internal voltage follower circuit
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Select DC/DC Step-up Selects DC/DC step-up reduce power consumption this instruction. very useful realize partial display function.
Selected DC-DC converter circuit times boosting circuit times boosting circuit times boosting circuit times boosting circuit times boosting circuit
Regulator Resistor Select Selects resistance ratio internal resistor used internal voltage regulator. voltage regulator section power supply circuit. Refer table ratio
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Electronic Volume Register Consists -byte instruction. instruction sets Electronic Volume mode, updates contents Electronic Volume register. After second instruction, Electronic Volume mode released. Instruction
Instruction
Reference voltage
Setting Electronic Volume Start Instruction Mode Setting Instruction Register Setting Setting Electronic Volume
Figure Sequence Setting Electronic Volume
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Select Bias Selects Bias ratio voltage required driving LCD.
Selected bias 1/10 1/11 1/12
Select output scanning direction selected this instruction which determines driver output status.
normal direction (COM0 COM127) reverse direction (COM127 COM0)
Select Changes relationship between column address segment driver. direction segment driver output pins reversed software. This makes layout flexible module assembly.
normal direction (SEG0 SEG131) reverse direction (SEG131 SEG0)
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Oscillator Start This instruction enables built-in oscillator circuit.
Reset This instruction resets initial display line, column address, page address, common output status select their initial status, dose affect contents display data RAM. This instruction cannot initialize power supply that initialized RESETB pin.
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Power Save S6B0728 enters Power Save status reduce power consumption static power consumption value returns normal operation status following instructions. Power Save Mode
Release Power Save Mode
internal status during power save mode follows Oscillator circuit power supply circuit output level Consumption Current Non-operation
Test Instruction This instruction testing Please
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Referential Instruction Setup Flow: Initializing with Built-in Power Supply Circuits
User System Setup External Pins
Start Initialization
Power (VDD-VSS) Keeping RESETB
Waiting Stabilizing Power
RESETB
User Application Setup Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select] User Power Setup Internal Instructions [Oscillator [DC-DC Step-up Register Select]
Waiting 50mS
[Regulator Resistor Select] [Electronic Volume Register Select]
Waiting
[LCD Bias Register Select] Waiting Stabilizing Power Levels
Initialization
Figure Initializing with Built-in Power Supply Circuits
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Referential Instruction Setup Flow: Initializing without Built-in Power Supply Circuits
User System Setup External Pins
Start Initialization
Power (VDD-VSS) Keeping RESETB
Waiting Stabilizing Power
RESETB
Power Save
User Application Setup Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select]
User Power setup internal instructions [Oscillator Regulator Follower Register Select [Power Control]
Release Power Save
Waiting Stabilizing Power Levels
Initialization
Figure Initializing without Built-in Power Supply Circuits
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Referential Instruction Setup Flow: Data Displaying
Initialization
Display Data Addressing Instruction [Initial Display Line] [Set Page Address] [Set Column Address]
Write Display Data Instruction [Display Data write]
Turn Display nstruction [Display ON/Off]
Data Display
Figure Data Displaying Referential Instruction Setup Flow: Power
Optional Status
Power Save Instruction
Waiting 50mS
Power (VDD-VSS)
Power
Figure Power
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Referential Instruction Setup Flow: Partial Duty Changing
Start Partial changing Display Internal Instruction [Display OFF] Standby Mode Internal Instruction [Power Save Mode] Partial Duty Internal Instructions [Partial Display Duty Ratio Select] [Initial Display Line Register] [COM0 Register Select] User Power Setup Internal Instructions [Oscillator [DC-DC Step-up Register Select] Waiting 50mS [Regulator Resistor Select] Electronic Volume Register Select] Waiting
Bias Register Select]
Waiting Discharging Power Levels Release Power Save Waiting Stabilizing Power Levels Write Display Data Display Internal Instruction [Display Data Write] [Display OFF]
Partial Changing
Figure Partial Duty Changing
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SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings (Vss Unit
Parameter Supply voltage range
Symbol VOUT
Rating -0.3 17.0 +0.3
External reference voltage Input voltage range Operating temperature range Storage temperature range
NOTES
VEXT TOPR TSTR
VDD, VOUT, VEXT based Voltage VOUT must always satisfied. supply voltage exceeds absolute maximum range, this damaged permanently. desirable this under electrical characteristic conditions during general operation. Otherwise, this malfunction reduced reliability result.
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CHARACTERISTICS
Table Characteristics 3.6V, -40~85°C) Item Operating voltage Operating voltage Input voltage Output voltage High High Symbol -0.5mA 0.5mA 25°C, 25°C Condition Min. 0.8V 0.8V Typ. Max. 15.0 0.2V 0.2V SEGn COMn Unit used
Input leakage current Output leakage current driver resistance Frame frequency
Table Characteristics Item Voltage converter Circuit input voltage Voltage converter circuit output voltage Voltage regulator circuit operating voltage Voltage follower circuit operating voltage Reference voltage Symbol Condition voltage conversion (no-load Min. Typ. Max. Unit used
VOUT
VOUT
VOUT
15.0
VOUT
VREF 25°C
1.940
2.000
15.0 2.060
voltage range calculated from VOUT specification. Min(VCI) 15V, Max(VCI)
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Dynamic Current Consumption when External Power Supply used. Table Display (VDD 3.0V, 25°C) Item Dynamic current consumption Symbol IDD1 Condition 15.0V, duty 1/128 Min. Typ. Max. Unit used
Table Checker Pattern (VDD 3.0V, 25°C) Item Dynamic current consumption Symbol IDD1 Condition 15.0V, duty 1/128 Min. Typ. Max. Unit used
Dynamic Current Consumption when Internal Power Supply Table Display (VDD 3.0V, 25°C) Item Dynamic current consumption Symbol IDD2 Condition 15.0V, boosting, duty 1/128, bias 1/12 Min. Typ. Max. Unit used
Table Check Pattern (VDD 3.0V, 25°C) Item Dynamic current consumption Symbol IDD2 Condition 15.0V, boosting, duty 1/128, bias 1/12 Min. Typ. Max. Unit used
Dynamic Current Consumption during Power Save Mode Table Power Save Mode (VDD 3.0V, 25°C) Item Sleep mode current Standby mode current Symbol IDDS1 IDDS2 Condition During sleep During standby Min. Typ. Max. Unit used
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Table Relationship between Oscillation Frequency Frame Frequency Duty ratio Item fOSC
On-chip oscillator circuit used (fOSC: oscillation frequency, fCL: display clock frequency, fFR: frame frequency, 128)
Remark Solves] Though wide range operating voltages guaranteed, spike voltage change affect voltage assurance during access from MPU. case external power supply applied. CS1B, CS2, DB7, E_RD, RW_WR, RESETB, C68, INTRS, REF, DB7, Applies when pins high impedance. Resistance value when -0.1[mA] applied during status output SEGn COMn. V[V] 0.1[mA] voltage change when -0.1[mA] applied status.) Table relationship between oscillation frequency frame frequency. voltage regulator circuit adjusts within voltage follower operating voltage range. On-chip reference voltage source voltage regulator circuit adjust *10. Applies case where on-chip oscillation circuit used access made from MPU. current consumption, when built-in power supply circuit OFF. current flowing through voltage regulation resistors included. does include current panel capacity, wiring capacity, etc.
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CHARACTERISTICS
Read Write Characteristics (8080-series MPU)
tAS80 tCY80 tPWLW tPWLR /RD, CS1B Write Read Figure Parallel Interface (8080-series MPU) Timing Diagram tACC80 tOD80 0.9VDD 0.1VDD tDS80 tPWHW tPWHR tDH80 tAH80
Table Characteristics (8080-series Parallel Mode) Item Address setup time Address hold time System cycle time Pulse width write Pulse width High write Pulse width read Pulse width high read Data setup time Data hold time Read access time Output disable time RW_WR (/WR) E_RD (/RD) Signal Symbol tAS80 tAH80 tCY80 tPWLW tPWHW tPWLR tPWHR tDS80 tDH80 tACC80 tOD80 Condition 3.6V, +85°C) Min. Max. Unit
NOTE: input signal rise time fall time (tr, specified less. (tCY80 tPWLW tPWHW write, (tCY80 tPWLR tPWHR read
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Read Write Characteristics (6800-series Microprocessor)
tAS68 tCY68 tEWLW tEWLR CS1B Write tACC68 Read Figure Parallel Interface (6800-series MPU) Timing Diagram tOD68 0.1VDD 0.9VDD tEWHW tEWHR tDS68 tDH68 tAH68
Table Characteristics (6800-series Parallel Mode) 3.6V, +85°C) Min. Max. Unit
Item Address setup time Address hold time System cycle time Enable width high write Enable width write Enable width high read Enable width read Data setup time Data hold time Read access time Output disable time
Signal
Symbol tAS68 tAH68 tCY68
Condition
E_RD E_RD
tEWHW tEWLW tEWHR tEWLR tDS68 tDH68 tACC68 tOD68
NOTE: input signal rise time fall time (tr, specified less. (tCY68 tEWHW tEWLW write, (tCY68 tEWHR tEWLR read
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Serial Interface Characteristics tCSS CS1B (CS2 tASS tCHS tAHS
tCYS SCLK 0.9VDD 0.1VDD tWLS tDSS Figure Serial Interface Timing Diagram tDHS tWHS
Table Characteristics (Serial Mode) 3.6V, +85°C) Item Serial clock cycle SCLK high pulse width SCLK pulse width Address setup time Address hold time Data setup time Data hold time CS1B setup time CS1B hold time Signal (SCLK) (SID) CS1B Symbol tASS tAHS tDSS tDHS tCSS tCHS Condition Min. Max. Unit
NOTE: input signal rise time fall time (tr, specified less.
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Reset Input Timing
RESETB Internal status During reset Reset complete
Figure Reset Input Timing Diagram
Table Characteristics (Reset mode) 3.6V, +85°C) Item Reset pulse width Reset time Signal RESETB Symbol Condition Min. 1000 Max. 1000 Unit
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REFERENCE APPLICATIONS
MICROPROCESSOR INTERFACE
CS1B
CS1B E_RD
6800-series
RESETB
S6B07
RW_WR RESETB
Figure Case Interfacing with 6800-series "H", "H")
CS1B CS1B E_RD
8080-series
RESETB
S6B07
RW_WR RESETB
Figure Case Interfacing with 8080-series "H", "L")
CS1B SCLK RESETB OPEN CS1B S6B07 DB7(SID) DB6(SCLK) RESETB
Figure Case 4-Pin Interface "L", "H")
CS1B SCLK RESETB OPEN CS1B S6B07 DB7(SID) DB6(SCLK) RESETB
Figure Case 3-Pin Interface "L", "L")
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CONNECTIONS BETWEEN S6B0728 PANEL
(1/128 Duty configurations)
COM127
S6B0728 (Bottom View)
SEG131 SEG130 SEG1 SEG0
COM0
COM63
S6B0728 (Top View)
SEG0 SEG1 SEG130 SEG131
COM64
pixels
pixels
Figure
Figure
pixels
pixels
SEG131 SEG130 SEG1 SEG0 COM127
SEG0 SEG1 SEG130 SEG131 COM0 COM63
S6B0728 (Bottom View)
S6B728 (Top View)
COM64
Figure
Figure

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