64CH COMMON DRIVER MATRIX July 2001 Ver. Contents this docum
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S6B0107
64CH COMMON DRIVER MATRIX
July 2001 Ver.
Contents this document subject change without notice. part this document reproduced transmitted form means, electronic mechanical, purpose, without express written permission Driver Team. Precautions Light Light characteristics move electrons integrated circuitry semiconductors, therefore change characteristics semiconductor devices when irradiated with light. Consequently, users packages which expose chips external light such COB, COG, must consider effective methods block light from reaching parts surface area, top, bottom sides chip. Follow precautions below when using products. Consider verify protection penetrating light substrate (board glass) product design stage. Always test inspect products under environment with penetration light.
S6B0107
64CH COMMON DRIVER MATRIX
S6B0107 Specification Revision History Version Original Content Date July.2001
64CH COMMON DRIVER MATRIX
S6B0107
CONTENTS
INTRODUCTION BLOCK DIAGRAM CONFIGURATION 100-QFP. DIAGRAM (CHIP LAYOUT 100QFP). CENTER COORDINATES (100QFP). 100-TQFP (S6B2107). DIAGRAM (CHIP LAYOUT 100-TQFP). CENTER COORDINATES (100-TQFP). DESCRIPTION ELECTRICAL CHARACTERISTICS CHARACTERISTICS CHARACTERISTICS (VDD 10%, -30°C +85°C).14 FUNCTIONAL DESCRIPTION TIMING DIAGRAM 1/48 DUTY TIMING (MASTER MODE).19 1/128 DUTY TIMING (MASTER MODE).20 1/48 DUTY TIMING (SLAVE MODE).21 POWER DRIVER CIRCUIT.22 APPLICATION CIRCUIT
64CH COMMON DRIVER MATRIX
S6B0107
INTRODUCTION
S6B0107 (TQFP type: S6B2107) driver with channel outputs matrix liquid crystal graphic display systems. This device provides shift registers output drivers. generates timing signal control S6B0108 channel segment driver TQFP type: S6B2108). S6B0107 fabricated power CMOS high voltage process technology, composed liquid crystal display system combination with S6B0108 channel segment driver).
FEATURES
matrix common driver with channel output 64-bit shift register internal driver circuit Internal timing generator circuit dynamic display Selection master/slave mode Applicable duty: 1/48, 1/64, 1/96, 1/128 Power supply voltage: driving voltage: DD-VEE) Interface Driver COMMON Other S6B0107 SEGMENT S6B0108
Controller
High voltage CMOS process 100QFP/100TQFP bare chip available
S6B0107
64CH COMMON DRIVER MATRIX
BLOCK DIAGRAM
Level Driver
Bi-Directional Shift Register
DIO1 PCLK2
Data Shift Direction Phase Selection Control Circuit
DIO2
Timing Generator Circuit
CLK1 CLK2
64CH COMMON DRIVER MATRIX
S6B0107
CONFIGURATION
100-QFP
DIO1
S6B0107
(100-QFP)
CLK2 CLK1 PCLK2 DIO2
S6B0107
64CH COMMON DRIVER MATRIX
DIAGRAM (CHIP LAYOUT 100QFP)
Chip size: 3450 4000 size: Unit
S6B0107
CLK2
CLK1
DIO1
There mark S6B0107 center chip.
PCLK2
DIO2
64CH COMMON DRIVER MATRIX
S6B0107
CENTER COORDINATES (100QFP)
Number Name DI01 Coordinate -1314.5 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1345.6 -1127.6 -977.6 -827.6 1775.4 1630 1505 1380 1255 1130 1005 -120 -245 -370 -495 -620 -745 -870 -995 -1120 -1245 -1370 -1495 -1775 -1775 -1775 -1775 Number Name CLK2 CLK1 PCLK2 DI02 Coordinate -677.6 -527.6 -377.6 -227.6 -77.6 113.8 308.7 458.7 608.7 758.7 908.7 1058.7 1208.7 1358.7 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1495 -1370 -1245 -1120 -995 -870 -745 -620 -495 -370 -245 -120 Number Name Coordinate 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1310.5 1185.5 1060.5 935.5 810.5 685.5 560.5 435.5 310.5 185.5 60.5 -64.5 -189.5 -314.5 -439.5 -564.5 -689.5 -814.5 -939.5 -1064.5 -1189.5 1005 1130 1255 1380 1505 1630 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4
S6B0107
64CH COMMON DRIVER MATRIX
100-TQFP (S6B2107)
S6B2107
(100-TQFP)
DIO1 CLK2 CLK1 PCLK2 DIO2
64CH COMMON DRIVER MATRIX
S6B0107
DIAGRAM (CHIP LAYOUT 100-TQFP)
Chip size: 3850 4100 size: Unit
CLK2
CLK1
DIO1
NOTE:
There mark S6B2107 center chip.
PCLK2
DIO2
S6B0107
64CH COMMON DRIVER MATRIX
CENTER COORDINATES (100-TQFP)
Number Name Coordinate Number Name Coordinate Number Name Coordinate
DIO1
-1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1245 -1095 -945 -795
1534 1409 1284 1159 1034 -216 -341 -466 -591 -716 -841 -966 -1091 -1216 -1341 -1466 -1821 -1821 -1821 -1821
PCLK2 DIO2 CLK2 CLK1
-195 1095 1245 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 -1466 -1341 -1216 -1091 -966 -841 -716 -591 -341 -216 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821
1697 1697 1697 1697 1697 1697 1697 1500 1375 1250 1125 1000 -125 -250 -375 -500 -625 -750 -875 -1000 -1125
1034 1159 1284 1409 1534 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822 1822
64CH COMMON DRIVER MATRIX
S6B0107
-645
-1821
1697 1697 1697 1697 1697
-1250 -1375 -1500
1822 1822 1822
-495
-1821
-345
-1821
S6B0107
64CH COMMON DRIVER MATRIX
DESCRIPTION
Table Description Number (TQFP) 28(25) 40(37) 23(20), 58(55) 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52) Symbol V0L, V1L, V4L, V5L, Power Power Description internal logic circuit (+5V 10%) driver circuit Bias supply voltage terminals drive LCD.
Slelect Level (R), Non-Select Level (R),
(V1L V1R, V4R, V5R) should connected same voltage. 42(39) Input Selection master/slave mode Master mode DIO1, DIO2, output state. Slave mode DIO1 input state (DIO2 output state) DIO2 input state (DIO1 output state) input state. 39(36) Input Selection data shift direction.
Data Shift Direction DIO1 DIO0 DIO2 DIO0
49(46)
PCLK2
Input
Selection shift clock (CL2) phase.
PCLK2 Shift Clock (CL2) Phase Data shift rising edge Data shift falling edge
30(27)
Input
Selection oscillation frequency. Master mode When frame frequency oscillation frequency should fosc 430kHz fosc 215kHz Slave mode Connect VDD.
64CH COMMON DRIVER MATRIX
S6B0107
Table Description (Continued) Number (TQFP) 31(28) 32(29) Symbol Input Selection display duty. Master mode
Duty 1/48 1/64 1/96 1/128
Description
Slave mode Connect 33(30) 35(32) 37(34) Oscillator Master mode: these terminals shown below.
S6B0107 Open S6B0107 External Open
Slave mode: Stop oscillator shown below.
Open Open
44(41) 43(40)
CLK1 CLK2
Output
Operating clock output S6B0108 Master mode: connection CLK1 CLK2 S6B0108 Slave mode: open Synchronous frame signal. Master mode: connection S6B0108 Slave mode: open Alternating signal input driving. Master mode: output state Connection S6B0108 Slave mode: input state Connection controller Data shift clock Master mode: output state Connection S6B0108 Slave mode: input state Connection shift clock terminal controller. Data input/output internal shift register.
DIO1 Output Output Input Output DIO2 Output Output Output Input
46(43)
Output
47(44)
Input/ Output Input Output
52(49)
29(26) 50(47)
DIO1 DIO2
Input/ Output
S6B0107
64CH COMMON DRIVER MATRIX
Table Description (Continued) Number (TQFP) 22-1(19-1) 100-59(100-56) Symbol C1-C64 Output Description Common signal output driving.
Data
34(31), 36(33) 38(35), 41(38) 45(42), 48(45) 51(48), 53(50)
connection
MAXIMUM ABSOLUTE LIMIT Characteristic Operating voltage Supply voltage Driver supply voltage Symbol VLCD Operating temperature Storage temperature
NOTES: Based Applies input terminals terminals high impedance. (Except V0L(R), V1L(R), V4L(R) V5L(R)). Applies V0L(R), V1L(R), V4L(R) V5L(R). Voltage level: VEE.
Value -0.3 +7.0 VDD-19.0 VDD+0.3 -0.3 VDD+0.3 VEE-0.3 VDD+0.3 +125
Unit
Note
(1), (3),
TOPR TSTG
64CH COMMON DRIVER MATRIX
S6B0107
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS 10%, DD-VEE 17V, +85°C) Characteristic Input Voltage Output Voltage High High Symbol ILKG fOSC -0.4mA 0.4mA VDD-VSS 20pf resistance (VDIV-CI) VDD-VEE Load current 150µA Operating current IDD1 IDD2 Supply current Operating Frequency fop1 fop2 Master mode 1/128 Duty Slave mode 1/128 Duty Master mode 1/128 Duty Master mode External clock Slave mode 1500
Condition
0.7V VDD-0.4 -1.0
0.3V
Unit
Note
Input leakage current frequency
NOTES: Applies input terminals DS1, DS2, SHL, PCLK2 terminals DIO1, DIO2, input state. Applies output terminals CLK1, CLK2 terminals DIO1, DIO2, output state. This value specified about current flowing through VSS. Internal oscillation circuit: 47k, 20pF Each terminal DS1, DS2, connected load. connected VDD, connected VSS. CL2, DIO1 external clock. This value specified about current flowing through VEE. Don't connect VLCD (V1-V5). This value specified about current flowing through VSS. Each terminal DS1, DS2, SHL, PCLK2
S6B0107
64CH COMMON DRIVER MATRIX
CHARACTERISTICS (VDD 10%, -30°C +85°C) Master Mode VDD, PCLK2 VDD, 20pF, 47k)
0.7VDD 0.3VDD
tWLC tWHC
DIO1 (SHL DIO2 (SHL DIO2 (SHL DIO1 (SHL
0.7VDD 0.3VDD tWH1
CLK1
tWL1
tD12
tD21
CLK2
tWH2
64CH COMMON DRIVER MATRIX
S6B0107
Master Mode
Characteristic Symbol Unit
Data setup time Data hold time Data delay time delay time delay time level width high level width CLK1 level width CLK2 level width CLK1 high level width CLK2 high level width CLK1-CLK2 phase difference CLK2-CLK1 phase difference CLK1, CLK2 rise/fall time
tWLC tWHC tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR/tF
2100 2100
S6B0107
64CH COMMON DRIVER MATRIX
Slave Mode VSS)
tWLC1 tWHC1 tWHC2 tWLC 0.7VDD 0.3VDD
(PLK2
(PLK2 VDD)
0.7VDD 0.3VDD 0.7VDD 0.3VDD tHCL
DIO1 (SHL DIO2 (SHL Input Data DIO1 (SHL DIO2 (SHL Onput Data
Characteristics level width high level width level width high level width Data setup time Data hold time Data delay time Output data hold time rise/fall time
NOTE: Connect load 30pF
Symbol tWLC1 tWHC1 tWLC2 tWHL tR/tF
Unit
Note PCLK2 PCLK2 PCLK2 PCLK2
(NOTE)
Output 30pF
64CH COMMON DRIVER MATRIX
S6B0107
FUNCTIONAL DESCRIPTION Oscillator Oscillator generates CL2, S6B0107, CLK1 CLK2 S6B0108 oscillation resister capacitor When selecting master/slave mode, oscillation circuit following: Master Mode: master mode, these terminals shown below.
S6B0107 20pF Open Open External Clock External Clock S6B0107
Internal Oscillation
Slave Mode: slave mode, stop oscillator shown below.
S6B0107 Open Open
Timing Generation Circuit generates CL2, FRM, CLK1 CLK2 frequency from oscillation circuit. Selection Master/Slave (M/S) Mode When "H", generates CL2, FRM, CLK1 CLK2 internally. When "L", operates receiving from mater device Frequency Selection (FS) adjust frequency 70Hz, oscillation frequency should follows: slave mode, connected VDD. Oscillation Frequency fOSC 430kHz fOSC 215kHz
S6B0107
64CH COMMON DRIVER MATRIX
Duty Selection (DS1, DS2) provides various duty selections according DS2. DUTY 1/48 1/64 1/96 1/128
Data Shift Phase Select Control Phase Selection circuit shift data synchronization rising edge, falling edge according PCLK2. PCLK2 Phase Selection Data shift rising edge Data shift falling edge
Data Shift Direction Selection When connected VDD, DIO1 DIO2 terminal only output. When connected VSS, depends SHL. DIO1 Output Output Input Output DIO2 Output Output Output Input DIO1 DIO2 DIO2 DIO1 Direction Data
64CH COMMON DRIVER MATRIX
S6B0107
TIMING DIAGRAM
1/48 DUTY TIMING (MASTER MODE) Condition: H(L), PCLK2
CLK1 CLK2
DIO1 (DIO2) (C48) (C47)
(C2) (C1) DIO2 (DIO1)
Relation DIO1 (DIO2)
CLK2
DIO1 (DIO2)
S6B0107
64CH COMMON DRIVER MATRIX
1/128 DUTY TIMING (MASTER MODE) Condition: H(L), PCLK2
CLK1 CLK2 DIO1 (DIO2) (C128) (C127)
C127 (C2) C128 (C1) DIO2 (DIO1)
Relation DIO1 (DIO2)
CLK2
DIO1 (DIO2)
64CH COMMON DRIVER MATRIX
S6B0107
1/48 DUTY TIMING (SLAVE MODE) Condition: PCLK2 H(L)
DIO1 (DIO2) (C48)
(C47)
(C2)
(C1)
DIO2 (DIO1)
S6B0107
64CH COMMON DRIVER MATRIX
POWER DRIVER CIRCUIT
V0L/R V5L/R V4L/R V1L/R S6B0108
S6B0107
Relation Duty Bias Duty 1/48 1/64 1/96 1/128 Bias 1/11 1/12 RDIV
When duty factor 1/48, value should satisfy. R1/(4R1
64CH COMMON DRIVER MATRIX
S6B0107
APPLICATION CIRCUIT 1/128 duty segment drive (S6B0108) interface circuit
V0R/L
V2R/L
V3R/L
V5R/L
V0R/L
V2R/L
V3R/L
CLK1
CLK2
CLK1
CLK2
CS2B CS1B -DB7 RSTB
SEG128
V5R/L CS2B CS1B -DB7 RSTB
S6B0108
Panel
V0R/L V2R/L V3R/L V5R/L V0R/L V2R/L V3R/L V5R/L
COM1
COM128
open open
PCLK2
PCLK2 V0R/L V1R/L V4R/L V5R/L
DIO2
CLK2
S6B0107 (master)
CLK2 CLK1
S6B0107 (slave)
open open open open open
CLK1
V0R/L
V1R/L
V4R/L
V5R/L
DIO1
DIO2
RSTB CS1B CS2B
CLK1
CLK2
CLK1
CLK2
CS2B CS1B -DB7 RSTB
S6B0108
S6B0108
CS2B CS1B -DB7 RSTB
S6B0108
SEG1
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