PLL2027XA PLL2027XA Phase-Locked Loop (PLL) frequency synthesizer

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PLL2027XA PLL2027XA Phase-Locked Loop (PLL) frequency synthesizer

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0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
PLL2027XA
PLL2027XA Phase-Locked Loop (PLL) frequency synthesizer constructed CMOS single monolithic structure. macrofunctions provide frequency multiplication capabilities. output clock frequency Fout related reference input clock frequency following equation: Fout=((M+2)*Fin)/(2P*2S) Where, Fout output clock frequency. reference input clock frequency. values programmable dividers. PLL2027XA consists phase/Frequency Detector(PFD), Charge Pump External Loop Filter, Voltage Controlled Oscillator(VCO), 2bit Pre-divider, 14bit Main divider 2bit Post Scaler shown Figure1.
FEATURES
0.35um CMOS device technology Volt single power supply Input frequency range: 250KHz frequency range: 200MHz Output frequency range: 200MHz Clock-to-Clock Jitter ±150ps 200MHz Duty ratio 55%(All tuned range) Frequency changed programmable divider Power down mode IMPORTANT NOTICE Please contact application engineer confirm proper selection M,P,S value.
PLL2027XA
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
FUNCTIONAL BLOCK DIAGRAM
Divider
Charge Pump
Post Scaler
FOUT
Loop Filter
Main Divider
Figure Phase Locked Loop Block Diagram
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
PLL2027XA
CORE DESCRIPTION
Name VDD2 VSS2 VDD1 VSS1 VBB1 FOUT PWRDN Type AB/DB vddd vssd vdda vssa vbba picc_bb poar50_bb piar50_bb pot12_bb picc_bb 20MHz~200MHz clock output FSPLL clock power down. -When PWRDN High, operate. isn't used this pin, tied VSS. values 2bit programmable pre-divider. values 14bit programmable main divider. values 2bit programmable post scaler. Digital ground Analog power supply Analog ground Analog Digital bias Reference Frequency Input External Loop Filter. Refer Figure(Core Configuration) Description Digital power supply
P[1:0] M[13:0] S[1:0] Type Abbr. Analog Input Digital Input Analog Output Digital Output
picc_bb picc_bb picc_bb
Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
PLL2027XA
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
CORE CONFIGURATION
PWRDN M[7:0] M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7] M[8] M[9] M[10] M[11] M[12] M[13] P[0] P[1] S[0] S[1]
FOUT
pll2027xa
P[1:0] S[1:0]
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
PLL2027XA
ABSOLUTE MAXIMUM RATINGS (TA=25°C)
Characteristics Supply Voltage Voltage Digital Storage Temperature Symbol VDD2 VDD1 Tstg Value vss-0.25 vdd+0.25 Unit Applicable VDD2,VDD1,VSS2, VSS1,VBB1 P[1:0],M[13:0],S[1:0] PWRDN
NOTES: ABSOLUTE MAXIMUM RATING specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect VSS2 unless otherwise specified. 100pF capacitor discharged through 1.5Kohm resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Differential Input Frequency Operating Temperature External Loop Filter Symbol VDD2-VDD1 Topr -0.1 +0.1 Unit
NOTE: strongly recommended that supply pins (VDD2, VDD1) powered same supply voltage avoid power latch-up.
PLL2027XA
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
ELECTRICAL CHARACTERISTICS
Characteristics Operating Voltage Digital Input Voltage High Digital Input Voltage Dynamic Current Power Down Current Symbol VDD2/VDD1 3.135 3.465 Unit
ELECTRICAL CHARACTERISTICS
Characteristics Input Frequency Output Clock Frequency Output Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle Locking Time Jitter,Clock Clock Symbol FOUT Fvco TJCC -150 +150 Unit
NOTE: strongly recommended that input signal generated glitch, consumer cannot help generating glitch, Consumer must carefully considerate specification.
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
PLL2027XA
FUCTIONAL DESCRIPTION
circuit synchronizing output signal (generated VCO) with reference input signal frequency well phase. this application, includes following basic blocks. voltage-controlled oscillator generate output frequency divider devides reference frequency divider devides output frequency divider divides output frequency phase frequency detector detects phase difference between reference frequency output frequency (after division) controls charge pump voltage. loop filter removes high frequency components charge pump voltage does smooth clean control
values programmed 18bit digital data from external source. locked desired frequency. Fout 250KHz, m=M+2 p=2^P, s=2^S Digital data format: Main Divider
NOTE:
Divider P1,P0
Post Scaler S1,S0
S[1] S[0]: Output Frequency Scaler M[13] M[0]: Frequency Divider P[1] P[0]: Reference Frequency Input Divider
IMPORTANT NOTICE Please contact application engineer confirm proper selection M,P,S value.
PLL2027XA
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
CORE EVALUATION GUIDE
embedded PLL, must consider test circuits embedded core multiple applications. Hence following requirements should satisfied. FILTER(CP,CZ) FOUT pins must bypassed external test. test (Below examples), needed control dividers M[13:0],P[1:0] S[1:0] -that generate multiple clocks. Registers used easy control divider values. sample bits 18-bit divider pins bypassed test using MUX.
3.3V Digital Power
3.3V Analog Power
External Clock Source
VDD2 VSS2
VDD1 VSS1 VBB1
FOUT
PWRDN M[13:0]
pll2027xa
#1.18bit Register Block
P[1:0] S[1:0]
Select
NOTES
Test Pins Sample bits
Internal Divider Signal Line
10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
PLL2027XA
PACKAGE CONFIGURATION
INDEX1 VSSO
pll2027xa
INDEX2 FOUT VBB1
ouput Clock
VDDO
VBB1 PWRDN PWDVCO VDD1
VSS2
External Loop Filter
VSS2
VDD2
VDD2
VDD1 VSS1
VSS1
Exteral Input Clock (15KHz 250KHz)
Note
10uF
PLL2027XA
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
PACKAGE DESCRIPTION
Name VDD2 VSS2 VBB1 PWRDN 11,12 9,10 43,44 Type AB/DB Digital power supply Digital ground Analog Digital Bias FSPLL clock power down PWRDN High, operating under this condition. isn't used this pin, tied VSS2. Pre-Divider Input Analog power supply Analog ground Input (15KHz 250KHz) Only Power Down.(Test Block pin) PWDVCO high, operate. isn't used this pin, tied VSS1 Loop filter( Pump output refer loop filter. Loop Filter( Input refer loop filter. 20MHZ~200MHz clock output Post scaler input 14bit main divider input Power Power Test (VDDO, Logic State High) Test (VSSO, Logic State Low) Description
P[0]~P[1] VDD1 VSS1 PWDVCO
27,28 37,38 35,36
FOUT S[0]~S[1] M[0]~M[13] VDDO VSSO
NOTE: TYPE denote power ground respectively.
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
PLL2027XA
EXTERNAL LOOP FILTER
:2.02K :0.1K :236nF :18nF
CORE LAYOUT GUIDE
digital power(VDD2,VSS2) analog power(VDD1,VSS1) must dedicated only seperated. dedicated VDD2 VSS2 allowed that least power consuming block shared with PLL. POAR50_BB, PIAR50_BB used that contains only production diodes without resistors buffers. FOUT pins must placed from internal signals order avoid overlapping signal lines. blocks having large digital switching current must located away from core. core must shielded guardring. FOUT pad, custom drive buffer POT12_BB buffer considering drive current.
PLL2027XA
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
DESIGN CONSIDERATIONS
following design consideratios apply: Phase tolerance jitter independent frequency. Jitter affected noise frequency power(VDD2/VSS2,VDD1/VSS1). increases when noise level increases. CMOS-level input reference clock recommend signal compatibility with circuit. Other levels such degrade tolerances. two, more PLLs requires special design considerations. Please consult your application engineer more information. following apply noise level, which minimized using good analog power ground isolation techniques system: wide traces POWER(VDD2/VSS2 VDD1/VSS1) connections core. Seperate races from chip's VDD2/VSS2,VDD1/VSS1 supplies. proper VDD2/VSS2,VDD1/VSS1 de-coupling. good power ground sources board. Power VBB1 minimize substrate noise core should placed close possible dedicated loop filter analog Power ground pins. inadvisable locate noise-generating signals, such data buses high-current outputs, near cells. Other related signals should placed near have pre-defined placement restriction
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
PLL2027XA
FEEDBACK REQUEST
Thank having interest products. Please fill this form, especially items which want request. Parameter Process Supply voltage (VDD) Input frequency (FIN) Output frequency (FOUT) Cycle cycle jitter (TJCC) 100M 200M 200M 300M 300M 400M 400M 500M Period jitter (TJP) 100M 200M 200M 300M 300M 400M 400M 500M Output duty ratio (TOD) Lock time (TLT) Dynamic current Stand current Filter capacitor many PLLs embedded your system need synchronization between input clock output clock need another spec jitter Parameter Long-term jitter (TJLT) Tracking Jitter (TJT) have another special request, please describe below. Customer Unit psec (pk-pk) psec (pk-pk) Customer Unit
PLL2027XA
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
JITTER DEFINITION
Period Jitter Period jitter maximum deviation output clock's transition from ideal position.
Ideal Cycle Fout
Cycle-to-Cycle Jitter Cycle-to-cycle jitter maximum deviation output clock's transition from corresponding position previous cycle.
Ti-1 Fout
Ti+1
TJCC (Ti+1
Long-Term Jitter Long-term jitter maximum deviation output clock' transition from ideal position, after many cycles. term "many" depends application frequency.
Cycle
Cycle
TJLP
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
PLL2027XA
Tracking Jitter Tracking jitter maximum deviation output clock(FOUT)'s transition from input clock (FIN) position.
Trigger
Delay
Fout
PLL2027XA
0.35µm 20MHZ-200MHZ PIXEL CLOCK GENERATOR
NOTES

PLL2027XA PLL2027XA Phase-Locked Loop (PLL) frequency synthesizer

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