BW2017X BW2017X Phase-Locked Loop (PLL) frequency synthesizer imp
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0.35µm 3MHZ-25MHZ FSPLL
BW2017X
BW2017X Phase-Locked Loop (PLL) frequency synthesizer implemented 0.35um CMOS technology. provides frequency multiplication capability. output clock frequency Fout related reference input clock frequency following equation:
Fout
where
Fout output clock frequency. reference input clock frequency. values programmable dividers. BW2017X consists phase frequency detector(PFD), charge pump, external loop filter, voltage controlled oscillator(VCO), 4bit pre-divider 8bit main divider 2bit post scaler lock detector shown Figure1.
FEATURES
0.35um CMOS technology 3.3V Single power supply Output frequency range: 25MHz Cycle Jitter: ±300ps Duty ratio: Frequency change programmable divider Power down mode
IMPORTANT NOTICE Please contact application engineer confirm proper selection M,P,S value.
BW2017X
0.35µm 3MHZ-25MHZ FSPLL
FUNCTIONAL BLOCK DIAGRAM
divider
charge pump
Loop Filter (external)
Post scaler
Fout
Filter Main divider
Figure BW2017X Block Diagram
0.35µm 3MHZ-25MHZ FSPLL
BW2017X
CORE DESCRIPTION
Name VDDA VSSA FOUT FILTER Type AB/DB vddd vssd vdda vssa vbba picc_bb pot12_bb poar50_bb Digital ground Analog power supply Analog ground Analog Digital Bias clock input 25MHz clock output Charge pump output connected loop filter. capacitor connected between analog ground. FSPLL clock power down. active HIGH. used, VSSD. values 4bit programmable pre-divider. values 8bit programmable main divider. values 2bit programmable post scaler. Description Digital power supply
picc_bb
P[3:0] M[7:0] S[1:0] Type Abbr. Analog Input Digital Input Analog Output Digital Output
picc_bb picc_bb picc_bb
Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
BW2017X
0.35µm 3MHZ-25MHZ FSPLL
CORE CONFIGURATION
M[7:0]
M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7] P[0] P[1] P[2] P[3]
FOUT
bw2017x
FILTER
P[3:0]
S[1:0]
S[0] S[1]
0.35µm 3MHZ-25MHZ FSPLL
BW2017X
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Voltage digital Storage Temperature Symbol VDDA Tstg Value -0.3 VSS-0.3 VDD+0.3 Unit Applicable VDD,VSS VDDA,VSSA,VBB P[3:0],M[7:0],S[1:0],
NOTES: ABSOLUTE MAXIMUM RATINGS specify values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATINGS conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect unless otherwise specified. 100pF capacitor discharged through resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Differential External Loop Filter Capacitance Operating Temperature Symbol VDDA Topr -0.1 Unit
NOTE: strongly recommended that supply pins (VDDA, VDD) powered from same source avoid power latch-up.
BW2017X
0.35µm 3MHZ-25MHZ FSPLL
ELECTRICAL CHARACTERISTICS
Characteristics Operating Voltage Digital Input Voltage High Digital Input Voltage Dynamic Current (CORE Level without Cell) Power Down Current Symbol VDD,VDDA 3.15 3.45 Unit
ELECTRICAL CHARACTERISTICS
Characteristics Input Frequency Output Clock Frequency Output Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle 25MHz) Lock Time Cycle Cycle Jitter Symbol FOUT Fvco TJCC -300 +300 Unit
0.35µm 3MHZ-25MHZ FSPLL
BW2017X
FUNCTION DESCRIPTION
circuit synchronizing output signal (generated VCO) with reference input signal frequency well phase. this application, includes following basic blocks. voltage-controlled oscillator generate output frequency pre-divider divides reference frequency main divider divides output frequency post scaler divides output frequency phase frequency detector (PFD) detects phase frequency difference between reference input output (after division) controls charge pump current. loop filter removes high frequency components control voltage does smooth correct control VCO. values programmed 14bit digital data from external source. Thus locked onto desired frequency.
Fout
4MHz, M=m+8 P=p+2, S=2^s Digital data format: Main Divider M7,M6,M5,M4,M3,M2,M1,M0
NOTES: Output Frequency Scaler Frequency Divider Reference Frequency Input Divide
Divider P3,P2,P1,P0
Post Scaler S1,S0
NOTES Don't zero, that 000000 00000000 proper range 1<=P<=14, 1<=M<=248 must selected considering stability output frequency range Please consult with application engineer select proper values
BW2017X
0.35µm 3MHZ-25MHZ FSPLL
CORE EVALUATION GUIDE
embedded PLL, must consider test circuit embedded core multiple applications. Hence following requirements should satisfied. FOUT must bypassed external test. test (below examples), needed control dividers M[7:0],P[3:0] S[1:0] -that generate multiple frequencies. Example Registers used easy control divider values. Example sample bits 14-bit divider pins bypassed test using MUX.
3.3V Power
Digital
3.3V Analog Power
External Clock Source
VDDA VSSA
FOUT
M[7:0]
bw2017x
FILTER 940pF
14bit Register Block
P[3:0]
S[1:0] VSSA
Select
NOTE:
Test Pins Sample bits
10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED
Internal Divider Signal Line
Figure BW2017X Core Test Scheme
0.35µm 3MHZ-25MHZ FSPLL
BW2017X
CORE LAYOUT GUIDE
digital power(VDD,VSS) analog power(VDDA,VSSA) must dedicated only seperated. dedicated available, that least power consuming block shared with PLL. used FILTER that contains protection diodes without resistors buffers. FOUT FILTER pins must placed from internal signals order prevent them from overlapping signal lines. blocks having large digital switching current must located away from core. core must shielded guard ring. FOUT, custom drive buffer POT12 buffer considering drive current.
WITHOUT XTAL-DRIVER USERS GUIDE
There crystal driver cell (XTAL-OSC PSOSCM2) options BW2017X core. crystal component used external clock source applied Please contact application engineer when using crystal. crystal component used external clock Buffer offered from Samsung's STD90 library recommanded When implementing embedded block, following pins must bypassed externally testing locking function: Without Xtal-driver FIN,FILTER,FOUT,VDDA,VSSA,VDD VSS.
BW2017X
0.35µm 3MHZ-25MHZ FSPLL
FILTER
FOUT
VDDA VSSA VBBA
Used PICC_BB
Divider
Scaler
PWRDN
Divider
P[3:0] M[7:0] S[1:0]
Glue Logic
Divider Optional Test Pins
Figure example block without crystal component (Normal Case)
0.35µm 3MHZ-25MHZ FSPLL
BW2017X
PACKAGE CONFIGURATION
2bit Post Scaler Dummy Test Block Control pins 3.3V Digital Power
3.3V Power
8bit Main Divider
FOUT
bw2017x
10uF
VBBA VBBA FILTER
940pF
External Clock Source
VDDA
4bit Divider Input
VDDA
3.3V Analog Power
NOTES: Noconnection test
BW2017X
0.35µm 3MHZ-25MHZ FSPLL
PACKAGE DESCRIPTION
Name VDDD VSSD 35,36 33,34 Type Digital ground FSPLL clock power down PWRDN High, operating under this condition. isn't used this pin, tied VSS. Pre-Divider Input(LSB) Analog power supply Analog ground Analog Digtal Bias Power Crystal input external FREF input 3MHZ~25MHz clock output Pump connected FILTER. 940pF Capcitor connected between analog Post scaler input 8bit main divider input Power Ground Description Digital power supply
P[0]~P[3] VDDA VSSA VBBA FOUT FILTER
45~48 13,14 11,12 19,20
AB/DB
S[0]~S[1] M[0]~M[7] VDDO VSSO
31,32 37~44
NOTE: TYPE denote power ground respectively.
0.35µm 3MHZ-25MHZ FSPLL
BW2017X
DESIGN CONSIDERATIONS
following design considerations apply Phase tolerance jitter independent frequency. Jitter affected noise frequency power(VDD,VSS,VDDA, VSSA). increases when noise level increases. CMOS-level input reference clock recommended signal compatibility with circuit. Other levels such degrade tolerances. more PLLs requires special design considerations. Please contact your application engineer detail. following apply noise level, which minimized selecting good analog power ground isolation techniques system: wide traces POWER(VDD,VSS, VDDA, VSSA) connections core. Seperate traces from chips' VDD/VSS/VDDA/VSSA supplies. proper VDD/VSS/VDDA/VSSA decoupling method. good power ground sources board. bulk power minimize substrate noise. core should placed close possible dedicated loop filter analog Power ground pins. desirable close noise-generating signals such data buses high-current outputs near cells. Other related signals should placed near have pre-defined placement restriction.
BW2017X
0.35µm 3MHZ-25MHZ FSPLL
FEEDBACK REQUEST
Thank having interest products. Please fill this form, especially items which want request. Parameter Process Supply voltage (VDD) Input frequency (FIN) Output frequency (FOUT) Cycle cycle jitter (TJCC) 100M 200M 200M 300M 300M 400M 400M 500M Period jitter (TJP) 100M 200M 200M 300M 300M 400M 400M 500M Output duty ratio (TOD) Lock time (TLT) Dynamic current Stand current Filter capacitor many PLLs embedded your system need synchronization between input clock output clock need another spec jitter Parameter Long-term jitter (TJLT) Tracking Jitter (TJT) have another special request, please describe below. Customer Unit psec (pk-pk) psec (pk-pk) Customer Unit
0.35µm 3MHZ-25MHZ FSPLL
BW2017X
JITTER DEFINITION
Period Jitter Period jitter maximum deviation output clock's transition from ideal position.
Ideal Cycle Fout
Cycle-to-Cycle Jitter Cycle-to-cycle jitter maximum deviation output clock's transition from corresponding position previous cycle.
Ti-1 Fout
Ti+1
TJCC (Ti+1
Long-Term Jitter Long-term jitter maximum deviation output clock' transition from ideal position, after many cycles. term "many" depends application frequency.
Cycle
Cycle
TJLP
BW2017X
0.35µm 3MHZ-25MHZ FSPLL
Tracking Jitter Tracking jitter maximum deviation output clock(FOUT)'s transition from input clock (FIN) position.
Trigger
Delay
Fout
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