BW2010D This CMOS 8-bit Triple Converter general applications.Its

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BW2010D This CMOS 8-bit Triple Converter general applications.Its

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0.35µm 8-BIT 250MSPS
BW2010D
This CMOS 8-bit Triple Converter general applications.Its typical conversion rate 250MHz Supply voltage 3.3V
TYPICAL APPLICATIONS
Graphic display Digital General purpose high-speed digital-to-analog conversion
FEATURES
250MHz Operation +3.3V power supply Optional 7.5IRE Mode (Internal External) RS-343A output level 8bit Voltage parallel Input Output Swing Power Down mode(High active)
BW2010D
0.35µm 8-BIT 250MSPS
FUNCTIONAL BLOCK DIAGRAM
BLANKEN SETUP RA7~RA0 2'nd DAC1
GA7~GA0
2'nd
DAC2
BA7~BA0
2'nd
DAC3
SLEEP High Active)
CCOMP
VREFOUT
I75uA
IRSET
SENSEZ
0.35µm 8-BIT 250MSPS
BW2010D
CORE DESCRIPTION
Name IOR,IOG,IOB RA0:RA7 GA0:GA7 BA0:BA7 SLEEP VREFOUT CCOMP I75uA SENSEZ IRSET VSETUP BLANKEN VDDA1 VDDA2 VDDD VSSA1 VSSA2 VSSD VBBA Type poa_bb_50option picc_bb picc_bb picc_bb picc_bb picc_bb poa_bb_50option poa_bb_50option poa_bb poar50_bb poa_bb_50option picc_bb picc_bb vdda vdda vddd vssa vssa vssd vbba Description Analog output (Red,Green,Blue) Video signal Digital input Video signal GREEN Digital input Video signal BLUE Digital input Clock Power down mode (hign active) Reference voltage input monitoring External capacitance connection drive [uA] (for RAMDAC) output sensing (for RAMDAC) external resistor connection Blank enable level enable Analog Power Analog Power Digital Power Analog Ground Analog Ground Digital Ground Analog Ground
Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
BW2010D
0.35µm 8-BIT 250MSPS
CORE CONFIGURATION
VDDA1 VSSA1 VDDA2 VSSA2
VDDD
VSSD
VBBA
RA[7:0]
GA[7:0]
bw2010d
BA[7:0]
BLANKEN VSETUP SLEEP
CCOMPSENSEZ
IRSET
I75UA VREFOUT
0.35µm 8-BIT 250MSPS
BW2010D
FUNCTIONAL DESCRIPTION
This Core 8bit 250MSPS digital analog data converter uses segment architecture 4bits sides binary-weighted architecture 4bits side. contains First Latch Block, Decoder Block ,Second Latch Block, Block, Block, Switch Buffer Block, Sleep Block power down, CM(current mirror) Block Analog Switch Block. This core uses reference current decide 1LSB current size dividing reference current 122times. reference current must constant switch's physical real size constant using block with high gain. most significant block this core analog switch block must maintain uniformity each switch, Layout designer must care about matching characteristics analog switch block. more than supply current dissipated Analog Switch Block Block. uses samsung(SEC) standard cell digital cell latch, decoder buffer. adjust full current output, must decide "Rset" resistor value(connected IRSET pin) "Vbias" voltage value(connected VREFOUT pin). voltage output obtained connecting RL1(connected IOR,IOG,IOB pin) Error: Linearity error defined maximum deviation actual analog output from ideal output, determined straight line drawn from zero full scale. Monotonicity: converter monotonic output either increases remains constants digital input increases. Offset Error: deviation output current from ideal zero called offset error. output expected when inputs Gain Errors: difference between actual andideal output span. actual span determined output when inputs minus output when inputs Output Compliance Range: range allowable voltage output current-output DAC. Operation beyond maximum compliance limits cause either output stage saturation breakdown resulting nonlinear performance. Settling Time: time required output reach remain within specified error band about final value, measured from start output transition Glitch Impulse: Asymmetrical switching times give rise undesired output transients that quantified glitch impulse. specified area glitch pV-s
BW2010D
0.35µm 8-BIT 250MSPS
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Symbol VDDA1 VDDA2 VDDA Tstg Values -0.3 Unit
Voltage Digital Voltage Storage Temperature Range
VSSA-0.3 VDDA+0.3
NOTES: strongly recommended that avoid power latch-up supply driven from same source. Absolute Maximum Rating values applied individually while other parameters within specified operating conditions. Function operation under these conditions implied. Applied voltage must current limited specified range. Absolute Maximum Ratings value beyond which device damaged permanently. Normal operation guaranteed.
RECOMMENDED OPERATING CONDITIONS
Characteristics Operating Supply Voltage Digital input Voltage HIGH Operating Temperature Range Symbol VDDA Topr 3.15 0.7VDDA 3.45 0.3VDDA Unit
0.35µm 8-BIT 250MSPS
BW2010D
ELECTRICAL CHARACTERISTICS
Characteristics Resolution Differential Linearity Error Integral Linearity Error Monotonicity White Black Pedestral Voltage Maximum Output Compliance Exteranl Reference Voltage (option) Internal Reference Voltage Power Supply Current Symbol 0.55 -0.3 1.15 Guaranteed 1.235 1.235 0.65 +1.3 1.27 1.25 Unit Bits
NOTES: White Black Pedestal Voltage changed using external RSET resistor Converter Specifications (unless otherwise specified) VDDA=3.3V VSSA=GND RL=37.5Ohm VREFOUT=1.235V
ELECTRICAL CHARACTERISTICS
Characteristics Conversion Speed Analog Output Delay Analog Output Rise Time Analog Output Fall Time Analog Output Settling Time Glitch Impulse Feedthrough Setup Time Hold Time Output Compliance THD(Total Harmonic Distortion) SNDR( Fin=6MHz Fck=300MHz) Symbol fdth SNDR -0.3 0.125 Unit pVsec nsec nsec
NOTES: above parameters guaranteed over full temperature range. Clock data feed-through function amount overshoot undershoot digital inputs .Settling time does include clock data feed-through Glitch impulse include clock data feed-through. Setup Hold Time simulation values, test result
BW2010D
0.35µm 8-BIT 250MSPS
TIMING DIAGRAM (FOR CHANNEL)
D[7:0] Tset 0.1%
Half clock pipeline delay
NOTES: Output delay measured from point rising edge full scale transition Settling time measured from point full scale transition output remaining within ±2LSB. Output rise/fall time measured between points full scale transition. Power Down Time 5.5us Power Down Time 5.5ms
0.35µm 8-BIT 250MSPS
BW2010D
TIMING DIAGRAM (FOR CHANNEL)
/G/B output disable 17.6 0.66 enable 19.04 0.714
WHITE LEVEL
BLACK LEVEL
1.44 0.54
BLANK LEVEL
NOTE: OUTPUT CONNECTED DOUBLY TERMINATED LOAD Vref 0.7V, Rset=1.27
FUNCTION (FOR EACH CHANNEL)
Binary Input Vsetup Blanken Data 000H 3FFH 000H 3FFH 000H 3FFH 000H 3FFH Code 1023 1023 1023 1023 Output Current(Ma) 37.5 R,G,B Channel 1.44 19.04 1.44 19.04 1.44 19.04 17.6
BW2010D
0.35µm 8-BIT 250MSPS
CORE EVALUATION GUIDE
3.3V 3.3V 3.3V
VDDA2 VSSA2
VDDA1 VSSA1 VBBA
VDDA
VSSA
CCOMP RA<7:0> GA<7:0>
MAIN PATH
I75uA SENSEZ
BA<7:0>
SLEEP(GND) BLANKEN VSETUP
bw2010d
IRSET
VREFOUT
selection option 1.235V
SELECT
Bi-drectional function Measuring&Digitla input forcing
Location
Description 0.1uF 37.5 10uF 0.1uF
0.35µm 8-BIT 250MSPS
BW2010D
1.Testability Whether internal logic testability, required able select values digital inputs ,TEST PATH block 16pins. above figure. Only check main function (Linearity) output (IOR,IOG,IOB), VREFOUT ,IRSET CCOMP pins reserved external use. Analysis voltage applied VREFOUT measured IRSET node voltage value proportioned reference current value resistor which connected IRSET node. estimate full scale current value measuring voltage, check characteristics OPAMP. reference, VREFOUT applied CCOMP node given IRSET node, current flowing through IRSET given VREFOUT/RSET. voltage scaled factor 1/122 VIDEO. full scale current given decimal value equivalent digital code. Resolution want change resolution, many appear bits want connect rest lower bits ground above diagram which 8bit application. Output Range Alteration order change output swing, following equation. Vout
BW2010D
0.35µm 8-BIT 250MSPS
PHANTOM CELL INFORMATION
Pins core assigned externally (Package pins) internally (internal ports) depending design methods. term "External" implies that pins should assigned externally like power pins. term "External/internal" implies that applications these pins depend user.
VBBA
VBBA
VSSA1 VDDA1
IRSET VSSA2 VDDA2 VDDA2
VDDA2 VREFOUT CCOMP VSSA2
VBBA
VBBA
BW2010D
8bit tripe 250MSPS
VSETUP
BLANKEN RA[7] RA[6] RA[5] RA[4] RA[3] RA[2] RA[1] RA[0] GA[7] GA[6] GA[5] GA[4] GA[3] GA[2] GA[1] GA[0] BA[7] BA[6] BA[5] BA[4] BA[3] BA[2] BA[1] BA[0]
SLEEP
VDDD
VDDD
VSSD
VSSD
0.35µm 8-BIT 250MSPS
BW2010D
PHANTOM CELL INFORMATION (Continued)
Name VDDD Usage External Layout Guide Maintain large width lines pads. place port positions minimize length power lines. merge analog powers with another power from other blocks. good power ground source board.
VSSD VBBA VDDA1 VSSA1 VDDA2 VSSA2 CCOMP VREFOUT IREF SLEEP BLANKEN VSETUP RA[7:0] GA[7:0] BA[7:0]
External External External External External External External/Internal overlap with digtal lines. Maintain shortest path pads. External/Internal External/Internal Separate from other analog signals External/Internal Maintain larger width shorter length pads. Separate from other digital lines. External/Internal External/Internal External/Internal Separated from analog clean signals possible. exceed length 1,000um. External/Internal External/Internal External/Internal External/Internal External/Internal
BW2010D
0.35µm 8-BIT 250MSPS
PACKAGE CONFIGURATION
VDDA VSSA SLEEP
VREFOUT
3.3V
normal operation
+3.3V
+1.2
VSSA2
VDDA2
R=37.5Ohm +3.3
CCOMP
I75uA
digital input data
R=37.5Ohm R=37.5Ohm
VDDA2
IRSET
VSSA2 VDDA1 VSSA1
R=147 3.3V 3.3V
+3.3V
BLANKE
VBBA
Location RSET 0.1uF TANTALUM CAPACITOR 10uF CAPACITOR 0.1uF CERAMIC CAPACITOR 37.5 RESISTOR
Description
METAL FILM RESISTOR
NOTES: Analog digital supplies should separated de-coupled. Supplies connected internally ground pins must connected. ground plane preferred although depends application
0.35µm 8-BIT 250MSPS
BW2010D
PACKAGE DESCRIPTION
Name BA<0:7> GA<0:7> RA<0:7> VREFOUT IRSET SLEEP BLANKEN VSETUP I75uA CCOMP SENSEZ VDDA VSSA VBBA VDDA1 VDDA2 VSSA1 VSSA2 9~16 17~24 33,40 31,42 Type Description Video signal BLUE Digital input Video signal GREEN Digital input Video signal Digital input Reference voltage input monitoring external resistor connection Power down mode (hign active) Blank enable level enable Clock drive (150 [uA] External capacitance connection output sensing Analog Voltage Output Analog Voltage Output Analog Voltage Output Digital Power Digital Ground Bulk Bias Ground Analog Power Analog Power Analog Ground Analog Ground
NOTE: TYPE denote Power Ground respectively.
BW2010D
0.35µm 8-BIT 250MSPS
FEEDBACK REQUEST
appreciate your interest products. have further questions, please specify attached form. Thank very much. ELECTRICAL CHARACTERISTIC Characteristics Supply Voltage Power dissipation Resolution Analog Output Voltage Operating Temperature Output Load Capacitor Output Load Resistor Integral Non-Linearity Error Differential Non-Linearity Error Maximum Conversion Rate Unit Bits Remarks
VOLTAGE OUTPUT Reference Voltage BOTTOM Analog Output Voltage Range Digital Input Format Binary Code Complement Code
CURRENT OUTPUT Analog Output Maximum Current Analog Output Maximum Signal Frequency Reference Voltage External Resistor Current Setting(RSET) Pipeline Delay want Power down mode? want Internal Reference Voltage(BGR)? Which want serial input data type parallel input type?
0.35µm 8-BIT 250MSPS
BW2010D
VERSION LIST
Version Date 98.05.01 99.12.13 20.02.23 02.0420 Modified Items Original version published Test configuration correction Font correction font correction layout guide correction item (Phantom cell guide) Comments
BW2010D
0.35µm 8-BIT 250MSPS
NOTES

BW2010D This CMOS 8-bit Triple Converter general applications.Its

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