BW1284X bw1284x CMOS 12Bit converter general application. This di

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0.35µm 3.3V 12-BIT 0.32MSPS
BW1284X
bw1284x CMOS 12Bit converter general application. This digital analog converter Rstring structure. settling time 3000ns (Typical value).
TYPICAL APPLICATIONS
Hard Disk Drive (HDD) ISDN Motor Control Systems General Applications
FEATURES
Resolution 12Bit Differential Linearity Error Integral Linearity Error Settling Time 3000ns Power Consumption 4.5mA Signal Noise Distortion Ratio 66dB Power Down Mode Operation Temperature Range Power Supply 3.3V Single
BW1284X
0.35µm 3.3V 12-BIT 0.32MSPS
FUNCTIONAL BLOCK DIAGRAM
VDDD
VSSD
VDDA
VSSA
VBBA
D[11:0]
PWDN
1-of-2N 1-of-2M Decoder Decoder Dout Dout
VOUT
VTOP VBOT PWDN
R-String
PWDN
VHALF
PWDN
0.35µm 3.3V 12-BIT 0.32MSPS
BW1284X
CORE DESCRIPTION
Name D[11:0] PWDN VTOP VBOT VHALF VOUT VDDD VSSD VDDA VSSA VBBA Type picc_bb picc_bb pia_bb pia_bb pia_bb pia_bb poa_bb poa_bb vddd vssa vdda vssa vbba Description Digital Input Data (12bit) D[11] D[0] Power Down (Active Low) Voltage Reference (3.3V) Voltage Reference Bottom (0.0V) Internal Voltage Reference (2.65V) Internal Voltage Reference Bottom (0.65V) Analog Voltage Output (1.65V) Analog Voltage Output Analog Power (+3.3V) Analog Ground (0.0V) Digital Power (+3.3V) Digital Ground (0.0V) Analog Bias (0.0V)
Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
BW1284X
0.35µm 3.3V 12-BIT 0.32MSPS
CORE CONFIGURATION
VDDD
VSSD
VDDA
VSSA
VBBA
VOUT
D[11:0]
bw1284x
VHALF
PWDN
VTOP VBOT
0.35µm 3.3V 12-BIT 0.32MSPS
BW1284X
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Analog Output Voltage Digital Input Voltage Reference Voltage Operating Temperature Range Symbol (VDDA,VDDD) VOUT D[11:0] Topr Value Unit
NOTES: ABSOLUTE MAXIMUM RATING specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect VSS(VSSA VSSD VBBA) unless otherwise specified. 100pF capacitor discharged through 1.5kW resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Supply Voltage Difference Reference Voltage Digital Input 'Low' Voltage Digital Input 'High' Voltage Operating Temperature Symbol VDDA VSSA VDDD VSSD VDDA VDDA Topr -0.1 2.65 0.65 3.15 3.45 Unit
NOTE: strongly recommended that avoid power latch-up supply pins(VDDA,VDDD) driven from same source.
BW1284X
0.35µm 3.3V 12-BIT 0.32MSPS
ELECTRICAL CHARACTERISTICS
(Converter Specifications VDDD=VDDA=3.3V, VSSD=VSSA=VBBA=0V, PWDN=High, Top=25°C, VRT=2.65V, VRB=0.65V unless otherwise specified.) Characteristics Resolution Differential Linearity Error Integral Linearity Error Zero Scale Error
Symbol VZSE VFSE VoMAX
2.649
Unit Bits
Conditions VRT=2.65V, VRB=0.65V VoMAX VOUT(D[11:0]=High) VLSB (VoMAX VOUT(D[11:0]=Low) 4095 AIN(254,255)
Full Scale Voltage Error Maximum Output Voltage Size
VLSB
0.488
NOTES: VZSE=VOUT(D[11:0]=Low) VFSE=VOUT(D[11:0]=High) {(VRT-VRB) 4095/4096 VRB}
0.35µm 3.3V 12-BIT 0.32MSPS
BW1284X
ELECTRICAL CHARACTERISTICS
(Converter Specifications VDDD=VDDA=3.3V, VSSD=VSSA=VBBA=0V, load cap=10pF, Top=25°C, VRT=2.65V, VRB=0.65V unless otherwise specified.) Characteristics Supply Current (Average Current) Supply Current (Power Down Mode) Symbol Ivdd1 Ivdd2 Unit Conditions Ivdd1 IVDDA IVDDD IVRT Data Input High Ivdd2 IVDDA IVDDD IVRT Data Rate 0.32MHz Load 10pF PWDN=LOW VOUT VSSA VDDA Data Input High Data Rate 0.32MHz Data HIGH Data Rate 0.32MHz Data HIGH Data Rate 0.32MHz Data HIGH Data Rate 0.32MHz Data HIGH PWDN HIGH PWDN HIGH 0.32MHz fout 80kHz
Short Circuit Current Analog Output Delay Analog Output Rise Time Analog Output Fall Time Analog Output Settling Time Power Down Time Power Down Time Signal Noise Distortion Ratio
Toff SNDR
3000 1000
BW1284X
0.35µm 3.3V 12-BIT 0.32MSPS
TIMING DIAGRAM
DATA 000000000000 111111111111
000000000000
111111111111
000000000000
VOUT DATA
VOUT
DATA
000000000000
111111111111
000000000000 0.5LSB
VOUT
PWDN
VOUT
0.5LSB 0.0V
Toff
0.5LSB
Output delay measured from point rising edge input data full scale transition. Settling time measured from point full scale transition output remaining within ±1/2 LSB. Output rise/fall time measured between points full scale transition.
FUNCTIONAL DESCRIPTION
bw1284x 12bit R-string block, decoders, amps, control block. digital outputs decoders decide voltage level R-string block.
VRstring
*Dn)
voltages internally generated resistor strings. (VTOP 3.3V VBOT 0.0V then 2.65V VRB= 0.65V) more accurate operations, better connect with voltage sources instead connecting VTOP VBOT with voltage sources. (VRT 2.65V 0.65V) VOUT dependent digital input values VHALF fixed 1.65V normal conditions. bw1284x designed drive just 10pF capacitive load.
0.35µm 3.3V 12-BIT 0.32MSPS
BW1284X
CORE EVALUATION GUIDE
CORE
HOST
PWDN D[11:0] VDDD VTOP 3.3V
TEST PATH
3.3V 0.0V
VSSD VDDA
VBOT VHALF VHALF
3.3V
bw1284x
VOUT VOUT
VSSA VBBA
Location
Description 10uF TANTALUM CAPACITOR 0.1uF CERAMIC CAPACITOR
TESTABILITY
Whether internal logic testability, required able select values digital inputs (D[11:0] above figure. Only check main function. (Linearity) more accurate operations, better connect with voltage sources connecting VTOP VBOT with voltage sources. (VRT 2.65V 0.65V)
BW1284X
0.35µm 3.3V 12-BIT 0.32MSPS
CORE LAYOUT GUIDE
PWDN
VDDA VSSA VBBA
Decoders R-String
VHALF VOUT
VDDD VSSD Guardring D[11:0] NWELL Guardring VBOT VTOP
0.35µm 3.3V 12-BIT 0.32MSPS
BW1284X
Name D[11:0] PWDN
Property
Usage Internal External Internal External External
Layout Guide Digital Input Signal lines must have same length reduce propagation delay. Voltage reference lines (VRT VRB) must wide metal reduce voltage drop metal lines. VOUT signal should crossed signals should next digital signals minimize capacitive coupling between signals.
VTOP VBOT VOUT VDDA
External Internal External Internal External Internal External External recommended that thick analog power metal. When connected PAD, path should kept short possible. Digital power analog power separately used.
VSSA VDDD VSSD VBBA
External External External External
When core block connected other blocks, must double guard-ring using N-well active remove substrate coupling noise. that case, power metal should connected directly. Bulk power used reduce influence substrate noise.
BW1284X
0.35µm 3.3V 12-BIT 0.32MSPS
FEEDBACK REQUEST
appreciate your interest products. have further questions, please specify attached form. Thank very much. ELECTRICAL CHARACTERISTIC Characteristics Supply Voltage Power dissipation Resolution Analog Output Voltage Operating Temperature Output Load Capacitor Output Load Resistor Integral Non-Linearity Error Differential Non-Linearity Error Maximum Conversion Rate Unit Bits Remarks
VOLTAGE OUTPUT Reference Voltage BOTTOM Analog Output Voltage Range Digital Input Format Binary Code Complement Code
CURRENT OUTPUT Analog Output Maximum Current Analog Output Maximum Signal Frequency Reference Voltage External Resistor Current Setting(RSET) Pipeline Delay want Power down mode? want Internal Reference Voltage(BGR)? Which want serial input data type parallel input data type? need 3.3V power supply your system?
0.35µm 3.3V 12-BIT 0.32MSPS
BW1284X
HISTORY CARD
Version Date 99.10 00.02.23 Preliminary Version Version Updated hun95 hun2000 file this datasheet modified with dac1253x datasheet page SNDR added page VHALF 2.65V 1.65V poa_abb poa_bb page settling time 1000ns 3000ns SNDR added Version Updated page (Output Load Resistor) Version Updated page Block Diagram modified page Power Down Current Modified page Layout Guide modified page Interal Internal Version Updated page Additional question modified reference datasheet dac1253x Modified Items Comments
01.03.28 02.03.19
02.04.16
BW1284X
0.35µm 3.3V 12-BIT 0.32MSPS
NOTES

BW1284X bw1284x CMOS 12Bit converter general application. This di

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