BW1254X bw1254x CMOS 14bit analog-to-digital converter (ADC). con

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BW1254X bw1254x CMOS 14bit analog-to-digital converter (ADC). con

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0.35µm 14-BIT 10MSPS
BW1254X
bw1254x CMOS 14bit analog-to-digital converter (ADC). converts analog input signal into 14bit binary digital codes maximum sampling rate 10MHz. device monolithic with on-chip, high-performance, sample-and-hold Amplifier (SHA) current reference voltage reference. structure allows both differential single-ended input.
TYPICAL APPLICATIONS
Imaging (Copiers, Scanners, Cameras) Medical Instruments Digital Communication Systems uADSL System
FEATURES
Resolution 14bit Maximum Conversion Rate 10MHz Package Type 48TSSOP Power Supply 3.3V Power Consumption 120mW (typical) Reference Voltage Internal reference (dual reference) Input Range 0.5V 2.5V (2.0VP-P) Differential Linearity Error ±0.7 Integral Linearity Error ±1.5 Signal Noise Distortion Ratio 72dB Total Harmonic Distortion 80dB Range Indicator Digital Output CMOS Level Operating Temperature Range 70°C
BW1254X
0.35µm 14-BIT 10MSPS
FUNCTIONAL BLOCK DIAGRAM
Analog Input
MDAC
MDAC
MDAC
FLASH
FLASH
FLASH
FLASH
Reference Output
Voltage Reference CLOCK GEN. DIGITAL LOGIC Digital Output
Clock
0.35µm 14-BIT 10MSPS
BW1254X
CORE DESCRIPTION
Name REFTOP REFBOT CML1 VDDA1 VBBA1 VSSA1 AINT AINC ITEST STBY CKIN D[13:0] VBBA2 VSSA2 VDDA2 Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Power Analog Ground Digital Power Digital Ground Analog Bidirectional Digital Bidirectional Type piar10_bb piar10_bb piar10_bb piar10_bb piar10_bb vdda vbba vssa piar10_bb piar10_bb pia_bb picc_bb picc_bb poa_bb poa_bb vbba vssd vddd Description Reference Output/Force (2.0V) Reference Bottom Output/Force (1.0V) output (1.23V) Internal Bias Internal Bias Analog Power (3.3V) Analog Bias Analog Ground Analog Input (Input Range 1.0V 2.0V) Analog Input (Input Range 1.0V 2.0V) open=use internal bias point VDD=power saving (standby), GND=normal Sampling Clock Input Digital Output Range Indicator Digital Bias Digital Digital Power (3.3V)
BW1254X
0.35µm 14-BIT 10MSPS
CORE CONFIGURATION
VDDA1 VBBA1 VSSA2 VSSA1 VDDA2 VBBA2
AINT AINC
bw1254x
REFTOP REFBOT
[MSB:LSB] DO[13:0]
CML1 ITEST STBY CKIN
0.35µm 14-BIT 10MSPS
BW1254X
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Analog Input Voltage Digital Input Voltage Storage Temperature Range Operating Temperature Range Symbol AINT/AINC Tstg Topr Value Unit
NOTE: Absolute maximum rating specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect unless otherwise specified. 100pF capacitor discharged through 1.5k resistor (Human body model)
OPERATING CONDITIONS Characteristics Supply Voltage Symbol VDDA1 VDDA2 VDDA3 AINT AINC Toper 3.15 3.45 Unit
Analog Input Voltage Operating Temperature
NOTE: strongly recommended that supply pins (VDDA1, VDDA2, VDDA3) powered from same source avoid power latch-up.
BW1254X
0.35µm 14-BIT 10MSPS
ELECTRICAL CHARACTERISTICS
Characteristics Differential Nonlinearity Integral Nonlinearity Offset Voltage Symbol ±0.7 Unit Test Condition Internal Voltage Reference REFTOP=2V REFBOT=1V Internal Voltage Reference REFTOP=2V REFBOT=1V REFTOP=2V REFBOT=1V
±1.5
NOTE: Converter Specifications VDDA1=VDDA2=VDDA3=3.3V, VSSA1=VSSA2=VSSA3=0V, Toper=25°C, REFTOP=2V, REFBOT=1V unless otherwise specified.
ELECTRICAL CHARACTERISTICS
Characteristics Maximum Conversion Rate Dynamic Supply Current Signal-to-Noise Distortion Ratio Total Harmonic Distortion Symbol IVDD SNDR Unit Test Condition AIN=AINT-AINC fc=10MHz (without system load) AIN=1MHz, Differential Input AIN=1MHz, Differential Input
NOTE: strongly recommended that supply pins (VDDA1, VDDA2, VDDA3) powered from same source avoid power latch-up.
0.35µm 14-BIT 10MSPS
BW1254X
CHART
Index 2047 2048 2049 4093 4094 4095 AINT Input 0.00081 0.00081 0.00161 0.00161 0.00242 1.64919 1.65000 1.65000 1.65081 1.65081 1.65161 3.29758 3.29839 3.29839 3.29919 3.29919 Digital Output 0000 0000 0000 0000 0000 0001 0000 0000 0010 0111 1111 1111 1000 0000 0000 1000 0000 0001 1111 1111 1101 1111 1111 1110 1111 1111 1111 1LSB=0.806mV VREF=3.3V AGND=0.0V
TIMING DIAGRAM
AINT
Input Sampling Period
CKIN
DO[13:0]
BW1254X
0.35µm 14-BIT 10MSPS
FUNCTIONAL DESCRIPTION
BW1254X CMOS four step pipelined Analog-to-Digital Converter. contains 5-bit flash Converters, 4bit, 3bit flash converters three multiplying Convertors. N-bit flash composed 2N-1 latched comparators, multiplying composed 2*(2N+1) capacitors fully-differential amplifiers. BW1254X operates follows. During first cycle external clock analog input data sampled, input held from rising edge external clock, which first 5-bit flash ADC, first multiplying DAC. Multiplying reconstructs voltage corresponding first 5-bit ADC's output, finally amplifies residue voltage second third flash ADC, MDAC worked same manner. Finally amplified residue voltage third multiplying last 3-bit flash decides final 3-bit digital digital code. BW1254X error correction scheme, which handles output from mismatch first, second, third fourth flash ADC.
MAIN BLOCK DESCRIPTION (Sample-and-Hold Amplifier) circuit that samples analog input signal hold that value until next sample-time. good small different value between analog input signal output signal. gain higher than 70dB 10MHz conversion rate, settling-time must shorten than 38ns with less than error voltage 14bit resolution. This consist fully differential amp, switching sampling capacitor. sampling clock non-overlapping clock (Q1, sampling capacitor value about 4pF. uses independent bias protect interruption other circuit. designed that open-loop gain higher than 70dB, phase margin higher than degrees. input block designed rail-to-rail architecture using complementary different pair. FLASH 5-bit flash converters compare analog signal (SAH output) with reference voltage, that results transfer MDAC digital correction logic block. realized fully differential comparators 31EA. Considering self-offset, dynamic feed through error, should distinguish 40mV least. First, comparators charge reference voltage sampling capacitors before transferred output.That operation performed phase discharging phase That comparators compare relative different values dual input voltage with dual reference voltage. output during operation stored pre-latch block Q1P. MDAC MDAC most important block this decides characteristics. MDAC consist stage amp, selection logic capacitor array (c_array). c_array's compositions capacitors charge analog input reference voltage, switches control path. Selection logic controls c_array internal switches. high, selection's output low, switches tsw1 off, switches tsw2 Therefore capacitors c_array charge analog input values held SHA.
0.35µm 14-BIT 10MSPS
BW1254X
CORE EVALUATION GUIDE
function evaluated external check bidirectional pads connected input nodes HOST back-end circuit. User want specific analog input range, reference voltages forced.
VDDA1 VBBA1 VSSA2 VSSA1 VDDA2 VBBA2
AINT AINC DO[13:0] [MSB:LSB]
bw1254x
REFTOP REFBOT CML1 ITEST
STBY CKIN
D[13:0]
D[13:0 Digital HOST CORE D[13:0] Bidirectional (ADC Function Test externally forced Digital Input)
BW1254X
0.35µm 14-BIT 10MSPS
PACKAGE CONFIGURATION
0.1u
Digital
0.1u
REFTOP REFBOT CML1 VDDA1 VDDA1 VBBA1 VSSA1 VSSA1 AINT AINC ITEST STBY VDDA3 VSSA3
VDDA2 VDDA2 VSSA2 VSSA2 CKIN DO[13] DO[12]
0.1u
0.1u
0.1u
0.1u
VBBA2
0.1u
DO[11]
BW1254X
DO[10] DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] TRIST
Analog Digital
0.1u
0.1u
NOTE: denotes Connection".
0.35µm 14-BIT 10MSPS
BW1254X
PACKAGE DESCRIPTION
Name REFTOP REFBOT CML1 VDDA1 VBBA1 VSSA1 AINT AINC ITEST STBY VDDA3 VSSA3 TRIST Type Description Reference Voltage Output Reference Output/Force Reference bottom Output/Force Internal Bias Internal Bias Analog Power (3.3V) Analog Bias Analog Ground Analog Input Analog Input open=use internal bias circuit VDDA=Power saving (Standby), GNP=Normal Power (3.3V) Ground Tri-state Buffer Input VDD=High Impedance, GND=Normal Range Indicator Normal='Low' Range='High' Digital Output (LSB) Digital Output Digital Output (MSB) Sampling Clock Input Digital Bias Digital Digital Power (3.3V)
28~39
DO[0] DO[1:12] DO[13] CKIN VBBA2 VSSA2 VDDA2
NOTE: TYPE denote Power Ground respectively.
BW1254X
0.35µm 14-BIT 10MSPS
PACKAGE DESCRIPTION (Continued)
Configuration
REFTOP REFBOT CML1 VDDA1 VDDA1 VBBA1 VSSA1 VSSA1 AINT AINC ITEST STBY VDDA3 VSSA3
VDDA2 VDDA2 VSSA2 VSSA2 VBBA2 CKIN DO[13] DO[12] DO[11] DO[10] DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] TRIST
BW1254X
0.35µm 14-BIT 10MSPS
BW1254X
USER GUIDE
Input Range want using single-ended input, should input range below. AINT: 0.5V 2.5V, AINC: 1.5V. want using differential input, should input range below. AINT: 1.0V 2.0V, AINC: 1.0V 2.0V. AIN: AINT AINC want changing input range (AIN span), force reference voltages. span -REF +REF REFTOP REFBOT
Power Consumption/Speed Optimization optimize power consumption, control ITEST voltage level precisely optimize ADC's speed also, control ITEST voltage level.
BW1254X
0.35µm 14-BIT 10MSPS
PHANTOM CELL INFORMATION
Pins core assigned externally (Package pins) internally (internal ports) depending design methods. term "External" implies that pins should assigned externally like power pins. term "External/internal" implies that applications these pins depend user.
VBBA
VSSA
VDDA
AINC
AINT
VBBA DO[0]
VSSA DO[1]
VDDA DO[2] DO[3]
14bit 10MSPS
ITEST DO[4] DO[5] DO[6]
bw1254x
REFBOT RETOP CML1 STBY
CKIN VDDD VSSD VBBD
DO[10]
DO[11]
DO[12]
DO[13]
DO[7]
DO[8]
DO[9]
0.35µm 14-BIT 10MSPS
BW1254X
PHANTOM CELL INFORMATION (Continued)
Name VDDA VSSA VBBA VDDD VSSD VBBD AINT AINC CKIN REFTOP REFBOT CML1 ITEST STBY DO[13] DO[12] DO[11] DO[10] DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] Usage External External External External External External External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal Separated from analog clean signals possible. exceed length 1,000um. Separate from other digital lines. Separate from other analog signals Maintain larger width shorter length pads. Separate from other digital lines. overlap with digtal lines. Maintain shotest path pads. Layout Guide Maintain large width lines pads. place port positions minimize length power lines. merge analog powers with anoter power from other blocks. good power ground source board.
BW1254X
0.35µm 14-BIT 10MSPS
FEEDBACK REQUEST
should quite helpful core development specify your system requirements following characteristic checking table fill additional questions. appreciate your interest products. Thank very much. Characteristic Analog Power Supply Voltage Digital Power Supply Voltage Resolution Reference Input Voltage Analog Input Voltage Operating Temperature Integral Non-linearity Error Differential Non-linearity Error Bottom Offset Voltage Error Offset Voltage Error Maximum Conversion Rate Dynamic Supply Current Power Dissipation Signal-to-noise Ratio Pipeline Delay Digital Output Format (Provide detailed description timing diagram) Between single input-output differential input-output configurations, which suitable your system why? Please comment internal/external configurations want have, have reason prefer some type configuration. Freely list those functions want implemented ADC, have any. Unit MSPS Remarks
0.35µm 14-BIT 10MSPS
BW1254X
HISTORY CARD
Version Date 99.6. 02.4.16 Modified Items Original version published (formal) Phantom information added datasheet format changed Comments
BW1254X
0.35µm 14-BIT 10MSPS
NOTES

BW1254X bw1254x CMOS 14bit analog-to-digital converter (ADC). con

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