BW1244D BW1244D CMOS 10Bit converter general application. This di
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0.35µm 10-BIT 0.5MSPS
BW1244D
BW1244D CMOS 10Bit converter general application. This digital analog converter R-2R ladder structure. maximum conversion rate 0.5MSPS
TYPICAL APPLICATIONS
Hard Disk Drive (HDD) Battery Operated Instruments Motor Control Systems General Applications
FEATURES
Resolution 10Bit Differential Linearity Error Integral Linearity Error Maximum Conversion Rate 0.5MSPS Power Consumption 9.9mW Power Down Mode Operation Temperature Range Power Supply 3.3V Single
BW1244D
0.35µm 10-BIT 0.5MSPS
FUNCTIONAL BLOCK DIAGRAM
VDDD
VSSD
VDDA
VSSA
VBBA
D[9:0] R-2R Ladder EXTREF DACCON PWRDN
Switch
VOUT
0.35µm 10-BIT 0.5MSPS
BW1244D
CORE DESCRIPTION
Name D[9:0] EXTREF DACCON Type picc_bb pia_bb picc_bb Description Digital Input Data (10bit) D[9] D[0] External Reference Input Control High EXTREF Output Power Down (Active Low) Voltage Reference Voltage Reference Bottom Analog Voltage Output Digital Power (+3.3V) Digital Ground (0.0V) Analog Power (+3.3V) Analog Ground (0.0V) Analog Bias (0.0V)
PWRDN VOUT VDDD VSSA VDDA VSSA VBBA Type Abbr. Analog Input Digital Input Analog Output Digital Output
picc_bb pia_bb pia_bb poa_bb vddd vssd vdda vssa vbba
Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
BW1244D
0.35µm 10-BIT 0.5MSPS
CORE CONFIGURATION
VDDD
VSSD
VDDA
VSSA
VBBA
D[9:0]
bw1244d
EXTREF DACCON
VOUT
PWRDN
0.35µm 10-BIT 0.5MSPS
BW1244D
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Analog Output Voltage Digital Input Voltage Reference Voltage Operating Temperature Range Symbol (VDDA,VDDD) VOUT D[9:0] Topr Value Unit
NOTES ABSOLUTE MAXIMUM RATING specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect VSS(VSSA VSSD VBBA) unless otherwise specified. 100pF capacitor discharged through 1.5k resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Supply Voltage Difference Reference Voltage Digital Input 'Low' Voltage Digital Input 'High' Voltage Operating Temperature Symbol VDDA VSSA VDDD VSSD VDDA VDDD Topr 3.15 -0.1 3.45 Unit
NOTE: strongly recommended that avoid power latch-up supply pins(VDDA,VDDD) driven from same source.
BW1244D
0.35µm 10-BIT 0.5MSPS
ELECTRICAL CHARACTERISTICS
(Converter Specifications VDDA=VDDD=3.3V, VSSA=VSSD=VBBA=0V, PWRDN=High, Top=25°C, VRT=3.3V, VRB=0.0V unless otherwise specified.) Characteristics Resolution Differential Linearity Error Integral Linearity Error Zero Scale Error
Symbol VZSE VFSE VoMAX VLSB
3.280 3.206
3.290 3.220
3.297 3.223
Unit Bits
Conditions VRT=3.3V VRB=0.0V VoMAX VOUT(D[9:0]=High) VLSB VoMAX 1023 AIN(254,255)
Full Scale Voltage Error
Maximum Output Voltage Size
NOTES: VZSE=VOUT(D[9:0]=Low) VFSE=VOUT(D[9:0]=High) {(VRT-VRB) 1023/1024 VRB}
0.35µm 10-BIT 0.5MSPS
BW1244D
ELECTRICAL CHARACTERISTICS
(Converter Specifications VDDA=VDDD=3.3V, VSSA=VSSD=VBBA=0V, load cap=25pF, Top=25°C, VRT=3.3V, VRB=0.0V unless otherwise specified.) Characteristics Maximum Conversion Rate Dynamic Supply Current Dynamic Supply Current (Power Down Mode) Analog Output Delay Analog Output Rise Time Analog Output Fall Time Analog Output Settling Time Power Down Time Power Down Time External Reference Transition Time External Reference Transition Time Symbol Ivdd1 Ivdd2 Unit MSPS Conditions Data Rate 0.5MHz Ivdd1 IVDDA IVRT IVDDD Data Rate 0.5MHz Ivdd2 IVDDA IVDDD Data Rate 0.5MHz PWRDN=LOW Data Rate 0.5MHz Data ®All HIGH Data Rate 0.5MHz Data HIGH Data Rate 0.5MHz Data HIGH Data Rate 0.5MHz Data HIGH VDD/2 PWRDN HIGH PWRDN HIGH DACCON HIGH EXTREF DACCON HIGH Ladder Output
Toff Texon Texoff
BW1244D
0.35µm 10-BIT 0.5MSPS
TIMING DIAGRAM
DATA 0000 000000 1111 111111
0000000000
1111111111
0000000000
VOUT DATA
VOUT
DATA
0000000000
1111111111
0000000000 0.5LSB
VOUT
PWRDN
VOUT
0.5LSB 0.0V
Toff
0.5LSB
DACCON
Texon VOUT
0.5LSB EXTREF
Texoff
0.5LSB
Output delay measured from point rising edge input data full scale transition. Settling time measured from point full scale transition output remaining within ±1/2 LSB. Output rise/fall time measured between points full scale transition.
0.35µm 10-BIT 0.5MSPS
BW1244D
FUCTION DESCRIPTION
bw1244d R-2R Ladder Block 10bit Block driving Output. R-2R Ladder Block generates binary weighted voltage (VRT/21 VRT/22 VRT/23 VRT/210) corresponding Digital Input Data n-bit Output total voltage summing each values. Output voltage, VMSB VRT/21 VLSB VRT/210 Output R-2R Ladder Block driven amp. DACCON signal controls input. When DACCON low, bw1244d operates normally R-2R Ladder output drives input when DACCON high, input connected EXTREF, bw1244d output buffered signal EXTREF. power down mode, only analog current (IVDDA) reduced.
BW1244D
0.35µm 10-BIT 0.5MSPS
CORE EVALUATION GUIDE
CORE
HOST
TEST PATH DACCON PWRDN EXTREF D[9:0] VDDD 3.3V
Location L1~L5
Analog Input 3.3V 0.0V
VSSD VDDA
3.3V
10uF TANTALUM CAPACITOR 0.1uF CERAMIC CAPACITOR FERRITE BEAD 0.1mh
bw1244d
VOUT VOUT
Description
VSSA VBBA
0.35µm 10-BIT 0.5MSPS
BW1244D
TESTABILITY
Whether internal logic testability, required able select values digital inputs (D[9:0]). above figure. Only check main function. (Linearity) Test Condition: VRT=3.3V, VRB=0.0V, PWRDN=High, DACCON=Low.
CORE LAYOUT GUIDE
VDDD VSSD VBBA
VDDA VSSA VBBA
D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
DACCON EXTREF
bw1244x
VOUT
BW1244D
0.35µm 10-BIT 0.5MSPS
Name D[9:0] DACCON PWDNB EXTREF VOUT VDDA VSSA VDDD VSSD VBBA
Property
Usage Internal External Internal External Internal External External External Internal External Internal External External External External External External
Layout Guide Digital Input Signal lines must have same length reduce propagation delay. Voltage reference lines (VRT VRB) must wide metal reduce voltage drop metal lines. VOUT signal should crossed signals should next digital signals minimize apacitive coupling between signals. recommended that thick analog power metal. When connected PAD, path should kept short possible. Digital power analog power separately used.
When core block connected other blocks, must double guard-ring using N-well active remove substrate coupling noise. that case, power metal should connected directly. Bulk power used reduce influence substrate noise.
0.35µm 10-BIT 0.5MSPS
BW1244D
PACKAGE CONFIGURATION
D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] (0.0V Typ.)
VDDD VDDD
VBBA VBBA
DACCON EXTREF
VSSD D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
BW1244D
VSSD
DACCON EXTREF VSSZ VSSZ VDDZ VDDZ VSSA VSSA
(VSS) 0.0V
VDDA VDDA
3.3V (VDD)
(3.3V norm operation)
PWRDN VOUT VOUT
PWRDN
VOUT
(3.3V Typ.)
Location L1~L5
Description 10uF TANTALUM CAPACITOR 0.1uF CERAMIC CAPACITOR FERRITE BEAD 0.1mh
BW1244D
0.35µm 10-BIT 0.5MSPS
PACKAGE DESCRIPTION
Name VDDD VSSD D[9:0] VOUT PWRDN VDDA VSSA VDDZ VSSZ EXTREF DACCON VBBA 8~17 23,24 25,26 29,30 36,37 38,39 41,42 43,44 47,48 5,6,7,18,19 20,21,22,27 28,32,33,34 35,40 Type Description Digital Power (3.3V) Digital Ground (0.0V) Digital Input Data Voltage Reference Bottom (0.0V) Voltage Reference (3.3V) Analog Voltage Output Power Down Mode (Low Active) Analog Power (3.3V) Analog Ground (0.0V) Power (3.3V) Ground (0.0V) External Reference Control (Low Normal Operation) (High Output buffered EXTREF) Analog Bias (0.0V) Connection
Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
0.35µm 10-BIT 0.5MSPS
BW1244D
BOARD LAYOUT CONSIDERATION
Board Considerations minimize noise power lines ground lines, digital inputs shielded decoupled. This trace length between groups (VDDA,VDDD) (VSSA,VSSD) pins should short possible minimize inductive ringing. Supply Decoupling Planes decoupling capacitor between power line ground line, 0.1uF capacitor used parallel with 10uF tantalum capacitor. digital power plane(VDDD) analog power plane(VDDA) connected ferrite bead, also digital ground plane(VSSD) analog plane(VSSA). This ferrite bead should located within 3inches BW1244D. analog power plane supplies power BW1244D analog output related devices.
BW1244D
0.35µm 10-BIT 0.5MSPS
FEEDBACK REQUEST
appreciate your interest products. have further questions, please specify attached form very much. ELECTRICAL CHARACTERISTIC Characteristics Supply Voltage Power dissipation Resolution Analog Output Voltage Operating Temperature Output Load Capacitor Output Load Resistor Integral Non-Linearity Error Differential Non-Linearity Error Maximum Conversion Rate Unit Bits Remarks
VOLTAGE OUTPUT Reference Voltage BOTTOM Analog Output Voltage Range Digital Input Format Binary Code Complement Code
CURRENT OUTPUT Analog Output Maximum Current Analog Output Maximum Signal Frequency Reference Voltage External Resistor Current Setting(RSET) Pipeline Delay want Power down mode? want Internal Reference Voltage(BGR)? Which want serial input data type parallel input data type? need 3.3V power supply your system?
0.35µm 10-BIT 0.5MSPS
BW1244D
HISTORY CARD
Version Date 00.02.22 Modified Items Version updated pictures texts modified with dac1236x's datasheet. format fonts datasheet same with dac1236x's datasheet. Version Updated page power down mode current 10uA) page (Output Load Resistor) Version Updated page functional description modified. page functon function page phantom cell modified table added. page number modified page Comments Reference datasheet DAC1236X
01.03.28
02.04.23
BW1244D
0.35µm 10-BIT 0.5MSPS
NOTES
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