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BW1223X BW1223X CMOS 8-bit converter video applications. two-step


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0.35µm 8-BIT 30MSPS
BW1223X
BW1223X CMOS 8-bit converter video applications. two-step ping-pong converter which consists reference resistor-matrix, 4-bit coarse fine converters. maximum conversion rate BW1223X 30MSPS supply voltage 3.3V single.
TYPICAL APPLICATIONS
Multi-media applications Frame-grabber scanner Camcorder Digital video (TV/VCR) Broadcasting studio equipments. Medical Electronics (ultra-sound imaging) High speed instruments (Digital scope, radar)
FEATURES
Process: CMOS Resolution: 8Bit Maximum Conversion Rate: 30MSPS Power Supply: 3.3V Single Power Consumption: 60mW Differential Linearity Error: LSB(Typ) Integral Linearity Error: LSB(Typ) On-Chip Reference Bias Resistors Reference Bias Adjustable Externally
BW1223X
0.35µm 8-BIT 30MSPS
FUNCTIONAL BLOCK DIAGRAM
VDDA
VSSA
VBBA
VDDD
VSSD
VBBD
COUT Coarse Sampling Amplifier Latch FREE Reference Matrix Error Correction Circuit Data Latches 3-state Output Buffer Latch Encoder DO[0] (LSB) DO[1] DO[2] DO[3] DO[4] DO[5] DO[6] Analog Fine Sampling Amplifier Timing Generator Latch FOUT Encoder DO[7] (MSB)
Fine Sampling Amplifier
VRTS
VRBS
0.35µm 8-BIT 30MSPS
BW1223X
CORE DESCRIPTION
Name VRTS VRBS VDDA VBBA VSSA DO[7:0] VBBD VSSD VDDD Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground Type poa_bb poa_bb poa_bb poa_bb vdda vbba vssa piar10_bb picc_bb pot2_bb vbba vssd vddd Description Internal Reference Bias (Short Self-Bias) 2.6V External Reference Bias Internal Reference Bottom Bias (Short Self-Bias) 0.6V External Reference Bottom Bias +3.3V Analog Power. Analog Bias. Analog Ground. Analog Input Input Span Clock Input Digital Output Digital Bias. Digital Ground. Digital Power.
BW1223X
0.35µm 8-BIT 30MSPS
CORE CONFIGURATION
VDDD
VDDA
VSSD
VBBD
VSSA
VBBA
DO[0] (LSB) DO[1] DO[2]
BW1223X
DO[3] DO[4] DO[5]
DO[6] DO[7] (MSB) VRTS VRBS
0.35µm 8-BIT 30MSPS
BW1223X
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Analog Input Voltage Digital Input Voltage Digital Output Voltage Reference Voltage Storage Temperature Range Symbol VOH, VRT/VRB Tstg Value -0.3 -0.3 VDD+0.3 -0.3 VDD+0.3 -0.3 VDD+0.3 -0.3 VDD+0.3 Unit
NOTES: ABSOLUTE MAXIMUM RATING specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect unless otherwise specified. 100pF capacitor discharged through 1.5K resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Supply Voltage Difference Reference Input Voltage Analog Input Voltage Clock High Time Clock Time Digital Input Voltage Digital Input Voltage Operating Temperature Symbol VDDA VSSA VDDD VSSD VDDA VDDD Tpwh Tpwl Topr 3.15 -0.1 16.6 16.6 3.45 Unit
NOTE: strongly recommended that supply pins (VDDA, VDDD, VDDP) powered from same source avoid power latch-up.
BW1223X
0.35µm 8-BIT 30MSPS
ELECTRICAL CHARACTERISTICS
Characteristics Resolution Reference Current Differential Linearity Error Integral Linearity Error Bottom Offset Voltage Error Offset Voltage Error Symbol IREF 6.25 Unit Bits VRT: 2.6V VRB: 0.6V AIN: 2.6V (Ramp Input) 1MHz 20MHz AIN(0,1) AIN(254,255) Conditions
NOTES: Converter Specifications (unless otherwise specified) VDDA=3.3V VDDD=3.3V VSSA=GND VSSD=GND Ta=25°C TBD: Determined
ELECTRICAL CHARACTERISTICS
Characteristics Clock High Time Clock Time Conversion Rate Dynamic Supply Current Digital Output Data Delay Signal Noise Distortion Ratio (SNDR) Symbol Tpwh Tpwl (IREF) SNR1 SNR2 SNR3 16.6 16.6 (6.25) Unit MSPS I(VDDA) I(VDDD) IREF 30MHz "DELAY TIMING DIAGRAM" AIN: 4MHz respectively (Sine Input) 30MHz Conditions
0.35µm 8-BIT 30MSPS
BW1223X
DELAY TIMING DIAGRAM
(-2)
(-1) PIPELINE DELAY
BW1223X
0.35µm 8-BIT 30MSPS
FUNCTIONAL DESCRIPTION
BW1223X two-step ping-pong converter with subranging reference resistor matrix. consists 4-bit coarse converter fine converter which accuracy 4.459 bits. latching comparators coarse fine converters have offset cancellation features built such auto-zero averaging, number comparators coarse converter fine one. sampling operation fine converter performed, through analog MUXs, ping-pong manner between sampling amplifier banks each which consists latching comparators. reference resistor matrix switch different sets reference voltages, according states coarse comparator digital outputs, fine sampling amplifier banks. This fact CMOS auto-zero comparator surely eliminate extra pain implementing high accuracy converter bits more, thus low-power, high-performance high speed converter results. operation BW1223X stated follows. (refer 'TIMING DIAGRAM' that follows) During first cycle external clock, analog input 'AIN' traced each converter, falling edge 'AIN' sampled held compared with 16-level coarse reference voltages. result comparison coarse comparator, 'COUT', latched used select fine reference voltage 'FREF' which, compared with sampled analog input, fine sampling amplifier banks. result comparison reproduced successive comparators with sufficiently large gain then multiplexed latching digital logic ping-pong manner. Latching logic coarse fine converters refine results comparison generate converter output 'FOUT' 'COUT', from which final digital output 'DO' generated. overall pipeline delay, measured from sampling instance time that 'DO' comes available, clock cycles. BW1223X implements error correction scheme correct error which stems from mismatch between offset coarse converter that fine converter. This scheme handle coarse comparator offset error LSBs helps reducing differential linearity error consequently.
0.35µm 8-BIT 30MSPS
BW1223X
TIMING DIAGRAM
Coarse Sample
Coarse Compare
FREF
COUT
Fine Sample
Fine Compare
Fine Sample
Fine Compare
FComp1
FComp2
FComp1
FComp2
FComp1
FOUT
Clock Pipeline Deley
BW1223X
0.35µm 8-BIT 30MSPS
CORE EVALUATION GUIDE
function evaluated external check bidirectional pads connected input nodes HOST back-end circuit. reference voltages biased externally through pins, otherwise these voltages internally generated with shorted VRTS VRBS respectively.
+3.3V Analog Power
+3.3V Digital Power
DO[0] (LSB) VDDA VSSA VBBA VBBD VSSD VDDD DO[1] DO[2] DO[3] AINC
BW1223X
DO[4] DO[5] DO[6]
HOST CORE
CKIN
VRTS
VRBS
DO[6] (MSB)
Bidirectional 2.6V 0.6V Bottom Reference Reference Function Measuring Digital Input Forcing
NOTES: 10uF electrolytic capacitor unless otherwise specified 0.1uF ceramic capacitor unless otherwise specifed External pias. Internal pias.
0.35µm 8-BIT 30MSPS
BW1223X
PACKAGE CONFIGURATION
+0.6V +2.6V Reference Reference Bottom
3.3V Digital Power
VDDD
VDDD
VSSD
VSSD
VRBS
VRTS
3.3V Analog Power Analog Input (Input Span VRB-VRT)
VDDA VDDA VBBA VSSA
VBBD
VSSA AINT
BW1223X
DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[0] DO[1] Digital Output Bits Through
3.3V Power
VDDP VSSP
Clock Signal
Digital Output Bits NOTES: 10uF electrolytic capacitor unless otherwise specified 0.1uF ceramic capacitor unless otherwise specifed NOTES: test function checking external bidirectional connected internal signal path. (ElectroStatic Discharge) sensitive device. Although digital control inputs diode protected, permanent damage occur devices subjected high electrostatic discharges. recommended that unused devices stored conductive foam shunts avoid performance degradation loss functionality. protective foam should discharged destination socket before devices inserted. denotes Connection".
BW1223X
0.35µm 8-BIT 30MSPS
PACKAGE DESCRIPTION
Name VRTS VRBS VDDA VBBA VSSA VDDP VSSP DO[7:0] VBBD VSSD VDDD Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground 34~27 Type Description +2.6V External Reference Bias. Internal Reference Bias. (Short VRTS Self-Bias.) Internal Reference Bottom Bias. (Short VRBS Self-Bias.) +0.6V External Reference Bottom Bias. +3.3V Analog Power. Analog Bias. Analog Ground. Analog Input. Input Span VRB. Power Ground Clock Input. Digital Output. Digital Bias. Digital Ground. Digital Power.

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