BW1222L samsung analog front end(AFE) CCD/CIS image signal integr

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BW1222L samsung analog front end(AFE) CCD/CIS image signal integr

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0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
samsung analog front end(AFE) CCD/CIS image signal integrated analog signal processor color image signal. converts CCD/CIS output signal digital data. includes three-channel CDS(Correlated Double Sampler) circuit, PGA(Programmable Gain Amplifier), 10-bit analog digital converter with reference generator. parallel data provides simple interface 8-bit microcontroller.
APPLICATIONS
Color Scanner Digital Copiers Facsimile General Purpose CCD/CIS imager
FEATURES
10-bit 6MSPS Converter Integrated Triple Correlated Double Sampler 3-Channel MSPS Color Mode Analog Programmble Gain Amplifier Internal Voltage Reference Wide clamp level controllability signal Missing Code Guaranteed Microcontroller-Compatible Control Interface Operation 3.3V Power Supply CMOS Power Dissipation
SPECIFICATION
Resolution: 10-bit Conversion Rate: MHz(2 MHz*3) Supply Voltage: Power Dissipation: mW(Typical)
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
FUNCTIONAL BLOCK DIAGRAM
GREEN
INPUT OFFSET REGISTER
D[9:0]
BLUE GAIN REGISTER PORT
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
CORE DESCRIPTION
Name VDDA1, VDDA2 VSSA1, VSSA2 REFT REFB VCOM R_VIN G_VIN B_VIN STRTLN CDS1_CLK CDS2_CLK ADCCLK VDDA3 VSSA3 D[9:0] AD[2:0] TEST_S1, TEST_S2 TEST_CTL TEST_OUT MCTL1, MCTL2 EXT_MCTL Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground Type vdda vssa vbba pia_bb pia_bb pia_bb piar10_bb piar10_bb piar10_bb picc_bb picc_bb picc_bb picc_bb vddd vssd picc_bb picc_bb picc_bb picc_bb poa_bb picc_bb picc_bb picc_bb poa_bb picc_bb picc_bb Analog Supply Analog Ground Analog Bulk Reference Decoupling Reference Decoupling Analog Common Voltage Analog Input; Analog Input; Green Analog Input; Blue STRTLN indicates beginning line Reset Clock Pulse Input Data Clock Pulse Input Converter Sample Clock Input Digital Supply pins;VDDA3, VDDA4) Digital Ground pins;VSSA3, VSSA4) Chip Select; Active Write Strobe; Active Read Strobe; Active Output Enable; Active Data Inputs/Outputs Register Select Channel Select Test Mode Test Mode Control; Active Test Mode Output Channel Select External Control External Control; Active Description
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
CODE CONFIGURATION
REFT VDDA1,VDDA2 VSSA1,VSSA2,VBBA
VCOM
REFB
R_VIN G_VIN B_VIN R_VIN
bw1222l
VSSA3,VSSA4
TEST_OUT TEST_CTL TEST_S1,TESTS2 EXT_MCTL MCTL1,MCTL2 D[9:0] AD[2:0]
VDDA3,VDDA4 STRTLN CDS1_CLK CDS2_CLK ADCCLK
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Analog Input Voltage Digital Input Voltage Reference Voltage Storage Temperature Range Operating Temperature Range Symbol VRT/VRB Tstg Topr Value Unit
NOTES: ABSOLUTE MAXIMUM RATING specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect unless otherwise specified. 100pF capacitor discharged through 1.5k resistor (Human body model)
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
ANALOG SPECIFICATIONS
(VDDA1, VDDA2=3.3V, VDDA3=3.3V, ADCCLK=6MHz, CDS1_CLK=2MHz,CDS2_CLK=2MHz, Gain=1 unless otherwise noted) Characteristics Resolution Signal-to-Noise Distortion Ratio Conversion Rate 3-Channel with 1-Channel with Differential Nonlinearity Integral Nonlinearity Unipolar Offset Error Gain Error Anlog Input Full-Scale Input Input Capacitance Reference Reference Bottom Power Supply Analog Voltage Digital Voltage Analog Current Digital Current Power Consumption Temperature Range VDDA VDDD IDDA IDDD 0.06 3.15 3.15 3.45 3.45 SNDR Symbol Unit Bits Comment
MSPS MSPS %FSR %FSR Vp-p 3.3V±5% 3.3V±5%
DIGITAL SPECIFICATIONS
(VDDA1, VDDA2=3.3V, VDDA3=3.3V, ADCCLK=6MHz, CDS1_CLK=2MHz, CDS2_CLK=2MHz, CL=20pF unless otherwise noted) Characteristics High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current High Level Output Voltage Level Output Voltage Symbol Unit IoH=0.5mA IoL=-0.5mA Comment
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
TIMING SPECIFICATIONS
Characteristics 3-Channel Conversion Rate 1-Channel Conversion Rate CDS1_CLK Pulse Width CDS2_CLK Pulse Width CDS2_CLK2 Pulse Width CDS1_CLK Falling CDS2_CLK2Rising CDS2_CLK Falling CDS1_CLK Rising ADCCLK Pulse Width CDS2_CLK Rising ADCCLK Rising CDS2_CLK Falling ADCCLK Falling ADCCLK Rising CDS2CLK Falling STRTLN Rising, Falling Setup Hold Output Delay Register Address Setup Time Register Address Hold Time Data Hold Time Register Chip Select Setup Time Register Chip Select Hold Time Register Read Pulse Width Write Pulse Width Register Read Data Valid Output Enable High Tri-State Tri-State Data Valid Aperture Delay Latency Channel mode tC1CLK tC2CLK tC2CLKB tC1C2A tC2C1A tADCLK tC2ADA tC2ADB tADC2A tADDT tCSS tCSH tPWR tPWW tDEV Symbol Unit ADCCLK Cycles
NOTE: Aperture delay timing measurement between sampling clocks CDS. measured from falling edge CDS2_CLK input when input signal held data conversion
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
TIMING DIAGRAM
3-CHANNEL MODE
Analog Input CDS1_CLK tC1C2A
R0,G0,B0
R1,G1,B1
R2,G2,B2
tC2C1A
tC1CLK
CDS2_CLK
tC2ADA tADCLK
tADC2A
tC2CLKB
ADCCLK STRTLN
3-CHANNEL MODE
Analog Input
R0,G0,B0
R1,G1,B1
R2,G2,B2
tC2ADA CDS2_CLK tADCLK ADCCLK
tADC2A
tC2CLKB
STRTLN
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
1-CHANNEL MODE
Analog Input CDS1_CLK tC1CLK tC2CLK CDS2_CLK tC2ADA ADCCLK tC2ADB tADCLK tC1C2A tC2C1A
STRTLN
1-CHANNEL MODE
Analog Input
R0,G0,B0
R1,G1,B1
R2,G2,B2
tC2CLK CDS2_CLK tC2ADA ADCCLK tC2ADB tADCLK
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
TIMING
Input ADCCLK
A(n)
A(n+1)
tADDT ADCOUT A(n-2)[9:0] A(n-1)[9:0] A(n)[9:0]
WRITE TIMING
AD[2:0] tCSS tPWW D[7:0] tCSH
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
READ(1) TIMING
AD[2:0] tCSS tPWR tCSH
D[7:0]
Read(1)' means microcontroller reads D[7:0]/MPU[7:0].
READ(2) TIMING
ADCCLK tADDT
D[9:0]
tDEV
should keep 'High' read.
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
FUNCTIONAL DESCRIPTION
3-Channel Operation with This mode enables simultaneous sampling triple output CCD. waveforms coupled VINR, VING VINB pins where they automatically biased appropriate voltage using on-chip clamp. internal CDSs take samples incoming pixel data; first samples taken during reset time while second samples taken during data portion input pixels. When STRTLN low, internal circuitry reset next rising edge ADCCLK; multiplexer switched channel. 3-Channel Operation This mode enables simultaneous sampling triple output something like that. functions replaced with sample hold amplifiers. input waveforms either coupled restored VINR, VING VINB pins. input reference voltage this mode will defined clamp level control register. When STRTLN low, internal circuitry reset next rising edge ADCCLK; multiplexer switched channel. 1-Channel Operation with This mode enables single channel monochrome sampling. waveforms coupled analog input where they automatically biased appropriate voltage using on-chip clamp. Bit2 bit3 configuration register select desired input among red, green blue. 1-Channel Operation This mode enables single-channel monochrome sampling. function replaced with sample hold amplifier. input waveforms either coupled restored analog input pin. input reference voltage this mode will defined clamp level control register. Bit2 bit2 configuration register select desired input among red, green blue.
MAIN BLOCK DESCRIPTION
Programmable Gain Amplifier analog programmable gain accommodate wide range input voltage spans. transfer function follows.
H(X) 1/6*X 5/6,
where range Thus, minimum gain value equal 5/6, maximum gain value equal transfer function linearity linear scale. overall gain equal analog gain multiplied digital gain. multiplier should required back AFE. REGISTER OVERVIEW port accessed through pins port format.(next page)
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
BLOCK DIAGRAM
VDDA1,
VSSA1,
VDDA3
VSSA3
REFT
VCOM
REFB
MCTL2
R_VIN
CLAMP
MCTL1 EXT_MCTL
TEST_S2
R_OFFSET[7:0] R_CLAMP[2:0]; only mode R_GAIN[4:0]
TEST_S1
TEST_CTL
G_VIN
CLAMP
GREEN
TEST_OUT
D[9:0]/ MPU[7:0]
G_OFFSET[7:0] G_CLAMP[2:0]; only mode G_GAIN[4:0]
B_VIN
CLAMP
BLUE
Configuration
B_OFFSET[7:0]
Register
B_CLAMP[2:0]; only mode
B_GAIN[4:0] R_OFFSET[7:0] G_OFFSET[7:0] B_OFFSET[7:0]
Input Offset Register (R,G,B)
PORT
AD[2] AD[1]
R_CLAMP[2:0], R_GAIN[4:0] G_CLAMP[2:0], G_GAIN[4:0] B_CLAMP[2:0], B_GAIN[4:0]
Gain Clamp Level Register (R,G,B)
AD[0]
CDS1_CLK
CDS2_CLK
STRTLN
ADCCLK
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
Table Port Format Configuration Register Input Offset register Green Input Offset Register Blue Input Offset Register Gain Clamp Control Register Green Gain Clamp Control Register Blue Gain Clamp Control Register Reserved Register
Configuration Register Clamp mode select1 Clamp mode select0 External Reference Color1 (Single Channel) Color0 (Single Channel) Single Channel Enable
Single Channel Color Pointer Bit3 Bit2 Color Green Blue Reserved
Clamp Mode Selection Bit3 Bit2 Clamp Mode Line Clamp Pixel Clamp Clamp Reserved
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
Input Offset Register
Gain Clamp Control Register PGA2 PGA1 CCC0 PGA4 PGA3 PGA2 PGA1 PGA0
NOTE: CCCn: Clamp Control
EXTERNAL MULTIPLEXER CONTROL MODE
EXT_MCTL "LOW" MCTL2 MCTL1 Color Green Blue Reserved
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
OVERALL TRANSFER FUNCTION
overall transfer function calculated follows. ADCout=[(Vin+Input_Offset)* PGA_Gain]/(2*REF)*1024, where equal (REFT-REFB) Input _Offset means value input offset register. analog offset range input offset register varied between 150mV -150 8-bit data format input offset register straight binary coding. Thus, 'zeros' data word corresponds -150 'ones' data word corresponds maximize dynamic range input, necessary program input offset register code move code corresponding black level towards 'zero'. case processing signal, 3bits gain clamp control register allocated control clamp level. Like input offset register, 3-bit data format straight binary coding. 'zeros' data word corresponds 'ones' data word corresponds
INPUT COUPLING CAPACITOR
Because offset present output CCD, some kind restoration required. case enable mode, simplify input level shifting, decoupling capacitor used conjuction with internal input circuitry. capacitor charging discharging depends clamping time, analog input resistance output resistance circuit driving coupling capacitor. clamping time typically (n*T), where number periods CDSCLK1 asserted period assertion. CDSCLK2 should asserted during clamping time. And, STRTLN must line clamp mode clamping operation. analog input resistance equal recommended input coupling capacitor more than 0.01uF. Thus, extend clamping time, time transport motor moves scanner carriage available, example.
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
TEST MODE EACH OUTPUT (OPTIONAL)
possible test each output that connected next block external control pins. each output shown with external test pin. Test mode control(TEST_CTL) should 'LOW' operate test mode. Color Pointer Test Mode TEST_S2 TEST_S1 Color Green Blue Reserved
TEST
<TEST_CTL> <TEST_S2> <TEST_S1>
<TEST_OUT>
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
POWER-ON INITIALIZATION
CALIBRATION
Write configuration register operation channel mode color pointer clamp mode
Decide clamp level mode (Refer next page) gain (Input offset
Scan dark line
Write gain register gain one(00001)
Compute pixel offsets
input offset Write input offset register 0mV(10000000)
odd/even offset back
another color
another color
gain/offset size back
external pixel offset back
Scan white line
Compute pixel gains back
Adjust gain
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
CLAMP LEVEL DECISION EACH INPUT
*Assume that gain user modify this alogorithm required overall system
Write clamp control register (111)
Decrease clamp control register
Scan clamp level input
[Repeatedly, scan clamp level. Average output]
output
Scan dark line
[MIN(ADC output) Minimum value pixels]
MIN(ADC output)
MIN(ADC output)
[(100mV)/(2V) 1024
Increase clamp control register
Decrease clamp control register Scan dark line
MIN(ADC output)
Increase clamp control register
MIN(ADC output)
Increase clamp control register calibration
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
CORE EVALUATION GUIDE
0.1u 0.1u 0.1u
VDDA1,VDDA2 VSSA1,VSSA2,VBBA
REFT
VCOM
REFB
R_VIN G_VIN B_VIN R_VIN
bw1222l
VSSA3,VSSA4
TEST_OUT TEST_CTL TEST_S1,TESTS2 EXT_MCTL MCTL1,MCTL2 D[9:0] AD[2:0]
CDS1_CLK CDS2_CLK ADCCLK
VDDA3,VDDA4 STRTLN
TIMING GENERATOR
INTERFACE
ASIC
Externally forced digital input/output
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
PACKAGE CONFIGURATION
digital pins should well decoupled analog ground plane.
0.1u 0.01u
0.1u 0.1u 0.1u
0.01u 0.01u 0.1u
R_VIN G_VIN B_VIN IBIAS VDDA1 VDDA1 VSSA1 VSSA1 VBBA SPEEDUP STBY ITEST
AD[2] AD[1] AD[0] MCTL2 MCTL1 EXT_MCTL
BW1222L
TEST_CTL TEST_S2 TEST_S1 INDEX2 INDEX1 D[9] D[8]
D[7]
0.1u
0.1u
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
PACKAGE DESCRIPTION
Name TEST_OUT VDDA2 VDDA2 VSSA2 VSSA2 VSSA4 VSSA4 VDDA4 VDDA4 D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] INDEX1 INDEX2 TEST_S1 TEST_S2 TEST_CTL EXT_MCTL MCTL1 MCTL2 AD[0] AD[1] AD[2] Type Description Analog Output Test Mode Analog Power Converter Analog Power Converter Analog Ground Converter Analog Ground Converter Output Buffer Ground Output Buffer Ground Output Buffer Power Output Buffer Power Digital Output (LSB) Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output (MSB) Index Resistor(+) Index Resistor(-) Color Pointer Test Mode Color Pointer Test Mode Test Mode Control (Active Low) Connected Connected Control Mode Selection(Active Low) Color Pointer Control Color Pointer Control Register Selection Register Selection Register Selection
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
PACKAGE DESCRIPTION (Continued)
Name ADCCLK CDS2_CLK CDS1_CLK STRTLN VDDA3 VDDA3 VSSA3 VSSA3 VCOM REFT REFB R_VIN G_VIN B_VIN IBIAS VDDA1 VDDA1 VSSA1 VSSA1 VBBA SPEEDUP STBY ITEST Type Description Chip Selection (Active Low) Read Strobe (Active Low) Write Strobe (Active Low) Output Enable (Active Low) Converter Clock Input Data Clock Input Reset Clock Input Start Line (Active Low) Digital Power Digital Power Digital Ground Digital Ground Connected Reference Middle Voltage Reference Voltage Reference Bottom Voltage Analog Input Green Analog Input Blue Analog Input Current Bias Control Analog Power Analog Power Analog Ground Analog Ground Analog Ground Connected Connected Connected Connected Speed-Up Selection Converter Power Down Mode Converter Current Bias Control Converter
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
USER GUIDE
SYSTEM CONFIGURATION necessary that output signal analog front shading-compensated back logic block including subtracter multiplier.
(Shading-Compensation Block)
Memory
CCD/CIS
Subtracter Multiplier
Controller
Table Output Controls DOUT Input Output Output
NOTE: Don't Care Unknown (Not recommended) High Impedance
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
FEEDBACK REQUEST
SPECIFICATION Characteristics Resolution Signal-to-Noise Distortion Ratio Conversion Rate 3-Channel with 1-Channel with Differential Nonlinearity Integral Nonlinearity Unipolar Offset Error Gain Error Anlog Input Full-Scale Input Power Supply Analog Voltage Digital Voltage Power Consumption Temperature Range VDDA VDDD SNDR Symbol Unit Bits Comment
MSPS MSPS %FSR %FSR Vp-p
What want choose power supply voltages? example, analog needs digital 3.3V/5V. Which modes overall system (Refer page Would define gain range input offset range Could explain external/internal configurations required? Should interface compatible with possible, present other requirements below.
0.35µm CCD/CIS SIGNAL PROCESSOR
BW1222L
HISTORY CARD
Version 1998.10 Release formal datasheet Date Modified Items Original version published (preliminary) Comments
BW1222L
0.35µm CCD/CIS SIGNAL PROCESSOR
NOTES

BW1222L samsung analog front end(AFE) CCD/CIS image signal integr

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