BW1221L_2CLK BW1221L_2CLK CMOS Dual 10Bit converter general video

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BW1221L_2CLK BW1221L_2CLK CMOS Dual 10Bit converter general video

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0.35µm 10-BIT 80MSPS DUAL
BW1221L_2CLK
BW1221L_2CLK CMOS Dual 10Bit converter general video applications. typical conversion rate 80MSPS (maximum 100MSPS) supply voltage 3.3V single. external 1.0V voltage reference(VREF) single resistor (RSET) control full_scale output current.
TYPICAL APPLICATIONS
High Definition Television(DTV,HDTV) High Resolution Color Graphics Hard Disk Driver(HDD) CAE/CAD/CAM Image Processing Instrumentation Conventional Digital Analog Conversion
FEATURES
80MSPS 1CLK pipeline delay operation +3.3V CMOS monolothic construction 1.0LSB differential linearity error(Max) ±2.5LSB integral linearity error(Max) ±External voltage reference Dual Channel 10-Bit voltage parallel input channel High impedance single current output Bineary coding input High impedance analog output current source
BW1221L_2CLK
0.35µm 10-BIT 80MSPS DUAL
FUNCTIONAL BLOCK DIAGRAM
econ Latch
First Latch1
Deco
D1[9:0]
econ Latch
Firs Latch2
Deco
D2[9:0]
COMP
CLK1
CLK2
CLKG
VREF
IREF
0.35µm 10-BIT 80MSPS DUAL
BW1221L_2CLK
CORE DESCRIPTION
Name D1[9:0] D2[9:0] CLK1 CLK2 VREF COMP IREF VDDA VDDD VSSA VSSD Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground Type picc_bb picc_bb poa_bb poa_bb picc_bb picc_bb pia_bb pia_bb picc_bb pia_bb vdda vddd vssa vssd vbba Description Channel Digital input Channel Digital input Channel Current Output Channel Current Output Clock Input channel Clock Input channel Reference voltage input External capacitance connection Power-Down High Enable external resistor connection Analog Power Digital Power Analog Ground Digital Ground Bulk Bias
BW1221L_2CLK
0.35µm 10-BIT 80MSPS DUAL
CORE CONFIGURATION
VDDD
VSSD
VDDA
VSSA
D1[9:0]
bw1221l_2clk
D2[9:0]
Note
External when it's been embedded Interrnal when it's been embedded
CLK1
CLK2
COMP
IREF
VREF
0.35µm 10-BIT 80MSPS DUAL
BW1221L_2CLK
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Voltage Digital Voltage Storage Temperature Range Symbol VDDA VDDD Tstg Values VSSD-0.3 VDDD+0.3 Unit
NOTES strongly recommended that avoid power latch-up supply Pins(VDDA,VDDD) driven from same source, ground Pins(VSSA,VSSD,VBB) driven from same source. Absolute Maximum Rating values should applied individually while other parameters within specified operating conditions. Function operation under these conditions implied. Applied voltage must limited specified range. Absolute Maximum Ratings values beyond which device damaged permanently. Normal operation guaranteed.
RECOMMENDED OPERATING CONDITIONS
Characteristics Operating Supply Voltage Digital input Voltage HIGH Operating Temperature Range Output Load(effective) Data Input Setup Time Data Input Hold Time Clock Cycle Time Clock Pulse Width High Clock Pulse Width IREF Current Zero_level Voltage External Reference Voltage Symbol VDDA,VDDD Topr tCLK tPWH tPWL IREF VREF 3.15 0.7VDDD -10.0 12.5 0.33 -1.2 3.45 0.3VDDD 10.0 Unit
NOTES: strongly recommended that supply pins(VDDA,VDDD) should driven from same source avoid power latch-up. data above could available with less than 10pF parasitic load capacitance node.
BW1221L_2CLK
0.35µm 10-BIT 80MSPS DUAL
ELECTRICAL CHARACTERISTICS
Characteristics Resolution Differential Linearity Error Integral Linearity Error Full Scale Current Channel Monotonicity Size Maximum Output Compliance Exteranl Refence Voltage Power Supply Current Symbol ±0.6 ±1.8 Guaranteed ±1.0 ±2.5 Unit Bits
NOTES: Converter Specifications (unless otherwise specified) VDDA=3.3V VDDD=3.3V VSSA=VSSD=VBB=GND Ta=25°C RL1=RL2=249, VREF=1.0V, Rset TBD: Determined
ELECTRICAL CHARACTERISTICS
Characteristics Conversion Speed Analog Output Delay Analog Output Rising Time Analog Output Falling Time Analog Output Settling Time Glitch Impulse Pipeline Delay Power Supply Rejection Ratio (f=1KHz, COMP=0.1uF) Feedthrough Power_Down Time Power_Down Time Symbol fMAX Tset fdth ±120 ±200 Unit pVsec Clock
NOTE: above pararameters tested through temperature range. Clock data feedthrough function amount overshoot undershoot digital inputs. Settling time does include clock data feedthrough. Glitch impulse include clock data feedthrough.
0.35µm 10-BIT 80MSPS DUAL
BW1221L_2CLK
FUCTION DESCRIPTION
This dual 10bit 80MSPS digital analog data converter uses segment architecture 5bits sides binerary-weighted architecture 5bits side. contains latch block, decoder block, latch block, block, CM(current mirror)block analog switch block. This core uses reference current decide 1LSB current size dividing reference current 68times. reference current must constant reference curretn constant using block with high gain. most significant block this core analog switch block must maintain uniformity each switch, layout designer must care matching characteristic analog switch block. more than supply current dissipated analog switch block block. uses samsung(SEC) standard cell digital cell latch,decoder buffer. adjust full current output, must decide "Rset" resistor value(connected IREF pin) "Vbias" voltage value(connected VREF pin). voltage output obtained connecting RL1(connected pin), RL2(connected pin). maximum output voltage limit 1.2V. must decide RL2, Vbias Rset carefully Vout(p-p) exceed 1.2V. contains power-save regretfuly isn't complete. want more complete power-save mode, call back us(SEC). provide more complete power-save mode control scheme.
BW1221L_2CLK
0.35µm 10-BIT 80MSPS DUAL
TIMING DIAGRAM
D[9:0]
High
0000000000
data(1111111111)
0000000000
Tset
Vout(p-p)
Clocks Pipeline Delay
D[9:0]
data[1] data[2]
data[3]
Vout[1]
Vout[2]
D[9:0]
Vout(pp)
data1(1111111111)
NOTES: Behavioral Modeling provided Verilog modeling file which includes spec pipeline delay, setup_time, hold_time, rising time, falling time, clock frequency, Output delay(Td) measured from point rising edge full scale trasition Settling time(Tset) measured from point full scale transition output remaining within ±1LSB. Output rising(Tr)/falling(Tf) time measured between points full scale transition. Power_down doesn't need clock signal.
0.35µm 10-BIT 80MSPS DUAL
BW1221L_2CLK
CORE EVALUATION GUIDE
3.3V 3.3V
VDDD VSSD VDDA VSSA D1[9] D1[8] D1[7] D1[6] D1[5] D1[4] D1[3] D1[2] D1[1] D1[0]
HOST CORE
D2[9] D2[8] D2[7] D2[6] D2[5] D2[4] D2[3] D2[2] D2[1] D2[0]
CLK1 CLK2 COMP IREF VREF
bw1221l_2clk
CHANNEL SELECT
PATH SELECT CLK2 input TEST PATH CLK1 input VDDA
COMP
RSET
1.0V
LOCATION CCOMP,Cc RSET VREF 0.1uF CERAMIC CAPACITOR 10uF TANTALUM CAPACITOR 1.0V Voltage Supply
DESCRIPTION
BW1221L_2CLK
0.35µm 10-BIT 80MSPS DUAL
change resolution needed change resolution, many more significant bits, rest (less significant bits) grounded supplied VDDD power. That need only 8bits, have 8bit digital input pin, digital input have grounded supplied VDDD power. change output range change output swing using following equation: Vout Vref Rset*68) 1023 This equation implies that determine output swing changing value Vref, Rset, where output swing limited 1.2V. ABOUT TESTABILITY want test over full spec channel main chip(that when used block main chip) must many pins(for 20pins digital inputs, 2pins analog outputs, etc) main chip test this block. usually nearly impossble 'cause total number pins main chip limited. more efficient method testing this block needed. offer ways testing efficiently here reference. remember this best way. test your testing method. FIRST METHOD TESTABILITY first adding only extra 10PADs 10bit parallel digital inputs 2PADs channel selecting path selecting. check three channels one, that test only channel time. Therefore test three channels turn cannot check channel time. this method needs extra switch blocks testing. Furthermore confirm channels testing only channel because channels have same architecture share same analog reference block(OPAMP, BGR). This characteristic makes simple test this block(when embedded main chip) adding another 10PADs parallel digital inputs 2PADs selecting channel analog switch block three channels. SECOND METHOD TESTABILITY above extra 12PADs burden you, then test this second method reduce extra PADs testing. What different from above method that this needs only extra PADs(one 1bit serial digital input other clock signal), must insert extra serial parallel converter block converting 1bit 10times high speed digital input 10bit parallel digital inputs. this block needs considerable area. Further this method also needs extra 2PADs channel selecting path selecting. ANALYSIS voltage applied VREF measured IREF node voltage value proportioned reference current value resistor which connected IREF node. estimate full scale current value measuring voltage, check characteristics OPAMP. reference, VREF voltage applied VREF given IREF node, current flowing through RSET resistor(connected IREF pin) given VREF/RSET. voltage applied VREF same with IREF node, "This chip does work properly", because internal OPAMP block makes node voltage(IFEF pin, VREF pin) equal. have check COMP node desired voltage desired voltage measured, check output appling desired voltage COMP instead compensation capacitor directly. internal reference voltage(BGR's output voltage) instead external Vbias setting BGRSW low, check BGR's output checking VREF voltage.
0.35µm 10-BIT 80MSPS DUAL
BW1221L_2CLK
CORE LAYOUT GUIDE
Layout core replacement recommended that thick analog power metal(larger than 40um width). When connecting PAD, path should kept short possible, branch metal connect center analog switch block. recommended that thick analog output metal(at least more than 50um) when connecting PAD, also path length should kept short possible. metal width less than 50um, should double triple PADs. Digital power analog power separately used. When connected other blocks, must double shielded using N-well active remove substrate coupling noise. that case, power metal should connected directly. Bulk power used reduce influence substrate noise. must more than pins VDDA because requires much current dissipation.
BW1221L_2CLK
0.35µm 10-BIT 80MSPS DUAL
FEEDBACK REQUEST
appreciate your interest products. have further questions, please specify attached form. Thank very much. ELECTRICAL CHARACTERISTIC Characteristics Supply Voltage Power dissipation Resolution Analog Output Voltage Operating Temperature Output Load Capacitor Output Load Resistor Integral Non-Linearity Error Differential Non-Linearity Error Maximum Conversion Rate Unit Bits Remarks
VOLTAGE OUTPUT Reference Voltage BOTTOM Analog Output Voltage Range Digital Input Format Binary Code Complement Code
CURRENT OUTPUT Analog Output Maximum Current Analog Output Maximum Signal Frequency Reference Voltage External Resistor Current Setting (RSET) Pipeline Delay want Power down mode? want Interal Reference Voltage(BGR)? Which want Serial Input TYPE parallel Input TYPE? need 3.3v power supply your system? many channels need(BW1221L_2CLK dual channel DAC)?

BW1221L_2CLK BW1221L_2CLK CMOS Dual 10Bit converter general video

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