BW1218L BW1218L CMOS 10-bit analog-to-digital converter (ADC). co

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BW1218L BW1218L CMOS 10-bit analog-to-digital converter (ADC). co

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0.35µm 10-BIT 5-10MSPS
BW1218L
BW1218L CMOS 10-bit analog-to-digital converter (ADC). converts analog input signal into 10bit binary digital codes maximum sampling rate 10MHz. device monolithic with on-chip, high-performance, sample-and-hold Amplifier (SHA) current reference. structure allows single-ended input simple interface.
TYPICAL APPLICATIONS
Engine Multi-Media (CDP) Power Application
FEATURES
Resolution: 10-bit Maximum Conversion Rate: 10MHz Package Type: 48TSSOP Power Supply: 3.3V Power Consumption: 40mW (typical) Reference Voltage: 3.2V (single reference) Input Range: 3.0V (3.0VP-P) Differential Linearity Error: ±0.7 Integral Linearity Error: ±1.1 Signal Noise Distortion Ratio 54dB Digital Output: CMOS Level Operating Temperature Range
BW1218L
0.35µm 10-BIT 5-10MSPS
FUNCTIONAL BLOCK DIAGRAM
Analog Input
MDAC
MDAC
Reference Input
Flash
Flash
Flash
GEN.
Main Bias Clock
Clock GEN.
Digital Logic
Digital Output
0.35µm 10-BIT 5-10MSPS
BW1218L
CORE DESCRIPTION
Name VREF AGND VDDA VBBA VSSA AINT SPEEDUP STBY CKIN DO[9:0] STCB VBBD VSSD VDDD Type Abbr. Analog Input Digital Input Analog Output Analog Output Analog Power Analog Ground Digital Power Digital Ground Analog Bidirection Digital Bidirection Type pia_bb pia_bb vdda vbba vssa piar50_bb picc_bb picc_bb picc_bb pot4_bb pot4_bb picc_bb vbba vssd vddd Description Reference Voltage (3.2V) Analog Ground Reference Analog Power (3.3V) Analog Bias Analog Ground Analog Input (Input Range: 0.0V 3.0V) VDD=Speed GND=Normal VDD=power saving (standby), GND=normal Sampling Clock Input Digital Output Conversion Signal Start Conversion Signal Digital Bias Digital Digital Power (3.3V)
BW1218L
0.35µm 10-BIT 5-10MSPS
CODE CONFIGURATION
VDDD
VDDA
VSSD
VBBD
VSSA
VBBA
AINC
STCB
BW1218L
VREF AGND
[MSB:LSB] DO[9:0]
SPEEDUP
STBY
CKIN
0.35µm 10-BIT 5-10MSPS
BW1218L
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Analog Input Voltage Digital Input Voltage Reference Voltage Storage Temperature Range Operating Temperature Range Symbol CKIN VREF/AGND Tstg Topr Value Unit
NOTES ABSOLUTE MAXIMUM RATING specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect unless otherwise specified. 100pF capacitor discharged through 1.5k resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Symbol VDDD VDDA VDDR VREF AINT Toper 3.15 3.45 Unit
Reference Input Voltage Analog Input Voltage Operating Temperature
NOTE: strongly recommended that supply pins (VDDA, VDDD, VDDR) powered from same source avoid power latch-up.
BW1218L
0.35µm 10-BIT 5-10MSPS
ELECTRICAL CHARACTERISTICS
Characteristics Differential Nonlinearity Integral Nonlinearity Offset Voltage Symbol Unit Test Condition VREF 3.2V AINT 3.0V VREF 3.2V AINT 3.0V VREF 3.2V
NOTE: Converter Specifications: VDDA=VDDD=VDDR=3.3V, VSSA=VSSD=VSSR=0V, Toper=25 REFTOP=2V, REFBOT=1V unless otherwise specified
ELECTRICAL CHARACTERISTICS
Characteristics Maximum Conversion Rate Dynamic Supply Current Signal-to-Noise Distortion Ratio Symbol IVDD SNDR Unit Test Condition 500kHz AINT 3.0V 5MHz (without system load) 500kHz AINT 3.0V
NOTE: Converter Specifications: VDDA=VDDD=VDDR=3.3V, VSSA=VSSD=VSSR=0V, Toper=25 REFTOP=2V, REFBOT=1V unless otherwise specified
0.35µm 10-BIT 5-10MSPS
BW1218L
CHART
Index 1021 1022 1023 AINT Input 0.00000 0.00293 0.00293 0.00586 0.00586 0.00879 1.49707 1.50000 1.50000 1.50293 1.50293 1.50586 2.99121 2.99414 2.99414 2.99707 2.99707 3.00000 Digital Output 0000000000 0000000001 0000000010 0111111111 1000000000 1000000001 1111111101 1111111110 1111111111 1LSB=2.93mV VREF=3.2V
BW1218L
0.35µm 10-BIT 5-10MSPS
TIMING DIAGRAM
Main Waveform
AINT Input Sampling Period CKIN
STCB
DO[9:0]
STCB CKIN Condition
10ns TSAFE
CKIN
STCB
Converter operates data conversion when STCB(Start Conversion Bar) signal just "HIGH". Otherwise, output data (DO[9:0]) keep current states. STCB signal should changed during "TSAFE" with "HIGH" level clock operation shown main waveform.
Pipeline Delay
STCB
Pipeline Delay
After STCB "HIGH", Converter requires pipeline delay clock period generate signal data outputs.
0.35µm 10-BIT 5-10MSPS
BW1218L
CORE EVALUATION GUIDE
function evaluated external check bidirectional pads connected input nodes HOST back-end circuit. reference voltages biased internally through resistor divider.
VDDD
VDDA
VSSD
VBBD
VSSA
VBBA
AINT DO[9:0] CKIN DO[9:0] HOST CORE
BW1218L
VREF AGND SPEEDUP STBY
DO[9:0]
Digital
DO[9:0] Bidrectional
(ADC Function Test Externally Forced Digital Input)
STCB
BW1218L
0.35µm 10-BIT 5-10MSPS
PACKAGE CONFIGURATION
Digital
0.1u 0.1u 0.1u
VREF AGND VDDA VDDA VBBA VSSA VSSA AINT SPEEDUP ITEST STBY VDDR VSSR CKIN TEST1 TSET2
VDDD VDDD VSSD VSSD VBBD STCB 0.1u
0.1u
BW1218L
DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] TRIST
0.1u
Analog Digital
0.1u
NOTE: denotes Connection".
0.35µm 10-BIT 5-10MSPS
BW1218L
PACKAGE DESCRIPTION
Number Name VREF AGND VDDA VBBA VSSA AINT SPEEDUP ITEST STBY VDDR VSSR CKIN TEST1 TEST2 TRIST Type Description Reference Voltage (3.2V) Analog Ground Reference Internal Bias Point Analog Power (3.3V) Analog Bias Analog Ground Analog Input (0.0V~3.0V) VDD=Speed GND=Normal open=use internal bias circuit VDD=Power saving (Standby), GND=Normal Power (3.3V) Ground Sampling Clock Input Monitoring (TEST) Cell Pin1, GND=Normal Monitoring (TEST) Cell Pin2, GND=Normal Tristate Buffer Input VDD=High Impedance, GND=Normal Digital Output (LSB) Digital Output Digital Output (MSB) Conversion Signal Start Conversion Signal Digital Bias Digital Digital Power (3.3V)
28~5
DO[0] DO[1:8] DO[9] STCB VBBD VSSD VDDD
NOTE: TYPE denote Power Ground respectively.
BW1218L
0.35µm 10-BIT 5-10MSPS
PACKAGE DESCRIPTION (Continued)
Configuration
VREF AGND VDDA VDDA VBBA VSSA VSSA AINT SPEEDUP ITEST STBY VDDR VSSR CKIN TEST1 TSET2
VDDD VDDD VSSD VSSD VBBD STCB DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] TRIST
BW1218L
0.35µm 10-BIT 5-10MSPS
BW1218L
USER GUIDE
Input Range BW1218L only single-ended input, input range 0.0V 3.0V (3.0VP-P). Speed initial target speed BW1009L 10MHz. want more speed (about 10MHz), should connect SPEEDUP port 'HIGH'. Power Consumption Optimization optimize power consumption, control ITEST voltage level precisely
AINT VSSA VBBA SPEEDUP VDDA STBY DOUT[0] DOUT[1] DOUT[2] DOUT[3] DOUT[4] DOUT[5] DOUT[6] DOUT[7] DOUT[8] DOUT[9] CKIN VBBD STCB VSSD VDDD AGND VREF VDDD VSSD VBBD
BW1218L
PHANTOM CELL INFORMATION
BW1218L
0.35µm 10-BIT 5-10MSPS
0.35µm 10-BIT 5-10MSPS
BW1218L
PHANTOM CELL INFORMATION (Continued)
Name VDDA VSSA VBBA VDDD VSSD VBBD AINT VREF, AGND SPEEDUP CKIN STBY STCB ADO[9] ADO[8] ADO[7] ADO[6] ADO[5] ADO[4] ADO[3] ADO[2] ADO[1] ADO[0] Usage External External External External External External External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal External/Internal Separated from analog clean signals possible. overlap with digital lines. Maintain shortest path pads. Maintain larger width shorter length pads. Separate from other digital lines. Separate from other analog signals from other blocks. good power ground source board. Layout Guide merge analog powers with another power
BW1218L
0.35µm 10-BIT 5-10MSPS
FEEDBACK REQUEST
Specification Parameter Supply voltage Reference Input voltage Analog Input voltage Operating temperature Integral non-linearity error Differential non-linearity error Offset voltage error (Bottom) Offset voltage error (Top) Maximum conversion rate Dynamic supply current Power dissipation Signal-to-noise ratio Digital output format (Provide detailed description timing diagram) What want choose power supply voltages? example, analog needs digital 3.3V/5V. What resolution need ADC? about conversion speed (data data out)? many cycles exist during latency (pipelined delay)? What's input range? then what need between single input differential input? interface compatible with TTL? Could explain external/internal configurations required? Unit MSPS Remarks
Specially requested function list
0.35µm 10-BIT 5-10MSPS
BW1218L
HISTORY CARD
Version 2000.11 02.04.29 Release formal datasheet information phantom cell information Date Modified Items Original version published (preliminary) Comments
BW1218L
0.35µm 10-BIT 5-10MSPS
NOTES

BW1218L BW1218L CMOS 10-bit analog-to-digital converter (ADC). co

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