128M GDDR SDRAM 128Mbit GDDR SDRAM 16Bit Banks Graphic Doubl
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K4D261638F
128M GDDR SDRAM
128Mbit GDDR SDRAM
16Bit Banks Graphic Double Data Rate Synchronous DRAM
Revision January 2004
Samsung Electronics reserves right change products specification without notice.
Rev. (Jan. 2004)
K4D261638F
Revision History
Revision (January 2004)
Changed tWR_A K4D261638F-TC25/2A/33/36 from 3tCK 4tCK Changed K4D261638F-TC25 from 17tCK 18tCK Changed K4D261638F-TC2A/33/36 from 15tCK 16tCK Changed tRAS K4D261638F-TC25 from 12tCK 13tCK. Changed tRAS K4D261638F-TC2A/33/36 from 10tCK 11tCK. Changed tDAL K4D261638F-TC25/2A/33/36 from 8tCK 9tCK
128M GDDR SDRAM
Revision (January 2004)
Added K4D261638F-TC25 spec.
Revision (December 2003) Revision (October 2003) Preliminary Spec
Defined spec
Revision (October 2003) Target Spec
Added Lead free package part number datasheet
Revision (August 2003) Target Spec
Defined Target Specification
Rev. (Jan. 2004)
K4D261638F
128M GDDR SDRAM
16Bit Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe FEATURES
2.5V power supply device operation 2.5V power supply interface SSTL_2 compatible inputs/outputs banks operation cycle with address programs Read latency 5(clock) Burst length Burst type (sequential interleave) inputs except data sampled positive going edge system clock Differential clock input Wrtie-Interrupted Read Function DQS's 1DQS Byte Data transactions both edges Data strobe aligns transitions with Clock transition Edge aligned data data strobe output Center aligned data data strobe input write masking only Auto Self refresh 32ms refresh period cycle) 66pin TSOP-II Maximum clock frequency 400MHz Maximum data rate 800Mbps/pin
ORDERING INFORMATION
Part K4D261638F-TC25 K4D261638F-TC2A K4D261638F-TC33 K4D261638F-TC36 K4D261638F-TC40 K4D261638F-TC50 Freq. 400MHz 350MHz 300MHz 275MHz 250MHz 200MHz Data Rate 800Mbps/pin 700Mbps/pin 600Mbps/pin 550Mbps/pin 500Mbps/pin 400Mbps/pin SSTL_2 66pin TSOP-II Interface Package
K4D261638F-LC Lead Free package part number. K4D261638F-TC25/2A, VDDQ 2.8V+0.1V
GENERAL DESCRIPTION
16Bit Bank SDRAM
K4D261638F 134,217,728 bits hyper synchronous data rate Dynamic organized 2,097,152 words bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance 1.6GB/s/chip. transactions possible both edges clock cycle. Range operating frequencies, programmable burst length programmable latencies allow device useful variety high performance memory system applications.
Rev. (Jan. 2004)
K4D261638F
CONFIGURATION (Top View)
VDDQ VSSQ VDDQ VSSQ VDDQ LDQS AP/A10 DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ VSSQ UDQS VREF
128M GDDR SDRAM
TSOP(II) (400mil 875mil) (0.65 Pitch)
DESCRIPTION
CK,CK L(U)DQS L(U)DM Differential Clock Input Clock Enable Chip Select Address Strobe Column Address Strobe Write Enable Data Strobe Data Mask Reserved Future BA0, ~A11 DQ15 VDDQ VSSQ Bank Select Address Address Input Data Input/Output Power Ground Power DQ's Ground DQ's Connection
Rev. (Jan. 2004)
K4D261638F
INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol CK*1 Input Type
128M GDDR SDRAM
Function differential system clock Input. inputs sampled rising edge clock except DQ's DM's that sampled both edges DQS. Activates signal when high deactivates signal when low. deactivating clock, indicates Power down mode Self refresh mode. enables command decoder when disabled command decoder when high. When command decoder disabled, commands ignored previous operations continue. Latches addresses positive going edge with low. Enables access precharge. Latches column addresses positive going edge with low. Enables column access. Enables write operation precharge. Latches data starting from CAS, active. Data input output synchronized with both edge DQS. x16, LDQS corresponds data DQ0-DQ7 UDQS corresponds data DQ8-DQ15. Data Mask. Data masked Latency=0 when high burst write. x16, corresponds data DQ0-DQ7 correspons data DQ8-DQ15. Data inputs/Outputs multiplexed same pins. Selects which bank active. Row/Column addresses multiplexed same pins. addresses RA11, Column addresses CA8. Power ground input buffers core logic. Isolated power supply ground output buffers provide improved noise immunity. Reference voltage inputs, used SSTL interface. This recommended left connection" device
Input
Input
Input Input Input
LDQS,UDQS
Input/Output
LDM,UDM DQ15 BA0, VDD/VSS VDDQ/VSSQ VREF NC/RFU
Input Input/Output Input Input Power Supply Power Supply Power Supply connection/ Reserved future
timing reference point differential clocking cross point applications using single ended clocking, apply VREF pin.
Rev. (Jan. 2004)
K4D261638F
BLOCK DIAGRAM (2Mbit 16I/O Bank)
128M GDDR SDRAM
Intput Buffer Control LDMi
Bank Select
Data Input Register Serial parallel
2Mx16 Output Buffer 2-bit prefetch Sense Refresh Counter Buffer Decoder 2Mx16 2Mx16 2Mx16
Address Register
CK,CK ADDR
Column Decoder LCBR LRAS Col. Buffer
Latency Burst Length Strobe Gen. Data Strobe
Programming Register LCKE LRAS LCBR LCAS LWCBR
CK,CK
LDMi
Timing Register
CK,CK
Rev. (Jan. 2004)
K4D261638F
FUNCTIONAL DESCRIPTION
Power-Up Sequence
128M GDDR SDRAM
SDRAMs must powered initialized predefined manner prevent undefined operations. Apply power keep state (All other inputs undefined) Apply before VDDQ Apply VDDQ before VREF Start clock maintain stable condition minimum 200us. minimum 200us after stable power clock(CK,CK apply take high Issue precharge command banks device. Issue EMRS command enable Issue command reset DLL. additional clock cycles required lock DLL. *1,2 Issue precharge command banks device. Issue least more auto-refresh commands. Issue mode register command with initialize mode register. additional 200cycles clock input required lock after enabling DLL. Sequence regardless order.
Power Initialization Sequence
CK,CK
Command
precharge Banks
EMRS
Reset
precharge Banks
Auto Refresh
Auto Refresh
Clock min.
Clock min.
tRFC
tRFC
Clock min.
Mode
Register
Command
Inputs must stable 200us
When operating frequency changed, reset should required again. After reset again, minimum cycles clock input needed lock DLL.
Clock min.
Rev. (Jan. 2004)
K4D261638F
MODE REGISTER SET(MRS)
128M GDDR SDRAM
mode register stores data controlling various operating modes SDRAM. programs latency, addressing mode, burst length, test mode, reset various vendor specific options make SDRAM useful variety different applications. default value mode register defined, therefore mode register must written after EMRS setting proper operation. mode register written asserting RAS, WE(The SDRAM should active mode with already high prior writing into mode register). state address pins BA0, same cycle RAS, going written mode register. Minimum clock cycles requested complete write operation mode register. mode register contents changed using same command clock cycle requirements during operation long banks idle state. mode register divided into various fields depending functionality. burst length uses addressing mode uses latency(read latency from column address) uses used test mode. used reset. A7,A8, must normal operation. Refer table specific codes various burst length, addressing modes latencies. Address
Latency
Burst Length
Mode Register
Reset
Test Mode mode Normal Test
Burst Type Type Sequential Interleave Burst Length
Latency EMRS RFU(Reserved future use) should stay during cycle. Cycle
Command
Precharge Banks
Latency Reserved Reserved Reserved Reserved Reserved
Burst Type Sequential Reserve Reserve Reserve Reserve Reserve Interleave Reserve Reserve Reserve Reserve Reserve
Command
tMRD=2
issued only banks precharge state. Minimum required issue command.
Rev. (Jan. 2004)
K4D261638F
EXTENDED MODE REGISTER SET(EMRS)
128M GDDR SDRAM
extended mode register stores data enabling disabling selecting output driver strength. default value extended mode register defined, therefore extened mode register must written after power enabling disabling DLL. extended mode register written asserting RAS, CAS, high BA0(The SDRAM should bank precharge with already high prior writing into extended mode register). state address pins same cycle RAS, going written extended mode register. used setting driver strength normal, weak matched impedance. clock cycles required complete write operation extended mode register. mode register contents changed using same command clock cycle requirements during operation long banks idle state. used enable disable. "High" used EMRS. other address pins except A0,A1,A6 must proper EMRS operation. Refer table specific codes.
Address Extended Mode Register
D.I.C
D.I.C
EMRS
Output Driver Impedence Control Weak Matched
Enable Enable Disable
RFU(Reserved future use) should stay during EMRS cycle.
Rev. (Jan. 2004)
K4D261638F
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Voltage supply relative Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDDQ TSTG
128M GDDR SDRAM
Value -0.5 -1.0 -0.5 +150
Unit
Note Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
POWER OPERATING CONDITIONS(SSTL_2 In/Out)
Recommended operating conditions(Voltage referenced VSS=0V, TA=0 65°C)
Parameter
Device Supply voltage Output Supply voltage Reference voltage Termination voltage Input logic high voltage Input logic voltage Output logic high voltage Output logic voltage Input leakage current Output leakage current
Symbol
VDDQ VREF VIH(DC) VIL(DC)
2.375 2.375 0.49*VDDQ VREF-0.04 VREF+0.15 -0.30 Vtt+0.76
2.50 2.50 VREF
2.625 2.625 0.51*VDDQ VREF+0.04 VDDQ+0.30 VREF-0.15 Vtt-0.76
Unit
Note
IOH=-15.2mA IOL=+15.2mA
Note Under conditions VDDQ must less than equal VDD. VREF expected equal 0.50*VDDQ transmitting device track variations level same. Peak peak noise VREF exceed value. Thus, from 0.50*VDDQ, VREF allowed 25mV error additional 25mV noise. transmitting device must track VREF receiving device. VIH(max.)= VDDQ +1.5V pulse width greater than cycle rate. VIL(mim.)= -1.5V pulse width greater than cycle rate. under test input acceptable. other pins that under test VIN=0V. K4D261638F-TC25/2A, VDDQ 2.8V+0.1V
Rev. (Jan. 2004)
K4D261638F
Recommended operating conditions Unless Otherwise Noted, TA=0 65°C)
128M GDDR SDRAM
CHARACTERISTICS
Version Parameter Operating Current (One Bank Active) Precharge Standby Current Power-down mode Precharge Standby Current Power-down mode Active Standby Current power-down mode Active Standby Current Power-down mode Operating Current Burst Mode) Refresh Current Self Refresh Current Symbol Test Condition ICC1 ICC2P ICC2N ICC3P ICC3N ICC4 ICC5 ICC6 Burst Lenth=2 tRC(min) IOL=0mA, tCC= tCC(min) VIL(max), tCC= tCC(min) VIH(min), VIH(min), tCC= tCC(min) VIL(max), tCC= tCC(min) VIH(min), VIH(min), tCC= tCC(min) Unit Note
tRFC(min)tRC tRFC(min) Page Burst, Banks activated. tRFC(min)
0.2V
Note Measured with outputs open. Refresh period 32ms.
INPUT OPERATING CONDITIONS
Recommended operating conditions(Voltage referenced VSS=0V, VDD=2.5V+ VDDQ=2.5V+ 5%,TA=0 65°C)
Parameter
Input High (Logic Voltage; Input (Logic Voltage; Clock Input Differential Voltage; Clock Input Crossing Point Voltage;
Symbol
VREF+0.35 0.5*VDDQ-0.2
VREF-0.35 VDDQ+0.6 0.5*VDDQ+0.2
Unit
Note
Note magnitude difference between input level input level value expected equal 0.5*VDDQ transmitting device must track variations level same K4D261638F-TC25/2A, VDDQ 2.8V+0.1V.
Rev. (Jan. 2004)
K4D261638F
OPERATING TEST CONDITIONS (VDD=2.5V±5%, 65°C)
Parameter Input reference voltage CK(for single ended) signal maximum peak swing signal minimum slew rate Input Levels(VIH/VIL) Input timing measurement reference level Output timing measurement reference level Output load condition
1.For K4D261638F-TC25/2A, VDDQ 2.8V+0.1V.
128M GDDR SDRAM
Value 0.50*VDDQ VREF+0.35/VREF-0.35 VREF Fig.1
Unit V/ns
Note
Vtt=0.5*VDDQ
RT=50 Output Z0=50
VREF =0.5*VDDQ
CLOAD=30pF
(Fig. Output Load Circuit
CAPACITANCE (VDD=2.5V, 25°C, f=1MHz)
Parameter
Input capacitance( Input capacitance(A0~A11, BA0~BA1) Input capacitance CKE, RAS,CAS, Data input/output capacitance(DQ0~DQ15) Input capacitance(DM0 DM3)
Symbol
CIN1 CIN2 CIN3 COUT CIN4
Unit
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added power line board. Parameter Decoupling Capacitance between Decoupling Capacitance between VDDQ VSSQ Symbol CDC1 CDC2 Value 0.01 0.01 Unit
Note VDDQ pins separated each other. pins connected chip. VDDQ pins connected chip. VSSQ pins separated each other pins connected chip. VSSQ pins connected chip.
Rev. (Jan. 2004)
K4D261638F
CHARACTERISTICS
Parameter
cycle time high level width level width access time from Output access time from Data strobe edge Dout edge Read preamble Read postamble valid DQS-in DQS-In setup time DQS-in hold time write postamble DQS-In high level width DQS-In level width Address Control input setup Address Control input hold setup time hold time Clock half period Data output hold time from CL=3 CL=4 CL=5
128M GDDR SDRAM
Symbol
0.45 0.45 -0.55 -0.55 0.85 0.35 0.45 0.45 0.35 0.35 tCLmin tCHmin tHP-0.4
0.55 0.55 0.55 0.55 0.35 1.15 0.55 0.55
0.55 0.55 0.35 1.15
2.86 0.45 0.45 -0.6 -0.6 0.85 0.35 0.35 0.35 tCLmin tCHmin tHP-0.35
0.45 0.45 -0.6 -0.6 0.85 0.35 0.35 0.35 tCLmin tCHmin tHP-0.35
0.55 0.55 0.35 1.15
Unit
Note
tDQSCK tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL
Note JEDEC specification currently defines output data valid window(tDV) time period when data strobe data associated with that data strobe coincidentally valid. previously used definition tDV(=0.35tCK) artificially penalizes system timing budgets assuming worst case output vaild window even then clock duty cycle applied device better than 45/55% timing term, which stands data output hold time from difined account clock duty cycle variation replaces tQHmin tHP-X where tHP=Minimum half clock period given cycle defined clock high clock time(tCH,tCL) frequency dependent timing allowance account tDQSQmax
Rev. (Jan. 2004)
K4D261638F
CHARACTERISTICS
Parameter
cycle time high level width level width access time from Output access time from Data strobe edge Dout edge Read preamble Read postamble valid DQS-in DQS-In setup time DQS-in hold time write postamble DQS-In high level width DQS-In level width Address Control input setup Address Control input hold setup time hold time Clock half period Data output hold time from CL=3 CL=4 CL=5
128M GDDR SDRAM
Symbol
0.45 0.45 -0.6 -0.6 0.85 0.35 0.40 0.40 tCLmin tCHmin tHP-0.4
0.55 0.55 0.40 1.15
0.55 0.55 1.15
0.45 0.45 -0.6 -0.6 0.85 0.35 tCLmin tCHmin tHP-0.4
0.45 0.45 -0.7 -0.7 0.45 0.45 tCLmin tCHmin tHP-0.45
0.55 0.55 0.45
Unit
Note
tDQSCK tDQSQ tRPRE tRPST tDQSS tWPRES tWPREH tWPST tDQSH tDQSL
Note JEDEC specification currently defines output data valid window(tDV) time period when data strobe data associated with that data strobe coincidentally valid. previously used definition tDV(=0.35tCK) artificially penalizes system timing budgets assuming worst case output vaild window even then clock duty cycle applied device better than 45/55% timing term, which stands data output hold time from difined account clock duty cycle variation replaces tQHmin tHP-X where tHP=Minimum half clock period given cycle defined clock high clock time(tCH,tCL) frequency dependent timing allowance account tDQSQmax
Rev. (Jan. 2004)
K4D261638F
CHARACTERISTICS
Parameter
cycle time Refresh cycle time active time delay Read delay Write precharge time active active Last data precharge @Normal Precharge Last data precharge @Auto Precharge Last data Read command Col. address Col. address Mode register cycle time Auto precharge write recovery Precharge Exit self refresh read command Power down exit time Refresh interval time
128M GDDR SDRAM
3tCK +tIS
Symbol
tRFC tRAS tRCDRD tRCDWR tRRD tWR_A tCDLR tCCD tMRD tDAL tXSR tPDEX tREF
100K
100K
3tCK +tIS
3tCK +tIS
100K
Unit
Note
Note normal write operation, even numbers written inside DRAM
CHARACTERISTICS
K4D261638F-TC25 Frequency Latency 400MHz (2.5ns) 350MHz 2.86ns 300MHz 3.3ns 275MHz 3.6ns 250MHz 4.0ns 200MHz 5.0ns tRFC tRAS tRCDRD tRCDWR tRRD
(Unit Number Clock)
tDAL
Unit
K4D261638F-TC2A Frequency Latency 350MHz 2.86ns 300MHz 3.3ns 275MHz 3.6ns 250MHz 4.0ns 200MHz 5.0ns
tRFC
tRAS
tRCDRD tRCDWR
tRRD
tDAL
Unit
K4D261638F-TC33 Frequency Latency 300MHz 3.3ns 275MHz 3.6ns 250MHz 4.0ns 200MHz 5.0ns
tRFC
tRAS
tRCDRD tRCDWR
tRRD
tDAL
Unit
Rev. (Jan. 2004)
K4D261638F
CHARACTERISTICS
Parameter
cycle time Refresh cycle time active time delay Read delay Write precharge time active active Last data precharge @Normal Precharge Last data precharge @Auto Precharge Last data Read command Col. address Col. address Mode register cycle time Auto precharge write recovery Precharge Exit self refresh read command Power down exit time Refresh interval time
128M GDDR SDRAM
3tCK +tIS
Symbol
tRFC tRAS tRCDRD tRCDWR tRRD tWR_A tCDLR tCCD tMRD tDAL tXSR tPDEX tREF
100K
100K
3tCK +tIS
3tCK +tIS
100K
Unit
Note
Note normal write operation, even numbers written inside DRAM
CHARACTERISTICS
K4D261638F-TC36 Frequency Latency 275MHz 3.6ns 250MHz 4.0ns 200MHz 5.0ns tRFC tRAS tRCDRD tRCDWR tRRD
(Unit Number Clock)
tDAL
Unit
K4D261638F-TC40 Frequency Latency 250MHz 4.0ns 200MHz 5.0ns
tRFC
tRAS
tRCDRD tRCDWR
tRRD
tDAL
Unit
K4D261638F-TC50 Frequency Latency 200MHz 5.0ns
tRFC
tRAS
tRCDRD tRCDWR
tRRD
tDAL
Unit
Rev. (Jan. 2004)
K4D261638F
Simplified Timing BL=4
128M GDDR SDRAM
BA[1:0]
A8/AP
ADDR (A0~A7 ,A9~A11)
ACT_A
WR_A
PRECH
ACT_A
WR_A
ACT_B
WR_B
tRCD tRAS
tRRD
Normal Write Burst BL=4)
Multi Bank Interleaving Write Burst BL=4)
Rev. (Jan. 2004)
K4D261638F
PACKAGE DIMENSIONS (66pin TSOP-II)
128M GDDR SDRAM
Units Millimeters
(0.80) (0.50) 0.125 +0.075 -0.035 (0.50)
10.16±0.10
(1.50)
(1.50)
0.665±0.05
0.210±0.05
(0.80)
0.05
(0.71)
0.65TYP 0.65±0.08
0.30±0.08
0.10 0.075
NOTE REFERENCE ASS'Y QUALITY
Rev. (Jan. 2004)
0.25TYP
1.20MAX
22.22±0.10
1.00±0.10
0.45~0.75
11.76±0.20
(10.76)
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