BW0407X Samsung's BW0407X high resolution, single-chip stereo tha

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BW0407X Samsung's BW0407X high resolution, single-chip stereo tha

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0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
Samsung's BW0407X high resolution, single-chip stereo that employs Sigma-Delta modulation technique. With resolution 16bit, oversampling 90dB Signal-to-Noise ratio, BW0407X suitable applications consumer digital audio system, multimedia digital systems.
FEATURES
chip stereo A/D, converter 4-th order Sigma-Delta modulator Sigma-Delta Stereo ADC. Oversampling On-chip Decimation Filter On-chip Anti-Aliasing Filter 90dB Signal Noise Ratio. Sigma-Delta Stereo DAC. Oversampling On-chip Interpolation Filter On-chip Analog Postfilter 90dB Signal Noise Ratio Mute Analog Output Zero detection mute Analog Single-ended Input Output. Sampling Rate 48KHz Single +3.3V Power Supply
TYPICAL APPLICATIONS
multi-media applications consumer digital audio digital systems
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
FUNCTIONAL BLOCK DIAGRAM
single differential AINL
AURST
sigma-delta modulator (analog)
single differential
PWDN<1:0>
decimation filter sigma-delta modulator (analog) parallel interface SC-postfilter sigma-delta modulator (digital) Sinc filter
AUSDOUT
AINR
AUSCLK AULRCK FORMAT
differential single AOUTL
differential single AOUTR
interpolation filter
AUSDIN
SC-postfilter
MUTE
VREF
voltage reference
clock generator, bist
AUSYSCK
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
CORE DESCRIPTION
Name AINL AINR AOUTL AOUTR VREF REFIN REFH1L REFH1R REFH2L REFH2R REFL1L REFL1R REFL2L REFL2R AUSYSCK AUSCLK AULRCK AUSDIN FORMAT AURST MUTE PWDN<1> PWDN<0> AUSDOUT VDDA VSSA VDDD VSSD Type Digital Pins piccbb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb pot2bb_bb vdd3t_bb vsst_bb vdd3t_bb vsst_bb Master clock(256*Fs) Serial interface clock(32*Fs) Sampling Frequency clock(Fs) Digital serial input Serial interface format select Digital reset Analog output mute on/off ("H" mute enable) Power down control Power down control Digital serial output Power Pins Analog supply Analog ground Digital supply Digital ground Each Must AVSS respectively Analog Pins pia_bb_50option pia_bb_50option poa_bb_50option poa_bb_50option poar10_bb Analog Left Input Analog Right Input Analog Left output Analog Right output Voltage reference output bypass filtering Each Must VREF respectively Description
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
CORE DESCRIPTION (Continued)
Name Type Description
Core Interanl Block Test Pins These pins only used core internal block evaluation. don't these pins. must digital input pins DVSS disable state, output bidrections pins leave floating. TMODE DIAG ERRORB AUSDECI<1> AUSDECI<0> GAINSEL ANCK64 ANCKSE AUTDECIL AUTDECIR AUSPDATA AUADPDML AUADPDMR IREF piccbb_bb pot2bb_bb pot2bb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb piccbb_bb pot2bb_bb pot2bb_bb piar50bb_bb Test mode selection digital filter (normal "L") BIST output(sram) BIST output(sram) Test internal block loop path selection (normal "L") Test internal block loop path selection (normal "L") Test input decimation filter (normal "L") Test clock analog block loop test (normal "L") Test analog clock selection (normal "L") Test input decimation post left channel filter (normal Test input decimation post right channel filter (normal Test input ADC,DAC loop back test (normal "L") Test analog modulator left output monitoring. Test analog modulator right output monitoring. Test analog reference current control
Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
CORE CONFIGURTION
AUSYSCK AUSCLK AULRCK AUSDIN FORMAT AURST MUTE GAINSEL ANCK64 ANCKSE AUTDECIL AUTDECIR AUSPDATA TMODE AUSDECI<1> AUSDECI<0> PWDN<1> PWDN<0> AINL AINR REFIN REFH1L REFL1L REFH1R REFL1R
AUADPDML AUADPDMR DIAG ERRORB AUSDOUT AOUTL AOUTR VREF IREF
bw0407x
REFH2L REFL2L REFH2R REFL2R
Power Used VDDA VSSA VDDD VSSD
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
CORE EVALUATION GUIDE
3.3V
3.3V
AVDD AVSS AUSYSCK AUSCLK AULRCK AUSDIN FORMAT AURST MUTE GAINSEL
DVDD DVSS
AUADPDML AUADPDMR DIAG ERRORB AUSDOUT
host
ANCK64 ANCKSE AUTDECIL AUTDECIR AUSPDATA TMODE AUSDECI<1> AUSDECI<0> PWDN<1> PWDN<0>
AOUTL
External
100k
AOUTR
100k
0.33uF
VREF AINL AINR
bw0407x
IREF
External
External
0.33uF
REFIN REFH1L REFL1L REFH1R REFL1R Power Used AVDD AVSS DVDD DVSS REFH2L REFL2L REFH2R REFL2R
AVSS
AVSS
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
Location
Description 10uF TANTALUM CAPACITOR 0.1uF CERAMIC CAPACITOR
NOTE: Analog Power/Ground must seperated Digital Power/Ground. possible channel input/output line must symmetrical routing test board.
ABSOLUTE MAXIMUM RATINGS
Charateritics Supply Vtg. Digital Input Voltage range Storage Temp. Min. -0.3 -0.3 Typ. Max. Units
RECOMMANDED OPERATING CONDTIONS
Charateritics Supply Vtg. Operating Temp. Min. 3.135 Typ. Max. 3.465 Units
DIGITAL FILTER CHARACTERISTICS
Characteristics Sampling Frequency Passband Stopband Transition band Passband ripple Stopband attenuation Group delay distortion Passband Stopband Transition band Passband ripple Stopband attenuation Group delay distortion 0.4Fs 0.6Fs 0.4Fs~0.6Fs ±0.1 0.4Fs 0.6Fs 0.4Fs~0.6Fs ±0.1 Min. Typ. Max. Units
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
ELECTRICAL CHARACTERISTICS
(Measurement Bandwidth 20Hz 20KHz, Full scale input sine wave 1KHz, Fs=48KHz, AVDD=3.3V, DVDD=3.3V, 10k/25pF load, Ta=25°C, Unless otherwise specified) Characteristics Resolution Sampling rate Reference Voltage Output Characteristics (EIAJ) S/(N+D) Dynamic Range Interchannel Isolation Offset Error Maximum Input Voltage Range Input Impedance Characteristics (EIAJ) S/(N+D) Dynamic Range Interchannel Isolation Offset Error Maximum Output Voltage Range Power Supply Supply Current Power Dissipation Power Supply Rejection Ratio 1.55 Min. Typ. Max. Units Bits
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
TIMING CHARACTERISTICS
Characteristics AUSYSCK Frequency AUSCLK Frequency AULRCK Frequency AUSYSCK Duty cycle (H:L) AUSCLK Duty cycle (H:L) AULRCK Duty cycle (H:L) AUSYSCK Falling AUSCLK Edge Delay(Hold) AUSYSCK Falling AULRCK Edge Delay(Hold) AUSCLK Falling AUSDOUT Delay AUSCLK Rising AUSDIN Setup AUSCLK Rising AUSDIN Hold Symbol Fsysck Fsclk Flrck SYDuty SCDuty LRDuty Tdsclk Tdlrck Tdsdata Tsetup Thold 1.024 0.128 40:60 40:60 50:50 12.288 1.536 50:50 50:50 50:50 12.8 60:40 60:40 50:50 Unit
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
AUSYSCK DVDD
AUSCLK 1/Fsysck
DVDD
1/Fsclk
AULRCK
DVDD
AUSYSCK 1/Flrck
DVDD
SYDuty
AUSCLK
DVDD
SCDuty
AULRCK
DVDD
LRDuty
AUSCLK DVDD
AULRCK DVDD
AUSYSCK DVDD Tdsclk
AUSYSCK DVDD Tdlrck
Thold AUSDOUT DVDD AUSDIN DVDD
AUSCLK
DVDD Tdsdata
AUSCLK
DVDD Tsetup
NOTE: AUSCLK rising edge must occur same time AULRCK edge.
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
CODEC DIGITAL DATA INTERFACE
CODEC provides stereo, 16-bit functions. digital input output CODEC through serial input output ports. Codec related clock signals provided externally. CODEC other digital block communicates through serial output. interface consists serial input clock(AUSCLK), frame sync input clock(AULRCK), serial data output(AUSDOUT). Codec other digital block communicates through serial input. interface consists serial input clock(AUSCLK), frame sync input clock (AULRCK), serial data input(AUSDIN). digital reset power down, serial input disabled(all zeros). There kind serial interface CODEC digital data. Serial interface format controlled FORMAT pin. serial format. (when FORMAT "H") serial format. (when FORMAT "L") serial interface format frame sync clock transitions determine start serial data. Input data: first trailing leading unused bits. AULRCK transition marks 16bit, complement. Output data: first trailing leading unused bits. immediately first negative AUSCLK tranisiton after AULRCK transition. 16bit, complement. AULRCK HIGH OUT[AUSDOUT] Right Channel Left Channel INPUT[AUSDIN] Right Channel Left Channel
Clock 32Fs Right
AULRCK AUSCLK Left
AUSDOUT Right
Left
15;MSB, 0;LSB
AUSDIN
Codec serial interface timing diagram
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
serial format data input output changes occurs falling edge AUSCLK. careful attention LSB, after AULRCK transition. AULRCK sampling rate Take note AULRCK polarity. AULRCK HIGH OUT[AUSDOUT] Right Channel Left Channel INPUT[AUSDIN] Right Channel Left Channel
Clock 32Fs Right
AULRCK AUSCLK Left
Right
AUSDOUT
Left
15;MSB, 0;LSB
AUSDIN
Codec serial interface timing diagram
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
OVER RANGE
digital output CODEC will produce positive full scale[7FFF(h)] output analog input signal above maximum input voltage range negative full scale [8000(h)] input below minimum input voltage range.
POWER DOWN
Threr three power down mode, below table. Input PWDN<1:0> Value Condition Off, Off,
RESET
BW0407X digital block placed reset mode bringing AURST "H". Analog block still alive. exit reset mode, bring AURST "L", reset mode clock still operating, internal register reset mode.
ZERO DETECTION MUTE
anlaog 2-CH output CODEC will produce common level [VREF] digital zero input signal above number 8192 times sample cycle[AULRCK] input, either Left Right
CORE INTERNAL BLOCK TESTABILITY
Embedded Memory test TMODE= Built Self Test (BIST) mode embedded memor
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
31047 cycle When errors occured 2.483760 msec BIST finished time
TMODE AUSYSCK
ERRORB ERRORB
When errors occured
probing time
Memory BIST mode timing diagram
APPLICATION NOTES
Power Supply Grounding analog power pins codec should derived from cleanest power source available. decoupling capacitors placed close possible device. lowest value capacitor placed closest codec. circuit board layout should have separate analog digital regions ground planes. signal, especially clocks should kept away from VREF order avoid unwanted coupling into modulators postfilter. Analog Digital Connections analog inputs presented BW0407X single-ended input voltage. input range approximately 2.0Vp-p. analog outputs also single-ended output range typically 2.0Vp-p. on-chip voltage reference output VREF pin. electrolytic capacitor less than 10uF parallel with 0.1uF ceramic capacitor attached this eliminates effects high frequency noise. load current driven from VREF output pin.
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
PARAMETER DEFINITIONS
Resolution: number bits input words DACs, output words ADCs. Dynamic range: dynamic range available instant time. measured using S/(N+D) with 1KHz. -60dB input signal with 60dB added compensate small input signal. small input signal reduces harmonic distortion components noise insignificance. Units Signal Noise distortion Ratio. SNDR: value full scale signal lowest obtainable noise floor distortion. measured comparing full scale signal lowest noise floor distortion possible codec. Unit Total Harmonic Distortion. THD: value full scale signal lowest obtainable noise floor. measured comparing full scale signal lowest noise floor codec. Unit lowest noise floor acquired when analog input tied Vref. Interchannel Isolation: amount 1KHz signal present output grounded input channel with 1KHz signal present other channel. Unit Offset Error: ADCs, deviation LSBs output from mid-scale with selected input VREFH. DACs, deviation output from VREFH with mid-scale input code. Units volts.
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
PHANTOM CELL INFORMATION
Pins core assigned externally (Package pins) internally (internal ports) depending design methods. term "External" implies that pins should assigned externally like power pins. term "External/internal" implies that applications these pins depend user.
GAINSEL AUADPDML AUADPDMR
VSSA:G
VDDA:P
VREF:
REFH2L
REFH2R
REFL2L
REFL2R
AOUTR
AOUTL ANCKSE
bw0407x 16bit 48KHz Audio Codec
VDDA:P PWDN[0]
IREF AUSDIN
2358
VREF: AURST
REFIN PWDN[1]
VSSA:G MUTE
AINR
AINL
VERF:
REFH1L
REFH1R
REFL1L
REFL1R
VDDA:P
VSSA:G
REFL1R
VDDA:P
VSSA:G FORMAT AUTDECIR AUTDECIL
2120
ERRORB DIAG AUSDECI[0] AUSDECI[1] VDDD:P VSSD:G VDDD:P VSSD:G
AUSPDATA
AUSDOUT
AUSYSCK
MET1 MET2 MET3
AULRCK
AUSCLK
ANCK64
TMODE
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
Name VDDD:P
Usage Power Pins
Layout Guide
External/Internal Maintain large width lines pads. place port positions minimize length power lines. merge analog powers with another power from other blocks. good power ground source board. External/Internal External External Analog Pins
VSSD:G VDDA:P VSSA:G
AINL AINR AOUTL AOUTR VREF: REFH1L REFH2L REFH1R REFH2R REFIN REFL1L REFL2L REFL1R REFL2R
External External External External External Internal
overlap with digtal lines. Maintain shotest path pads.
overlap with digital line Each Must VREF respectively
Internal
overlap with digital line Each Must VSSA:G respectively
Digital Pins
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
Name AUSYSCK AUSCLK AULRCK AUSDOUT PWDN[0] PWDN[1] AURST MUTE TMODE DIAG ERRORB ANCKSE ANCK64 AUSPDATA GAINSEL AUTDECIL AUTDECIR AUSDECI[0] AUSDECI[1] AUADPDML AUADPDMR IREF
Usage External/Internal
Layout Guide Separate from other analog signals
External/Internal Internal Separated from analog clean signals possible.
Internal Internal Internal Block Test Pins Internal normal mode, these pins used, Each Must VSSD:G
Internal Internal Internal
Separate from other analog signals overlap with digital line
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
BW0407X
FEEDBACK REQUEST
should quite helpful CODEC core development specify your system requirements CODEC following characteristic checking table fill additional questions. appreciate your interest products. Thank very much. Could explain external/internal configurations required? Specially requested function list Parameter supply voltage master clock frequency Operating temperature Sampling Frequency Dynamic range Total harmonic distortion Signal-to-noise ratio Output format resolution (Serial/Parallel interface) Channel Power dissipation Input voltage range offset error group delay Phase linearity deviation passband region Peak-to-peak frequency response ripple passband region Dynamic range Total harmonic distortion Signal-to-noise ratio Input format resolution (Serial/Parallel interface) Channel Power dissipation Full scale output voltage range group delay Phase linearity deviation passband region Peak-to-peak frequency response ripple passband region Mono Stereo (Deg) Mono Stereo (Deg) Unit Remarks
BW0407X
0.35µm 16-BIT 48KHZ SIGMA-DELTA AUDIO CODEC
HISTORY CARD
Version Date 99.1.4 00.1.30 02.4.23 Modified Items Original version published (preliminary) Release datasheet (according Slilicon proven data) Appending phantom (GDS2) information Comments

BW0407X Samsung's BW0407X high resolution, single-chip stereo tha

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