BW0406X_LGISDN BW0406X_lgisdn Sigma-Delta CODEC speech telephony

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BW0406X_LGISDN BW0406X_lgisdn Sigma-Delta CODEC speech telephony

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0.35µm SIGMA-DELTA VOICE CODEC
BW0406X_LGISDN
BW0406X_lgisdn Sigma-Delta CODEC speech telephony applications. product contains both digital IIR/FIR filter smoothing filter. normal input output channels have format with 38dB signal distortion ratio. input output this device compressed form(A-law, m-law) 14bit linear which easily determined control select pins on-chip voltage reference circuit included allow single supply operation
FEATURES
Single chip voice line Codec (A/D, converter included) Oversampled Sigma Delta modulator/Demodulator Input/Output format 8bit u-law/A-law linear 14bit These three types easily selectible control pins When serial interface mode, 14bit linear data 16bit format with don't care bits from Sigma Delta 256X Oversampling chip Decimation Filter chip Smoothing Filter Sigma Delta 256X Oversampling chip 256X Interpolation Filter chip Analog Post Filter Single ended Input Output. Sampling Rate 8~11KHz chip voltage reference circuitry Single +3.3V Power Supply 2Vpp Output signal swing Power Consumption Operating Mode 10mW Typ(3.3V) Powerdown Mode 33uW Typ(3.3V)
TYPICAL APPLICATIONS
Speech Processing (Recognition, Synthesis, Compression etc.) Telephony Modem
BW0406X_LGISDN
0.35µm SIGMA-DELTA VOICE CODEC
BLOCK DIAGRAM WITH INPUT/OUPUT APPLICATION
AINFB0
ALOOP MUTE
TPOST
TDECI
REFH REFL
SINPO<1:0>
SDECI<1:0>
DAPWD SDOUT Serial Output
Analog Input0 Analog Input1
AINFB1 CIS<0> Analog Modulator CIS<1> Decimation filter
Serial Interface 14bit Linear 16bit format µ-law A-law
Voltage Reference Output
SDIN Serial Interface
VREFOUT
Voltage Reference
Analog Output0 Analog Output1
APOSTOUT0 APOSTOUT1
Analog Postfilter COS<1:0>> Differential Single circuit Smoothing filter
Digital Modulator
Interpolation filter
DADS
Selectible powerdown circuit
CPSEL
CIS<1:0> COS<1:0> X256FS
SYNC
VDDD
VSSD
VDDA
VSSA
ADPWD DAPWD
0.35µm SIGMA-DELTA VOICE CODEC
BW0406X_LGISDN
CORE DESCRIPTION
Name VDDA VSSA REFH REFL AMODIN0 AMODIN1 MUTE ALOOP VREFOUT AINFB0 AINFB1 APOSTOUT0 APOSTOUT1 ADPWD DAPWD X256FS SYNC SDECI<1:0> TDECI SINPO<1:0> SDIN TPOST CPSEL VSSD VDDD SDOUT DADS CIS<1:0> COS<1:0> Type vdda vssa piar50_bb piar50_bb piar50_bb piar50_bb picc_bb picc_bb poar50_bb poar50_bb poar50_bb poar50_bb poar50_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb vssd vddd pot2_bb picc_bb pot2_bb picc_bb pot2_bb Analog Power (+3.3V) Analog Ground (0.0V) Analog Reference Power(+3.3V) Analog Reference Ground (0.0V) Analog input Analog input Analog Mute select (High active) Analog loop back select (High active) Vref output Analog Input Gain control Analog Input Gain control Analog output Analog output Power Down1 (High active) Power Down2 (High active) Digital Reset (High active) 256*Sampling Freq.(FS) Clock Sampling Freq.(FS) Clock Digital Filter input select Digital Filter Test input Post Filter input select Serial Data Input Post Filter Test input Linear/Compand data select (Low/High) m-law/A-law select (Low/High) Digital Ground Digital Power Supply Serial Data Output Clock Modulator output Analog Input Select Pins Analog Output Select Pins Description
BW0406X_LGISDN
0.35µm SIGMA-DELTA VOICE CODEC
NOTES: This description fixed, recommended. Power pin(VDDA,VDDD) must connected DIODE_SLOT2. Ground (VSSA, VSSD) must connected DIODE_SLOT2. SDECI<1:0>, TDECI Decimation Filter Block test pin. SINPO<1:0>, TPOST Post Filter Block test pin. operate power down mode, control select pins, ADPWD DAPWD must activated simultaneously. followings input/output selection mute control pins, these pins instead MUTE pin.
CIS<1:0>
STATUS AMODIN1 MUTE, AMODIN0 MUTE AMODIN1 MUTE, AMODIN0 ACTIVE AMODIN1 ACTIVE, AMODIN0 MUTE AMODIN1 ACTIVE, AMODIN0 ACTIVE
COS<1:0>
STATUS APOSTOUT1 MUTE, APOSTOUT0 MUTE APOSTOUT1 MUTE, APOSTOUT0 ACTIVE APOSTOUT1 ACTIVE, APOSTOUT0 MUTE APOSTOUT1 ACTIVE, APOSTOUT0 ACTIVE
Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
0.35µm SIGMA-DELTA VOICE CODEC
BW0406X_LGISDN
CORE CONFIGURTION
COS<1:0> CIS<1:0> SYNC TPOST TDECI DAPWD ADPWD CPSEL SDIN X256FS ALOOP MUTE SINPO<1:0> SDECI<1:0> AINFB1 AINFB0 AMODIN1 AMODIN0 REFH REFL VDDD VSSD VDDA VSSA DADS SDOUT
bw0406x_lgisdn
VREFOUT APOSTOUT0 APOSTOUT1
BW0406X_LGISDN
0.35µm SIGMA-DELTA VOICE CODEC
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage Digital Input Voltage Storage Temperature Range Operating Temperature Range Symbol VDDD Tstg Topr Value -0.3 -0.3 Unit
NOTES: ABSOLUTE MAXIMUM RATING specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values ke+pt within following operating conditions function operations under these conditions implied. voltages measured with respect VSS(VSSA VSSD) unless otherwise specified.
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Supply Voltage Difference Digital Input Voltage Range Analog Input Voltage Range Symbol VDDA VSSA VDDD VSSD VDDA VDDD 3.15 3.45 Unit
NOTE: strongly recommended that supply pins (VDDA, VDDD) powered from same source avoid power latch
CONTROL CLOCK CHARACTERISTICS
Characteristics X256FS Minimum Pulse Width Minimum Pulse Width High SYNC Frequency clock) Duty Cycle Symbol 1.843 2.048 2.816 Unit Conditions Fs=8KHz
0.35µm SIGMA-DELTA VOICE CODEC
BW0406X_LGISDN
ELECTRICAL CHARACTERISTICS
(Measurement Bandwidth 20Hz-4KHz. Full scale input sine wave 1KHz, FS=8KHz, @VDDA=3.3V, Ta=25°C, Unless otherwise specified.) Characteristics Resolution Sampling rate Signal Distortion Ratio Symbol Offset Error Input Voltage Range Signal Distortion Ratio Offset Error Output Voltage Range Passband Passband Ripple Stopband Stopband Attenuation Power comsumption (3.3v Operating Mode) Analog Digital Power comsumption (3.3v Powerdown Mode) Power Supply +/-0.25 0.6375 29.5 33.5 Vp-p Unit Bits Input compand Input Linear -40dB Input u-Law compand -40dB Input A-Law compand -45dB Input u-Law compand -45dB Input A-Law compand Input compand Input Linear -40dB Input u-Law compand -40dB Input A-Law compand -45dB Input u-Law compand -45dB Input A-Law compand Conditions
Analog Input Characteristics
Analog Input Characteristics
Digital Filter Specification
BW0406X_LGISDN
0.35µm SIGMA-DELTA VOICE CODEC
CORE LAYOUT GUIDE
N-WELL Guardring Guardring VDDD VSSD
DIGITAL BLOCK
Analog Input
ANALOG BLOCK
VDDA Guardring Analog Output VSSA
NOTES: layout bw0406x consists digital part analog part. digital part analog part must divided. substrate digital analog part seperated from digital analog ground that minimize noise through substrate. recommended that thick analog power metal. when connecting PAD, path should kept short possible. Digital power analog power used separately. When core block connected other blocks, must double guardring using N-well P+active remove substrate coupling noise. that case, power metal should connected directly. Digital input signal lines must same length reduce difference delay.
0.35µm SIGMA-DELTA VOICE CODEC
BW0406X_LGISDN
CORE EVALUATION GUIDE
VSSD VDDD MUTE ALOOP ADPWD VDDA VSSA Analog Input X256FS SYNC Analog Output
AMODIN AINFB APOSTOUT VREFOUT REFH
BW0406X
SDECI<1:0> TDECI DAPWD SINPO<1:0> SDIN
Controller
REFL
TPOST CPSEL
SDOUT DADS
Table Connection User Guide Line Embedded Core Test Location Description 0.1mF TANTALUM CAPACITOR 10mF CERAMIC CAPACITOR 0.33mF TANTALUM CAPACITOR 75pF CERAMIC CAPACITOR 50kW RESISTOR 200kW RESISTOR 0.1uF TANTALUM CAPACITOR
NOTES: SDOUT externally shorted with SDIN, CODEC achieved loop-back test mode(ADC->DAC). users want test CODEC integrated chip, above must extracted PAD(pin 14). analog power/ground must separated from digital power/ground. CPSEL A-law select, m-law select TYPE denote Power Ground respectively. Power typical value: VDDA VDDD 3.3V, VSSA VSSD 0.0V
BW0406X_LGISDN
0.35µm SIGMA-DELTA VOICE CODEC
PACKAGE CONFIGURATION
REFH REFL APOSTOUT0 APOSTOUT1 NC21 VDDA NC32 DADS SINPO<0> TPOST VDDP VSSP NC31
SINPO<1> MUTE NC27 SDIN DAPWD ADPWD NC41 NC42 X256FS CPSEL SYNC SDOUT NC24
3.3V
BW0406X
NC19 VREFOUT VSSA COS<1:0> AMODIN0
SDECI<1>
SDECI<0>
AINFB1
ALOOP
AMODIN1
AINFB0 NC13
VDDD
VSSD
TDECI
LOCATION
10uF TANTALUM CAPACITOR 0.1uF CERAMIC CAPACITOR FERRITE BEAD (0.1mH)
CIS<1:0>
DESCRIPTION
0.35µm SIGMA-DELTA VOICE CODEC
BW0406X_LGISDN
CONTROL CLOCKS CHARACTERISTICS
Characteristics X256FS Frequency Frequency SYNC Frequency X256FS Duty cycle (H:L) Duty cycle (H:L) SYNC Duty cycle (H:L) X256FS Falling Edge Delay(Hold) X256FS Falling SYNC Edge Delay(Hold) Falling SDOUT Delay Rising SDIN Setup Rising SDIN Hold Symbol Fmck Fbck Fsync MCDuty BCDuty SYDuty Tdbck Tdsync Tdsdout Tsetup Thold 40:60 40:60 40:60 2.048 50:50 50:50 50:50 60:40 60:40 60:40 Unit
BW0406X_LGISDN
0.35µm SIGMA-DELTA VOICE CODEC
X256FS
VDDD
1/Fmck
VDDD
1/Fbck
SYNC
VDDD
X256FS 1/Fsync
VDDD
MCDuty
VDDD
BCDuty
SYNC
VDDD
SYDuty
VDDD
VDDD
X256FS
VDDD Tdbck
X256FS
VDDD Tdsync Thold
SDOUT
VDDD
SDIN
VDDD
VDDD Tdsdout
VDDD Tsetup
*Notes rising edge must occur same time SYNC edge.
0.35µm SIGMA-DELTA VOICE CODEC
BW0406X_LGISDN
TIMING DIAGRAM
frame sync clock(SYNC) transitions determine start serial data. Input data input data clocked falling edge BCK. 14bit, complement 8bit A-law, u-law data format. output data clocked falling edge BCK. 14bit, complement 8bit A-law, u-law data format.
Output data
NOTES: SYNC clock sampling frequency, 14bit linear data 16bit serial data format, this accomplished 16FS clock don't care bits added from LSB, into 16bit format.
BW0406X_LGISDN
0.35µm SIGMA-DELTA VOICE CODEC
Codec serial interface timing diagram
Clock
SYNC
16Fs
MSB, MSB,
Non-valid data insetion)
SDOUT[ADC output](Linear data)
Non-valid data insetion)
SDOUT[ADC output](Compressed data)
Don't care data
MSB,
SDIN [DAC input](Linear data)
Don't care data
MSB,
SDIN [DAC input](Compressed data)
Codec clock interface timing diagram
SYNC
16Fs
256Fs
X256FS
0.35µm SIGMA-DELTA VOICE CODEC
BW0406X_LGISDN
INPUT/OUTPUT APPLICATION GUIDE
Input stage application guide
AINFB0 AINFB1 AMODIN0 AMODIN1
Analog Input
Typhical value 0.33mF
Output stage application guide
APOSTOUT0 APOSTOUT1
Speaker Driver Ground
determine value 1.5*10-5/R3 example choose 200K, then value 75pF.
VREFOUT port application guide
VREFOUT Ground
0.1mF, 10mF Note user should dispose order shown above dispose capacitors VREFOUT close possibe.
BW0406X_LGISDN
0.35µm SIGMA-DELTA VOICE CODEC
PHANTOM CELL INFORMATION
0.35µm SIGMA-DELTA VOICE CODEC
BW0406X_LGISDN
LAYOUT GUIDE
BW0406X_LGISDN
0.35µm SIGMA-DELTA VOICE CODEC
FEEDBACK REQUEST
should quite helpful CODEC core development specify your system requirements CODEC following characteristic checking table fill additional questions. appreciate your interest products. Thank very much. Could explain external/internal configurations required? Specially requested function list What your signal band use, 3.6KHz? 4KHz? 4.8KHz? What your analog in/output signal voltage swing? what kind format your want analog signal in/ouput: single differential format? can, Please know, what your exact in/output signal spec. What your minimum S/N+D spec? want linear phase characteristic don't care digital filter spec? Could give exact design spec speech codec? (For example, A-law, u-law on.)
REVISION HISTORY
Version Date 02.04.28 Modified Items Digital Filter Specification added p12: Phantom Cell Information added p13: Layout Guide added typo corrected Comments
02.07.30

BW0406X_LGISDN BW0406X_lgisdn Sigma-Delta CODEC speech telephony

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