BW0405XA This product Digital-To-Analog Converter digital audio S
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0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
BW0405XA
This product Digital-To-Analog Converter digital audio System (CDP). product contains Serial-toParallel Converter Compensation Filter, Digital Volume Attenuator MICOM Interface, De-Emphasis Filter, filter, Sinc Filter, digital sigma-delta modulator, analog postfilter, (Anti-Image-Filter). normal input output channels provides 90dB (Signal Noise Ratio) over band (20kHz). product employs 1bit 4th-order sigma-delta architecture with 16bit resolution, over sampling 64X. analog postfilter with clock sensitivity linear phase, filters shaping-nosie outputs analog voltage with high resolution. on-chip reference voltage included allow single supply operations.
FEATURES
16bit Digital-To-Analog Converter On-Chip Analog Postfilter Filtered Line-Level Outputs, Linear Phase Filtering On-Chip Voltage Reference 90dB Sampling Rate 44.1kHz Input Rate Normal Mode/Double Mode Selection Zero Input Detection Mute On-Chip Compensation Filter Input Volume Attenuator MICOM Interface On-Chip De-Emphasis Filter On-Chip times oversampling Digital Filter Clock Jitter Sensitivity Single 3.3V~2.5V Power Supply
APPLICATIONS
Player, Portable Player, CD-ROM, Video-CD, Mini-Disk,
BW0405XA
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
FUNCTIONAL BLOCK DIAGRAM
VDDD VSSD
VDDA VSSA
SDATA LRCK
Converter Attenuator
Compensation Filter De-emphsis Filter
Sinc Filter Sigma-Delta Modulator
Analog Postfilter
AOUTL Anti-Imaging Filter AOUTR
MICOM Interface
Timing Generation
Voltage Reference
VREF VHALF IREF
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
BW0405XA
EMBEDDED CORE BLOCK DIAGRAM
External Inputs MSCK LRCK SDATA External AOUTL AOUTR VHALF VREF DEEM MUTEL RSTB MCLK MDATA BISTONP TSEL IFS64 IADSL IADSR
MUX_SEL
Audio Processor (DSP)
bw0405xa
IREF SDIAG SERRORB OFS64 ODSL ODSR
VSSD
These test pins internal blocks core. don't need internal test mode. Make test control pins disable ('L') state Output bidirectional pins leave foalting.
EMBEDDED CORE USER GUIDE
Digital serial data input clock input refer digital input format. Digital control pins inform refer description. Micom inform refer micom interface. External application analog output pins refer application circuit. want test only embedded analog core block (Sigma-Delta DAC), just adding pins supply digital serial input data (LRCK, BCK, SDATA, MSCK) block. Analog power(VDDA,VSSA) digital power(VDDD, VSSD) should seperated. pads should dedicated analog power(VDDA, VSSA) need test mode testability internal core block, make internal core block test pins disable state. (Test Input pins state Test output, bidirection pins leave floating)
BW0405XA
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
CORE DESCRIPTION
Symbol Power Supply Pins VDDD VSSD VDDA VSSA Digital Pins MSCK LRCK SDATA MCLK MDATA DEEM MUTEL RSTB Analog Pins AOUTL AOUTR VHALF VREF BISTONP TSEL IFS64 IADSL IADSR SDIAG SERRORB OFS64 ODSL ODSR IREF poa_bb poa_bb poar50_bb poar50_bb picc_bb picc_bb picc_bb picc_bb picc_bb pot2_bb pot2_bb pot2_bb pot2_bb pot2_bb poa_bb Analog Output L-CH Analog Output R-CH Reference Voltage Output Bypass Reference Voltage Output Bypass Memory Bist Test Mode. enabled Test Analog Postfilter Input Selection Sampling Clock Input Analog Postfilter (When TSEL=H) Inputs Analog Postfilter L-CH (When TSEL=H) Inputs Analog Postfilter R-CH (When TSEL=H) Test Output embeded memory BIST (BIST_ON="H") Test Output Embeded memory BIST (BIST_ON="H") Sampling Clock output Digital sigma-delta Modulator L-CH Output Digital sigma-delta Modulator. R-CH Output Digital sigma-delta Modulator. Test Analog Supply Current picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb picc_bb Master Clock Input. 384Fs Clock Clock Input. (32Fs 64Fs) Sample Rate Clock Input. 2Fs) Serial Digital Input Micom Interface Clock Input Micom Interface Command load Input (When low,load) Micom Interface Command Data Input De-Emphasis On/Off. enabled. disabled. Input Rate Select. High Double(2Fs) Mode, Normal(Fs) Mode. Analog Output Mute. enabled Power Down. enabled Reset Input. Enabled vdd3t_bb vsst_bb vdd3t_bb vsst_bb Digital Supply Digital Ground Analog Supply Analog Ground Type Description
Core Internal Block Test Pins
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
BW0405XA
Type Abbr. Analog Input Digital Input Analog Output Digital Output Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
BW0405XA
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
CORE CONFIGURTION
MSCK LRCK SDATA MCLK MDATA DEEM MUTEL RSTB BISTONP TSEL IFS64 IADSL IADSR
AOUTL AOUTR VHALF VREF
bw0405xa
Used Power: (VDDD VSSD VDDA VSSA)
IREF SDIAG SERRORB OFS64 ODSL ODSR
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Voltage Digital Storage Temperature Range Symbol VDDD,VDDA Tstg Values -0.15 VSS-0.15 VDD+0.15 +125 Unit
RECOMMENDED OPERATING CONDITIONS
Charateristics Supply Voltage Operating Temp. SYMBOL VDDD VDDA Topr UNITS
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
BW0405XA
ELECTRICAL CHARACTERISTICS
(VDDD,VDDA=2.5V, Temp=25°C, Fs=44.1kHz, Signal Frequency=20-20kHz, Cload AoutL, AoutR=10pF) Parameter Resolution
0.005
Units bits
0.01
SND(THD+Noise) Dynamic Range
VDDA 0.75 VDDA
Reference Voltage Ouput Frequency Responce Analog Output Voltage Range Load Impedance Digital Filter Pass Band Ripple Stop Band Attenuation Pass Band Power Supply Analog Current Digital Current Power Dissipation Power Down Current
NOTES: 1kHz Sinewave Input, EIAJ 1kHz -3dB Sinewave Input 1kHz Sinewave Input, (Not EIAJ) 1kHz -60dB Sinewve Input, then measured data 60dB
0.0072 62.7 0.45 17.5 22.5
BW0405XA
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
TIMING CHARACTERISTICS
(VDDD=2.5V, VSSD=0V, Temp=25°C) Characteristics MSCK Frequency Frequency (Normal/Doube Mode) MSCK Rising LRCK Edge Dealay MSCK Risng LRCK Edge Setup Time Rising LRCK Edge Dealay Risng LRCK Edge Setup Time SDATA Rising Setup Time Ring SDATA Hold Time Symbol Fmck Fbck Tmld Tmlst Tbld Tblst Tsbst Tbsht 16.9344 1.4112 2.8224 Unit
MSCK VDDD 1/Fmck
VDDD 1/Fbck
LRCK Tmld MSCK Tmlst
VDDD
VDDD
LRCK Tbld Tsbst SDATA Tbsht Tblst
VDDD
VDDD
VDDD
Figure Timing Chart
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
BW0405XA
CLOCK INPUT SERIAL INPUT DATA INFORM (FS=44.1KHZ)
normal double mode selection control pin. Refer following table clock input inform. Table Input Clock Informs Normal Mode (DN='Low') LRCK MSCK 44.1kHz 16.9344MHz 1.4112MHz Double Mode (DN='High') 88.2kHz 16.9344MHz 2.8224MHz
Serial input data (SDATA) fisrt falling edge triggered BCK.
LRCK
R-CH DATA
L-CH DATA
SDATA
MSB-1 MSB-2
LSB+2 LSB+1
MSB-1 MSB-2
LSB+2 LSB+1
Figure Digital Input Data Format
MICOM INTERFACE (DIGITAL ATTENUATION)
This product function digital attenuation whenever receives MDATA, MLD, MCLK signals form MICOM. When 14-bit serial data applied MDATA, MCLK, form Fig3, according data digital attenuation accomplished. lower eight LSBs should 5D(LSB First Format-Hex) according upper bits(LSB First Format-Bin) attenuation level adjusted. (see Table1) When RSTB state latch circuitry setting attenuation level becomes reset attenuation level 0dB. this instance, because digital filter circuit gets stop operation attenuation impossible. addition, whenever MDATA carried, MCLK must 'HIGH' state. case attenuation fuction needed, MDATA should 'L', MCLK should
MCLK MDATA Don't Care D(Hex) 5(Hex) Don't Care
Over 550ns needed
Figure MICOM Interface Timing Chart
BW0405XA
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
Table Digital Attenuation Level MDATA -0.28 -0.42 -0.56 -0.71 -0.86 -1.01 -1.16 -1.32 -1.48 -1.64 -1.80 -1.97 -2.14 -2.32 -2.50 -2.68 -2.87 -3.06 -3.25 -3.45 -3.66 -3.87 -4.08 -4.30 -4.53 -4.76 -5.00 -5.24 -5.49 -5.75 -6.02 Attenuation Level (dB) MDATA -6.30 -6.58 -6.88 -7.18 -7.50 -7.82 -8.16 -8.52 -8.89 -9.28 -9.68 -10.10 -10.55 -11.02 -11.51 -12.04 -12.60 -13.20 -13.84 -14.54 -15.30 -16.12 -17.04 -18.06 -19.22 -20.56 -22.14 -24.08 -26.58 -30.10 -36.12 Attenuation Level (dB)
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
BW0405XA
FUNCTIONAL DESCRIPTION
MCLK MDATA
DEEM
MUTEL
SDATA LRCK
1Fs/2Fs 16bits
Converter Attenuator
Compensation Filter De-emphasis/ Filter
4Fs/8Fs 16bits
Sinc Filter Modulator
64Fs 1bit
4bit SC-Postfilter
Anti-Image Filter
AoutL AoutR
Figure Funtional Block Diagram Fig4 1bit order sigma-delta block daigram. Converter converts serial 16bit input data parallel 16bit data. Digital input data attenuated MICOM interface control. Compensation Filter compensates gain droop Passband Sinc Filter Sigma-Dellta Modulator Signal Transfer Function. De-emphasis Block deemphasizes pre-emphasised input data emphssize high frequency audible band. Filter perfroms interpolation. outputs 4Fs(DN='Low') rate data 8Fs(DN='High') rate data variabled input data rate. also removes images input signal that present multiples input sample frequency. Sinc filter makes constant 64Fs rate data times times upsampling Filter output data according DN(Double/Normal Mode) Selection. This operation intorduces sinc function responce resulting frequency spectrum, which greatly attenuates energy images multifules 4Fs(or 8Fs). Digital sigma-delta modulator bit-stream type (Inverse-Follower-Leader) topology, performs noise-shaping function. modulator shapes quantization noise suppressing in-band component pushes noise energy outside band-of-interest without deteriorating audio input signal. times oversampled 1-bit outputs from modulator drives analog postfilter. analog postfilter comprises SC-postfilter, anti-imaging filter. SC-postfilter removes quantization noise shaped out-of-band digital sigma-delta modulator. This analog filter good clock jitter characteristc very linear characteristic. following CTF(continuous time filter) removes sampling images makes high resolution analog output.
BW0405XA
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
APPLICATION CIRCUIT
VDDA
0.1uF
10uF
Analog Ground Plane
VSSA
VSSA
VDDD
0.1uF
10uF
VSSD
VSSD
Digital Ground Plane
Figure Bypass Capacitor Power Supply Pins
VHALF
0.1uF
10uF
VSSA
VREF
0.1uF
10uF
VSSA
Figure Bypass Capacitors Reference Pins
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
BW0405XA
Analog pins digital pins must seperated, Analog pins should located analog ground plane digital pins should located digital ground plane. Analog ground digital ground connection recommended only path through ferrite bead like Fig5. Supply bypass capacitors should located close possible chip. Small bypass capacitor (0.1uF) should positioned first chip than large bypass capacitor (10uF). Reference (VHALF, VREF) bypass capacitors (Fig6) should located close possible chip.
AOUTL
100k
L-CH Output
AOUTR
100k
R-CH Output
Figure Ananlog output application FIg7 simple high pass filter circuit analog output. performs ac-coupling analog output signal from analog common level analog ground. Recommended component values 100k. User Guide This analog Core Verilog behavioral-modeling will supplied.
BW0405XA
0.35µm 16-BIT 44.1KHZ SIGMA-DELTA STEREO
FEEDBACK REQUEST
Sigma-Delta Specification appreciate your interest products. have further questions, please specify attached form. Thank very much. Parameter supply voltage master clock frequency Operating temperature Sampling Frequency Dynamic range Total harmonic distortion Signal-to-noise ratio Input format resolution (Serial/Parallel interface) Channel Power dissipation Full scale output voltage range Group delay Phase linearity deviation passband region Peak-to-peak frequency response ripple passband region Mono Unit Stereo (Deg) Remarks
Could explain external/internal configurations required? Specially requested function list:
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