AL2007LA AL2007LA Phase-Locked Loop (PLL) frequency synthesizer c

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

AL2007LA AL2007LA Phase-Locked Loop (PLL) frequency synthesizer c

Datasheet Thumbnail

Top Searches for this datasheet

0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
AL2007LA Phase-Locked Loop (PLL) frequency synthesizer constructed CMOS single monolithic structure. macrofunctions provide frequency multiplication capabilities. output clock frequency Fout related reference input clock frequency following equation: Fout m*Fin Where, Fout output clock frequency. reference input clock frequency. values programmable dividers. AL2007LA consists phase/Frequency Detector(PFD), Charge Pump External Loop Filter, Voltage Controlled Oscillator(VCO), 6bit Pre-divider, 8bit Main divider 2bit Post Scaler shown Figure1.
FEATURES
0.35um CMOS device technology Volt Single power supply frequency range: 60~170MHz Output frequency range: 20~170MHz Jitter ±150ps Duty ratio 170MHz Frequency changed programmable divider Power down mode IMPORTANT NOTICE Please contact application engineer confirm proper selection M,P,S value.
FUNCTIONAL BLOCK DIAGRAM
Divider
Charge Pump
Loop Filter (External)
Post Scaler
Fout
Main Divider
Figure Phase Lockd Loop Block Diagram
AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
CORE DESCRIPTION
Name VDDA VSSA FILTER FOUT PWRDN Type AB/DB vddd vssd vdda vssa vbba picc_bb poar50_bb pot12_bb picc_bb Digital power supply Digital ground Analog power supply Analog ground Analog/Digital bias Power clock input Pump connected Filter capacitor connected between analog ground 20MHz~170MHz clock output FSPLL clock power down. PWRDN High, operating under this condition. isn't used this pin, tied VSS. values 6bit programmable pre-divider. values 8bit programmable main divider. values 2bit programmable post scaler. Description
P[5:0] M[7:0] S[1:0] Type Abbr. Analog Input Digital Input Analog Output Digital Output
picc_bb picc_bb picc_bb
Analog Bidirectional Digital Bidirectional Analog Power Digital Power Analog Ground Digital Ground
0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
CORE CONFIGURATION
PWRDN M[7:0] M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7] P[0] P[1] P[2] P[3] P[4] P[5] S[0] S[1]
FOUT
FILTER
al2007la
P[5:0]
S[1:0]
AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
ABSOLUTE MAXIMUM RATINGS
Characteristics Supply Voltage Voltage Digital Storage Temperature Symbol VDDA Tstg Value -0.3 Vss-0.3 Vdd+0.3 Unit Applicable VDD,VDDA,VSS,VSSA P[5:0],M[7:0],S[1:0] PWRDN
NOTES: ABSOLUTE MAXIMUM RATING specifies values beyond which device damaged permanently. Exposure ABSOLUTE MAXIMUM RATING conditions extended periods affect reliability. Each condition value applied with other values kept within following operating conditions function operation under these conditions implied. voltages measured with respect unless otherwise specified. 100pF capacitor discharged through 1.5K resistor (Human body model)
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Differential External Loop Filter Capacitance Operating Temperature Symbol VDDA Topr -0.1 +0.1 Unit
NOTE: strongly recommended that supply pins (VDDA, VDD) powered from same source avoid power latch-up.
0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
ELECTRICAL CHARACTERISTICS
Characteristics Operating Voltage Digital Input Voltage High Digital Input Voltage Dynamic Current (CORE Level without Cell) Power Down Current Symbol VDD/VDDA 3.15 3.45 Unit
ELECTRICAL CHARACTERISTICS
Characteristics Input Frequency Output Clock Frequency Output Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle Locking Time Cycle Cycle Jitter Symbol FOUT Fvco TJCC -150 14.318 +150 Unit
AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
FUNCTION DESCRIPTION
circuit synchronizing output signal (generated VCO) with reference input signal frequency well phase. this application, includes following basic blocks. voltage-controlled oscillator generate output frequency divider devides reference frequency divider devides output frequency divider divides output frequency phase frequency detector detects phase difference between reference frequency output frequency (after division) controls charge pump voltage. loop filter removes high frequency components charge pump voltage does smooth clean control values programmed 16bit digital data from external source. locked desired frequency. Fout 14.318MHz, m=M+8 p=P+2, s=2^S Digital data format: Main Divider M7,M6,M5,M4,M3,M2,M1,M0
NOTES: S[1] S[0]: Output Frequency Scaler M[7] M[0]: Frequency Divider P[5] P[0]: Reference Frequency Input Divider
Divider P5,P4,P3,P2,P1,P0
Post Scaler S0,S1
0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
OUTPUT FREQUENCY EQUATION TABLE
Frequency Equation
Table Example Divider Ratio
(m+8) (p+2)
(p+2)
(m+8)
NOTES: Don't zero, that 000000 00000000 proper range 1<=P<=62, 1<=M<=248 must selected considering stability output frequency range Please consult with application engineer select proper values
AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
CORE EVALUATION GUIDE
embedded PLL, must consider test circuits embedded core inmultiple applications. Hence following requirements should satisfied. FILTER FOUT pins must bypassed external test. test (Below examples), needed control dividers M[7:0],P[5:0] S[1:0] -that generate multiple clocks. Example Registers used easy control divider values. Example sample bits 16-bit divider pins bypassed test using MUX.
3.3V Power
Digital
3.3V Analog Power
External Clock Source
VDDA VSSA VBBA
FOUT PWRDN M[7:0]
al2007la
FILTER
#1.16bit Register Block
P[5:0]
820pF S[1:0] VSSA
Select
NOTES
Test Pins Sample bits
Internal Divider Signal Line
10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED
0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
CORE LAYOUT GUIDE
digital power(VDD,VSS) analog power(VDA,VSSA) must dedicated only seperated. dedicated allowed that least power consuming block shared with PLL. used FILTER that contains only production diodes without resistors buffers. FOUT FILTER pins must placed from internal signals order avoid overlapping signal lines. blocks having large digital switching current must located away from core. core must shielded guardring. FOUT pad, custom drive buffer POT12 buffer considering drive current.
WITHOUT XTAL-DRIVER USERS GUIDE
There crystal driver cell (XTAL-OSC PSOSCM2) options AL2007LA core. crystal component used external clock source applied Please contact application engineer when using crystal. crystal component used external clock Buffer offered from Samsung's STD90 library recommanded When implementing embedded block, following pins must bypassed externally testing locking function: Without Xtal-driver FIN,FILTER,FOUT,VDDA,VSSA,VDD VSS.
AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
FILTER
FOUT
VDDA VSSA VBBA
Used PICC_BB
Divider
Scaler
PWRDN
Divider
P[5:0] M[7:0] S[1:0]
Glue Logic
Divider
Optional Test Pins
Figure example block without crystal component (Normal Case)
0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
PACKAGE CONFIGURATION
2bit Post Scaler Dummy Test Block Control pins 3.3V Digital Power
3.3V Power
8bit Main Divider
FOUT
al2007la
10uF
VBBA VBBA PWRDN FILTER
820pF
External Clock Source
VDDA
6bit Divider Input
VDDA
3.3V Analog Power
NOTES: TSEL0,TSEL1 pins internal dummy block test pins. Noconnection
AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
PACKAGE DESCRIPTION
Name VDDD VSSD PWRDN 35,36 33,34 Type Digital ground FSPLL clock power down -PWRDN High, operating under this condition. isn't used this pin, tied VSS. Pre-Divider Input(LSB) Analog power supply Analog ground Analog Digtal Bias Power Crystal input external FREF input 20MHZ~170MHz clock output Pump connected FILTER. 820pF Capcitor connected between analog FOUT divide control pins. -End users used this pins, tied FOUT divide control pins. -End users used this pins, tied Post scaler input 8bit main divider input Power Ground Description Digital power supply
P[0]~P[5] VDDA VSSA VBBA FOUT FILTER
1,2,45~48 13,14 11,12 19,20
AB/DB
TSEL0 TSEL1 S[0]~S[1] M[0]~M[7] VDDO VSSO
31,32 37~44
NOTE: TYPE denote power ground respectively.
0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
DESIGN CONSIDERATIONS
following design consideratios apply: Phase tolerance jitter independent frequency. Jitter affected noise frequency power(VDD/VSS,VDDA/VSSA). increases when noise level increases. CMOS-level input reference clock recommend signal compatibility with circuit. Other levels such degrade tolerances. two, more PLLs requires special design considerations. Please consult your application engineer more information. following apply noise level, which minimized using good analog power ground isolation techniques system: wide traces POWER(VDD/VSS, VDDA/VSSA) connections core. Seperate traces from chip's VDD/VSS,VDDA/VSSA supplies. proper VDD/VSS,VDDA/VSSA de-coupling. good power ground sources board. Power minimize substrate noise core should placed close possible dedicated loop filter analog Power ground pins. inadvisable locate noise-generating signals, such data buses high-current outputs, near cells. Other related signals should placed near have pre-defined placement restriction
AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
FEEDBACK REQUEST
Thank having interest products. Please fill this form, especially items which want request. Parameter Process Supply voltage (VDD) Input frequency (FIN) Output frequency (FOUT) Cycle cycle jitter (TJCC) 100M 200M 200M 300M 300M 400M 400M 500M Period jitter (TJP) 100M 200M 200M 300M 300M 400M 400M 500M Output duty ratio (TOD) Lock time (TLT) Dynamic current Stand current Filter capacitor many PLLs embedded your system need synchronization between input clock output clock need another spec jitter Parameter Long-term jitter (TJLT) Tracking Jitter (TJT) have another special request, please describe below. Customer Unit psec (pk-pk) psec (pk-pk) Customer Unit
0.35µm 20MHZ-170MHZ FSPLL
AL2007LA
JITTER DEFINITION
Period Jitter Period jitter maximum deviation output clock's transition from ideal position.
Ideal Cycle Fout
Cycle-to-Cycle Jitter Cycle-to-cycle jitter maximum deviation output clock's transition from corresponding position previous cycle.
Ti-1 Fout
Ti+1
TJCC (Ti+1
Long-Term Jitter Long-term jitter maximum deviation output clock' transition from ideal position, after many cycles. term "many" depends application frequency.
Cycle
Cycle
TJLP
AL2007LA
0.35µm 20MHZ-170MHZ FSPLL
Tracking Jitter Tracking jitter maximum deviation output clock(FOUT)'s transition from input clock (FIN) position.
Trigger
Delay
Fout

AL2007LA AL2007LA Phase-Locked Loop (PLL) frequency synthesizer c

Top Searches for this datasheet

Other recent searches