0.25µm 20MHz~170MHz FSPLL PLL2013X Phase-Locked Loop (PLL) freque
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PLL2013X
0.25µm 20MHz~170MHz FSPLL
PLL2013X Phase-Locked Loop (PLL) frequency synthesizer constructed CMOS single monolithic structure. macro-functions provide frequency multiplication capabilities. output clock frequency Fout related input clock frequency Fin(XTALIN) following equation: Where, Fout output clock frequency. input clock frequency. values programmable dividers. PLL2013X consists phase/Frequency Detector(PFD), Charge Pump External Loop Filter, Voltage Controlled Oscillator(VCO), 6bit Pre-divider, 8-bit Main divider 2bit Post Scaler shown Figure1.
FEATURES
0.25mm CMOS device technology Volt single power supply frequency range: 80M~170MHz Output frequency range: Jitter ±150ps 170MHz Duty ratio (All tuned range) Frequency changed programmable divider Provision 14.318Mhz crystal oscillator buffer OPTION Power down mode
TYPICAL APPLICATIONS
Hard Disk Driver (HDD) Battery Operated Instruments Motor Control Systems General Applications
IMPORTANT NOTICE Please contact application engineer confirm proper selection M,P,S value.
0.25µm 20MHz~170MHz FSPLL
PLL2013X
FUNCTIONAL BLOCK DIAGRAM
Divider
Charge Pump
Post Scaler
FOUT
Loop Filter
Main Divider
Figure Phase Locked Loop Block Diagram
NOTE: Xtal oscillator OPTIONAL block. customer concerns about this block xtal buffer lock detector, refer next chapter.
(Dec, 2002) responsibility assumed infringements patents other rights third parties that result from use. contents data sheet subject change without notice.
PLL2013X
0.25µm 20MHz~170MHz FSPLL
CORE DESCRIPTION
Name VDD25A2 VSS25A2 VDD25A1 VSS25A1 VBBA FILTER Type AB/DB vdd2t_abb vss2t_abb vdd2t_abb vss2t_abb vbb_abb picc_abb poar50_abb Digital ground Analog power supply Analog ground Analog Digital bias Reference Frequency Input Pump connected Filter capacitor connected between analog ground 20MHz~170MHz clock output FSPLL clock power down. When PWRDN High, operate. Customer don't this pin, Apply VSS. values 6bit programmable pre-divider. values 8bit programmable main divider. values 2bit programmable post scaler. Description Digital power supply
FOUT PWRDN P[5:0] M[7:0] S[1:0]
pot8_abb picc_abb
picc_abb picc_abb picc_abb
NOTES: recommends customers power cell type vdd2t_abb, vss2t_abb. When using recommended power cells, customers must slot cells separating digital analog power. Please contact when customers recommended power cells customer arrange this cells product.
TYPE ABBR. Analog Input Digital Input Analog Output Analog Output Analog Power Analog Ground Analog Bias Digital Power Digital Ground Digital Vias Bidirectional Port
0.25µm 20MHz~170MHz FSPLL
PLL2013X
CORE CONFIGURATION
PWRDN M[7:0]
M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7]
Pll2013x
P[5:0]
P[0] P[1] P[2] P[3] P[4] P[5] S[0] S[1]
FILTER
S[1:0]
PLL2013X
0.25µm 20MHz~170MHz FSPLL
RECOMMENDED OPERATING CONDITIONS
Characteristics Supply Voltage Differential Oscillator Frequency External Loop Filter Capacitance Operating Temperature Symbol VDD25A2-VDD25A1 Fosc Topr -0.1 14.318 +0.1 Unit
NOTE: strongly recommended that supply pins (VDD25A1, VDD25A2) powered same supply voltage avoid power latch-up.
ELECTRICAL CHARACTERISTICS
Characteristics Operating Voltage Digital Input Voltage High Digital Input Voltage Dynamic Current Power Down Current Symbol VDD25A2/VDD25A1
2.375
2.625
Unit
ELECTRICAL CHARACTERISTICS
Characteristics Crystal frequency Input Frequency Output Clock Frequency Output Clock Frequency Input Clock Duty Cycle Output Clock Duty Cycle 170MHz) Locking Time Jitter, Cycle Cycle Symbol FXTAL FOUT FVCO TJCC -150 14.318 +150 Unit
NOTE: strongly recommended that input signal generated glitch, consumer cannot help generating glitch, Consumer must carefully considerate specification.
0.25µm 20MHz~170MHz FSPLL
PLL2013X
FUNCTIONAL DESCRIPTION
circuit synchronizing output signal (generated VCO) with reference input signal frequency well phase. this application, includes following basic blocks. voltage-controlled oscillator generate output frequency divider divides input frequency divider divides output frequency divider divides output frequency phase frequency detector detects phase difference between reference frequency output frequency (after division) controls charge pump voltage. loop filter removes high frequency components charge pump voltage does smooth clean control values programmed 16bit digital data from external source. locked desired frequency. Fout 14.318MHz, m=M+8 p=P+2, s=2^S Digital data format: Main Divider M7,M6,M5,M4,M3,M2,M1,M0
NOTES: S[1] S[0] Output Frequency Scaler M[7] M[0] Frequency Divider P[5] P[0] Reference Frequency Input Divider
Divider P5,P4,P3,P2,P1,P0
Post Scaler S1,S0
OUTPUT FREQUENCY EQUATION TABLE
Frequency Equation: FOUT (P+2) Table Example Divider Ratio
(M+8)
(P+2)
NOTES: Don't zero, that 000000 00000000 proper range 1<=P<=62, 1<=M<=248 must selected considering stability output frequency range Please consult with application engineer select proper values
PLL2013X
0.25µm 20MHz~170MHz FSPLL
CORE EVALUATION GUIDE
embedded PLL, must consider test circuits embedded core multiple applications. Hence following requirements should satisfied. FILTER FOUT pins must bypassed external test. test (Below examples), needed control dividers M[7:0],P[5:0] S[1:0] -that generate multiple clocks. Registers used easy control divider values. sample bits 16-bit divider pins bypassed test using MUX.
2.5V Digital Power 2.5V Analog Power
VDD25A2 VSS25A2
VDD25A1 VSS25A1 VBBA
FOUT
PWRDN M[7:0] 16bit Resistor Block P[5:0] FILTER
pll2013x
S[1:0]
820pF
VSS25A1 Select
Test Pins Sample bits
Internal Divider Signal Line
NOTES 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED
0.25µm 20MHz~170MHz FSPLL
PLL2013X
CORE LAYOUT GUIDE
digital power(VDD25A2,VSS25A2) analog power(VDD25A1,VSS25A1) must dedicated only separated. dedicated VDD25A2 VSS25A2 allowed that least power consuming block shared with PLL. poar50_abb used FILTER that contains only production diodes with 50Ohm resistors. FOUT FILTER pins must placed from internal signals order avoid overlapping signal lines. blocks having large digital switching current must located away from core. FOUT pad, custom drive buffer pot8_abb buffer considering drive current.
OPTIONAL BLOCK USERS GUIDE
There crystal driver cell options PLL2013X core. crystal component used external clock source applied crystal component used external clock Buffer offered from Samsung's STD110 library recommended When implementing embedded block, following pins must bypassed externally testing locking function: Without Xtal-driver: VSS25A2,VBBA. crystal component Lock detector used, please contact application engineer When implementing embedded block, following pins must bypassed externally testing locking function: With Xtal-driver: VSS25A2,VBBA
FILTER
FOUT
VDD25A1
VSS25A1
Divide
Charge Pump
Post Scaler
Loop Filter Used picc_abb
PWRDN P[5:0]
VDD25A2
Main Divider
M[7:0] S[1:0]
VSS25A2
Glue Logic
VBBA
*Divider
Optional Test Pins
PLL2013X
0.25µm 20MHz~170MHz FSPLL
Figure example block without crystal component Lock Detector
0.25µm 20MHz~170MHz FSPLL
PLL2013X
FILTER LDOUT
FOUT
VDD25A1
VSS25A1
XTALIN
XTAL
Divide Charge Pump Post Scaler
XTAOUT
Loop Filter PWRDN P[5:0] Main Divider M[7:0] S[1:0]
VDD25A2
VSS25A2
Glue Logic
VBBA
*Divider
Optional Test Pins
Figure example block with dedicated XTAL-OSC Lock Detector
XTAL BUFFER CELL
PADA PADB
Figure Xtal Buffer Cell Symbol
XTAL Buffer cell supported MDL110 data book XTAL must located between PADA PADB. Enable pin(E) must HIGH normal operation. must connected VDD25A2 floated.
PLL2013X
0.25µm 20MHz~170MHz FSPLL
LOCK DETECTOR
Internal Signal
LOCK STATE
LDOUT
Detector
Internal DOWN Signal
Figure Lock Detector Block
built-in Lock Detector circuit will only work, When used conjunction with block output up/down signal. (Figure5). represent output lock detector timing diagram. (Figure Unlock State: Lock State: HIGH
UP/DOWN
LDOUT Unlock
Lock
Figure Lock Detector Timing Diagram
0.25µm 20MHz~170MHz FSPLL
PLL2013X
PACKAGE CONFIGURATION
TST1 TST2 TST3 LDOUT VSSA VSSA VDDA VDDA XTALIN XTALOUT FILTER PWRDN FOUT
VDDD VDDD VSSD VSSD TST5 TST4 VDDO VSSO
pll2013x
10uF 0.1uF
NOTE: connection
PLL2013X
0.25µm 20MHz~170MHz FSPLL
PACKAGE DESCRIPTION
Name VDDD VSSD PWRDN 35,36 33,34 19,20 Type AB/DB Digital ground Analog Digital Bias FSPLL clock power down PWRDN High, operating under this condition. isn't used this pin, tied VSSD. Pre-Divider Input Analog power supply Analog ground Xtal external input, Load Cap.: 25pF Customer don't Xtal, this Input Port. Xtal external output, Load Cap.: 25pF Customer don't Xtal, Float this pin. 20MHZ~170MHz clock output Lock detector output Pump connected FILTER. 820pF Capacitor connected between filter analog ground pin. Post scaler input 8bit main divider input Test Pin, Apply Analog vdda. Test Pin, Apply Ground Power Ground Description Digital power supply
P[0]~P[5] VDDA VSSA XTALIN
45~48,1,2 13,14 11,12
XTALOUT FOUT LDOUT FILTER S[0]~S[1] M[0]~M[7] TST1, TST3 TST2,TST4,TST5 VDDO VSSO
32,31 37~44 4,29,30
NOTES: TYPE denote power ground respectively. XTALIN, XTALOUT, LDOUT test SEC.
0.25µm 20MHz~170MHz FSPLL
PLL2013X
DESIGN CONSIDERATIONS
following design considerations apply: Jitter affected power noise, substrate noise.etc. increases when noise level increases. CMOS-level input reference clock recommend signal compatibility with circuit. Other levels such degrade tolerances. two, more PLLs requires special design considerations. Please consult your application engineer more information. following apply noise level, which minimized using good analog power ground isolation techniques system: wide traces POWER(VDD25A2/VSS25A2, VDD25A1/VSS25A1) connections core. Separate traces from chip's VDD25A2/VSS25A2,VDD25A1/VSS25A1 supplies. proper VDD25A2/VSS25A2,VDD25A1/VSS25A1 de-coupling. good power ground sources board. Power VBBA minimize substrate noise core should placed close possible dedicated loop filter analog Power ground pins. inadvisable locate noise-generating signals, such data buses high-current outputs, near cells. Other related signals should placed near have pre-defined placement restriction
PLL2013X
0.25µm 20MHz~170MHz FSPLL
PHANTOM CELL INFORMATION Pins core assigned externally(Package pins) internally(internal ports) depending design methods. term "external" implies that pins should assigned externally like power pins. term "internal/external" implies that these pins user dependant
VSS25A2:G VDD25A2:P VBBA:G VSS25A2:G VDD25A2:P VBBA:G
M[0] M[1] M[2] S[1] M[3] M[4] M[5] M[6] M[7] FOUT S[0]
P[5] P[4] P[3] P[2] P[1] P[0]
pll2013x
PWRDN
VDD25A1:P
VSS25A1:G
VBBA:G
FILTER
VBBA:G
VSS25A1:G
VDD25A1:P
Figure Phantom Cell Feature (Chip Size: um2)
PLL2013X
0.25µm 20MHz~170MHz FSPLL
Name VDD25A2
Usage External
Layout Guide Dedicated power/ground pins Power cuts required provide on-chip isolation between dedicated power/ground other power/ground good power ground source board
VSS25A2 VDD25A1 VSS25A1 VBBA FOUT
External External External External External External Neighboring circuitry pads proper jitter reference clock Neighboring circuitry pads Internal routing path should long, This will minimize loading effect. Fout signals should crossed signals should next digital signals. This will minimize capacitive coupling between signals.
Name FILTER
Usage External
Layout Guide Neighboring circuitry pads Ground Shielding external loop filter placed between analog power avoid stray coupling outside chip magnetic coupling bond wires Closely placed Loop Filter components
PWRDN M[7]~M[0] P[5]~P[0] S[1]~S[0]
Internal/External Internal/External Internal/External Internal/External
PLL2013X
0.25µm 20MHz~170MHz FSPLL
FEEDBACK REQUEST
appreciate your interest products. have further questions, please specify attached form. Thank very much. Parameter Supply Voltage Output frequency range Input frequency range Cycle Cycle Jitter Lock time Dynamic current Stand current Output clock duty ratio Long term jitter Output slew rate need XTAL driver buffer Core? need what's crystal frequency range? not, What's input frequency range? need lock detector? need cell SEC? need external test? What's main frequency frequency range? many FSPLLs your system? What's output loading? Could external/internal configurations required? Specially requested function list: Unit Remarks
0.25µm 20MHz~170MHz FSPLL
PLL2013X
Version
Date 98.12.1 99.5.10
Modified Items Original version published Change power name VDDA VDD25A1 VSSA VSS25A1 VDDD VDD25A2 VSSD VSS25A2 VBBA Font check Phantom Inform Layout Guide added. Pre-Divider Divisor ratio guide Current adjusted during power down mode. Power cell Guide added. Change file into Word format
Comments
Ver3.0
99.12.10 00.3.29 00.07.13 01.02.23 02.12.04
Refer Page
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