Multi-Chip Package MEMORY MEMORY 256M Bit(16Mx16) Nand Flash

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Multi-Chip Package MEMORY MEMORY 256M Bit(16Mx16) Nand Flash

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KAA00B209M-TGxx
Multi-Chip Package MEMORY
MEMORY
256M Bit(16Mx16) Nand Flash/32M Bit(2Mx16) UtRAM/128M Bit(2Mx16x4Banks) MobileSDRAM
Revision History
Revision History
Initial issue. <Mobile SDRAM> Revised errorta Inserted description mode external Revised tRDL(min.) clocks 15ns Revised Advance Preliminary <NAND Flash> Revised tWP=25ns less than 10ns, must minimum 35ns,
otherwise, minimum 25ns
Draft Date
January 2002 January 2002
Remark
Advance Advance
March 2002
Preliminary
<Mobile SDRAM> Changed from 0.9xVDDQ 0.8xVDDQ from 0.95xVDDQ 0.9xVDDQ Changed SDRAM Input Pulse Level from 0.95xVDDQ 0.9xVDDQ. Changed tDAL from 2CLK+tRP tRDL+tRP. Changed tARFC from 14CLK 105ns Changed tSRFX from 16CLK 120ns Inserted Functional Block Diagram <Mobile SDRAM> Inserted Standby Current Deep Power Down Mode (IccD=20uA) <NAND SDRAM> Changed Vcc/Vccq from 1.85V 0.15V 1.8V 0.15V <NAND> Revised Flash Operation Table(During Read) <Mobile SDRAM> Inserted 105MHz Condition Changed from 3.5ns 66MHz Erased external TCSR addition internal TCSR. Changed Current specification. Changed from 0.9xVccq Vccq-0.2V. <UtRAM> Inserted Standby Current(ISB2u) Comment <NAND Mobile SDRAM> Changed Vcc/Vccq from 1.8V 0.15V 1.85V 0.15V April 2002 Preliminary
August 2002
Final
October 2002
Final
Note more detailed features specifications including FAQ, please refer Samsung's site. attached datasheets prepared approved SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications. SAMSUNG Electronics will evaluate reply your requests questions about device. have questions, please contact SAMSUNG branch office near you. -1Revision March 2003
KAA00B209M-TGxx
Multi-Chip Package MEMORY
MEMORY
256M Bit(16Mx16) Nand Flash/32M Bit(2Mx16) UtRAM/128M Bit(2Mx16x4Banks) MobileSDRAM
Revision History
Revision History
<Mobile SDRAM> Revised errate Unit tARFC tSRFX: Addition Timing Diagram Addition Internal TCSR Removal External TCSR
Draft Date
February 2003
Remark
Final
Changed part number. KAA00B206M KAA00B209M
March 2003
Final
Note more detailed features specifications including FAQ, please refer Samsung's site. attached datasheets prepared approved SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications. SAMSUNG Electronics will evaluate reply your requests questions about device. have questions, please contact SAMSUNG branch office near you. -2Revision March 2003
KAA00B209M-TGxx
Multi-Chip Package MEMORY
MEMORY
256M (16Mx16) Nand Flash/32M (2Mx16) UtRAM/128M (2Mx16x4Banks) Mobile SDRAM
FEATURES
<Common> Power Supply Voltage NAND, SDRAM 1.7~2.0V UtRAM 2.7~3.1V Data Output Power 1.7~2.0V Operating Temperature -25°C 85°C Package 127-ball TBGA Type 10.5x12mm, 0.8mm pitch <NAND> Organization Memory Cell Array (16M 512K)bit 16bit Data Register (256 8)bit x16bit Automatic Program Erase Page Program (256 8)Word Block Erase 256)Word Page Read Operation Page Size (256 8)Word Random Access 10µs(Max.) Serial Page Access 50ns(Min.) Fast Write Cycle Time Program time 200µs(Typ.) Block Erase Time 2ms(Typ.) Command/Address/Data Multiplexed Port Hardware Data Protection Program/Erase Lockout During Power Transitions Reliable CMOS Floating-Gate Technology Endurance 100K Program/Erase Cycles Data Retention Years Command Register Operation Intelligent Copy-Back <UtRAM> Process Technology CMOS Organization Read Access Time 90ns, 100ns Three State Outputs Compatible with Power SRAM Deep Power Down Memory cell data holds invalid <SDRAM> 1.8V power supply. LVCMOS compatible with multiplexed address. Four banks operation. Frequency 105MHz, 66MHz cycle with address programs. latency Burst length Full page). Burst type (Sequential Interleave). Special option Mobile application. PASR(Partial Array Self Refresh) with EMRS cycle. Internal TCSR(Temperature Compensated Self Refresh) DS(Driver Strength Control) inputs sampled positive going edge system clock. Burst read single-bit write operation. Special Function Support. Mode External masking. Auto refresh. 64ms refresh period cycle).
GENERAL DESCRIPTION
KAA00B209M Multi Chip Package Memory which combines 256Mbit Nand Flash Memory, 32Mbit Unit Transistor CMOS 128Mbit synchronous high data rate Dynamic RAM. 256Mbit NAND Flash memory organized bits 32Mbit UtRAM organized bits 128Mbit SDRAM organized bits banks. 256Mbit NAND Flash, 264-word page program typically achieved within 200us 8K-word block erase typically achieved within 2ms. serial read operation, byte read 50ns. pins serve ports address data input/output well command inputs. Even write-intensive systems take advantage FLASHs extended reliability 100K program/erase cycles with real time mapping-out algorithm. These algorithms have been implemented many mass storage applications. 128Mbit SDRAM, Synchronous design allows precise cycle control with system clock, transactions possible every clock cycle. Range operating frequencies, programmable burst length programmable latencies allow same device useful variety high bandwidth, high performance memory system applications. KAA00B209M suitable data memory mobile communication system reduce only mount area also power consumption. This device available 127-ball TBGA Type.
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KAA00B209M-TGxx
CONFIGURATION
MEMORY
Vccu
Vccn
R/Bn
Vccq
DQ9d
DQ11d
DQ8d
DQ10d
DQ14d
DQ13d
DQ15d
DQ12d
LDQM
UDQM
DQ1d
DQ0d
Vccq
A11d
DQ5d
DQ4d
DQ3d
DQ2d
A10d
DQ7d
DQ6d
DQ10
DQ14
Vccq
DQ11
DQ12
DQ15
Vccqn
Vccn
Vccqu
Vccu
DQ13
TBGA: View (Ball Down)
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KAA00B209M-TGxx
DESCRIPTION
Name A0~A20 A0d~A11d BA0~BA1 DQ0~DQ15 DQ0d~DQ15d R/Bn Function Address Input(UtRAM) Address Input(SDRAM) Bank Address Input(SDRAM) Data Input/Out Put(UtRAM, NAND) Data Input/Out Put(SDRAM) Chip Enable(NAND) Read Enable(NAND) Write Protection(NAND) Address Latch Enable(NAND) Command Latch Enable(NAND) Read/Busy OutPut(NAND) Write Enable(NAND, UtRAM) Chip Enable(UtRAM) Deep Power Down(UtRAM) Upper Byte (UtRAM) Byte(UtRAM) Output Enable(UtRAM) System Clock(SDRAM) Name LDQM UDQM Vccn Vccu Vccqn Vccqu Vccq
MEMORY
Function Chip Enable(SDRAM) Clock Enable(SDRAM) Address Strobe(SDRAM) Column Address Strobe(SDRAM) Write Enable(SDRAM) Data Mask(SDRAM) Upper Data Mask(SDRAM) Deep Power Down(SDRAM) Power Supply(NAND) Power Supply(UtRAM) Power Supply(SDRAM) Data Power(NAND) Data Power(UtRAM) Data Power(SDRAM) Ground Connection
ORDERING INFORMATION
Samsung Memory(3chips) Device Type NAND UtRAM SDRAM
SDRAM Speed 15ns 10ns UtRAM Speed 90ns 100ns NAND Flash Speed 50ns Package TBGA Version Generation DRAM Interface, Density, Voltage, Organization SDR, 128M, 1.85V/1.85V, X16,T Internal TCSR(Icc6:300uA(@85'C)
Flash Density, Voltage, Organization, Bank Size, Boot Block None NAND Flash Density, Voltage, Organization 256M, 1.85V/1.85V, UtRAM Density, Voltage, Organization 32M, 2.9V/1.85V, SRAM Density, Voltage, Organization None
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KAA00B209M-TGxx
FUNCTIONAL BLOCK DIAGRAM
Control Output Buffer
MEMORY
BA0~BA1
Address Register
Bank Select
Data Input Register
Buffer Refresh Counter
Decoder
Sense
DQ15
Timing Register
Column Decoder
LRAS
LCBR
Col. Buffer
LDQM UDQM
Latency Burst Length
Programming Register
VccQ/Vcc
VccF R/BF
X-Buffers Latches Decoders Y-Buffers Latches Decoders
256M+8M NAND flash ARRAY (256 8)Word 65536 page Register Y-Gating
DQ15
Command Register Buffers Latches Control Logic High Voltage Generator
Global Buffers
Output Driver
DQ15
gen. Precharge circuit.
VccU VccQU
Control logic Data control Circuit Column select select
UtRAM Main Cell Array
(2Mb x16)
DQ15
Bottom Boot Block
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KAA00B209M-TGxx
MEMORY
256Mb(16M NAND Flash
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KAA00B209M-TGxx
Figure NAND Flash(x16) ARRAY ORGANIZATION
MEMORY
Block Pages 256) Word
Pages (=2,048 Blocks)
Page Register (=256 Words)
Page Word Block Word Pages 256) Word Device 264Words 32Pages 2048 Blocks Mbits Word
256Word
Page Register
Word
Word
Cycle Cycle Cycle
I/O8
Column Address Address (Page Address)
NOTE Column Address Starting Address Register. must "Low".
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KAA00B209M-TGxx
PRODUCT INTRODUCTION
MEMORY
This device 264Mbit(276,824,064 bit) memory organized 65,536 rows(pages) columns. Spare eight columns located from column address 256~263. 264-Word data register connected memory cell arrays accommodating data transfer between buffers memory during page read page program operations. memory array made cells that serially connected form NAND structure. Each cells resides different page. block consists pages formed NAND structures, totaling 8448 NAND structures cells. array organization shown Figure1. program read operations executed page basis, while erase operation executed block basis. memory array consists 2048 separately erasable 8K-Word blocks. indicates that erase operation prohibited this device. This device addresses multiplexed into lower I/O`s. This device allows sixteen wide data transport into page registers. This scheme dramatically reduces counts while providing high performance allows systems upgrades future densities maintaining consistency system board design. Command, address data written through I/Os bringing while low. Data latched rising edge Command Latch Enable(CLE) Address Latch Enable(ALE) used multiplex command address respectively, pins. Some commands require cycle. example, Reset command, Read command, Status Read command, require just cycle bus. Some other commands like Page Program Copy-back Program Block Erase, require cycles: cycle setup other cycle execution. 16M-word physical space requires addresses, thereby requiring three cycles word-level addressing: column address, address high address, that order. Page Read Page Program need same three address cycles following required command input. Block Erase operation, however, only address cycles used. Device operations selected writing specific commands into command register. Table defines specific commands this device. device includes block sized OTP(One Time Programmable), which used increase system security provide identification capabilities. Detailed information obtained contact with Samsung.
Table COMMAND SETS
Function Read Read Read Reset Page Program Copy-Back Program Block Erase Read Status 1st. Cycle 2nd. Cycle Acceptable Command during Busy
Caution undefined command inputs prohibited except above command Table
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KAA00B209M-TGxx
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol VIN/OUT Voltage relative VCCQ Temperature Under Bias Storage Temperature Short Circuit Current TBIAS TSTG
MEMORY
Rating -0.6 2.45 -0.2 2.45 -0.2 2.45 +125 +150
Unit
NOTE Minimum voltage -0.6V input/output pins. During transitions, this level undershoot -2.0V periods <30ns. Maximum voltage input/output pins VCC,+0.3V which, during transitions, overshoot VCC+2.0V periods <20ns. Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference GND, TA=-25 85°C)
Parameter Supply Voltage Supply Voltage Supply Voltage Symbo VCCQ 1.65 1.65 Typ. 1.95 1.95 Unit
OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter Operating Current Sequential Read Program Erase Stand-by Current(TTL) Stand-by Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage Input Voltage, inputs Output High Voltage Level Output Voltage Level Output Current(R/B) Symbol ICC1 ICC2 ICC3 ISB1 ISB2 Except pins IOL(R/B) IOH=-100µA IOL=100uA VOL=0.1V VCC-0.4 -0.3 VCCQ-0.1 Test Conditions tRC=50ns, CE=VIL IOUT=0mA CE=VIH, WP=0V/VCC CE=VCC-0.2, WP=0V/VCC VIN=0 Vcc(max) VOUT=0 Vcc(max) pins VCCQ-0.4 VCCQ+0.3 VCC+0.3 Unit
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KAA00B209M-TGxx
VALID BLOCK
Parameter Valid Block Number Symbol 2013 Typ.
MEMORY
2048 Unit Blocks
NOTE This device include invalid blocks when first shipped. Additional invalid blocks develop while being used. number valid blocks presented with both cases invalid blocks considered. Invalid blocks defined blocks that contain more bits. erase program factory-marked blocks. Refer attached technical notes appropriate management invalid blocks. block, which placed block address, fully guaranteed valid block, does require Error Correction. blocks good upon shipping.
TEST CONDITION
Vcc=1.65V~1.95V TA=-25 85°C unless otherwise noted) Parameter Input Pulse Levels Input Rise Fall Times Input Output Timing Levels Output Load (VccQ:1.8V +/-10%) Value VccQ VccQ/2 GATE CL=30pF
CAPACITANCE(TA=25°C, VCC=1.8V, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance Symbol CI/O Test Condition VIL=0V VIN=0V Unit
NOTE Capacitance periodically sampled 100% tested.
MODE SELECTION
Data Input Data Output During Program(Busy) During Erase(Busy) Write Protect Write Mode Read Mode
Mode Command Input Address Input(3clock) Command Input Address Input(3clock)
0V/VCC(2) Stand-by
NOTE VIH. should biased CMOS high CMOS standby.
Program/Erase Characteristics
Parameter Program Time Number Partial Program Cycles Same Page Block Erase Time Main Array Spare Array Symbol tPROG tBERS Unit cycles cycles
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KAA00B209M-TGxx
Timing Characteristics Command Address Data Input
Parameter Set-up Time Hold Time Setup Time Hold Time Pulse Width Setup Time Hold Time Data Setup Time Data Hold Time Write Cycle Time High Hold Time Symbol tCLS tCLH tALS tALH
MEMORY
.Unit
NOTE less than 10ns, must minimum 35ns, otherwise, minimum 25ns.
Characteristics Operation
Parameter Data Transfer from Cell Register Delay Delay Ready Pulse Width High Busy Read Cycle Time Access Time Access Time High Output Hi-Z High Output Hi-Z High Output hold High Hold Time Output Hi-Z High Device Resetting Time(Read/Program/Erase) Symbol tCLR tCEA tREA tRHZ tCHZ tREH tWHR tRST 5/10/500
Unit
NOTE reset command(FFh) written Ready state, device goes into Busy maximum 5us.
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KAA00B209M-TGxx
NAND Flash Technical Notes Invalid Block(s)
MEMORY
Invalid blocks defined blocks that contain more invalid bits whose reliability guaranteed Samsung. information regarding invalid block(s) called invalid block information. Devices with invalid block(s) have same quality level devices with valid blocks have same characteristics. invalid block(s) does affect performance valid block(s) because isolated from line common source line select transistor. system design must able mask invalid block(s) address mapping. block, which placed block address, fully guaranteed valid block, does require Error Correction.
Identifying Invalid Block(s)
device locations erased(FFh) except locations where invalid block(s) information written prior shipping. invalid block(s) status defined word spare area. Samsung makes sure that either page every invalid block non-FFFFh data column address 261. Since invalid block information also erasable most cases, impossible recover information once been erased. Therefore, system must able recognize invalid block(s) based original invalid block information create invalid block table following suggested flow chart(Figure intentional erasure original invalid block information prohibited.
Start
Block Address
Increment Block Address
Create update) Invalid Block(s) Table
Check "FFh"
Check "FFh" column address page block
Last Block
Figure Flow chart create invalid block table.
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KAA00B209M-TGxx
NAND Flash Technical Notes(Continued) Error write read operation
MEMORY
Over life time, additional invalid blocks develop with NAND Flash memory. Refer qualification report actual data.The following possible failure modes should considered implement highly reliable system. case status read failure after erase program, block replacement should done. Because program status fail during page program does affect data other pages same block, block replacement executed with page-sized buffer finding erased empty block reprogramming current target data copying rest replaced block. improve efficiency memory space, recommended that read verification failure single error reclaimed without block replacement. said additional block failure rate does include those reclaimed blocks. Failure Mode Erase Failure Write Program Failure Single Failure Detection Countermeasure sequence Status Read after Erase Block Replacement Status Read after Program Block Replacement Read back Verify after Program) Block Replacement Correction Verify Correction
Read
Error Correcting Code Hamming Code etc. Example) 1bit correction 2bit detection
Program Flow Chart
used, this verification operation needed. Start Write
Write
Write Address
Write Address
Write Data
Wait Time
Write
Verify Data
Program Error
Read Status Register Program Completed
Program Error
program operation results error, block including page error copy target data another block.
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KAA00B209M-TGxx
NAND Flash Technical Notes(Continued) Erase Flow Chart
Start Write Write Block Address Write Read Status Register
MEMORY
Read Flow Chart
Start Write Write Address Read Data Generation
Erase Completed
Reclaim Error
Verify Page Read Completed
Erase Error
erase operation results error, failing block replace with another block.
Block Replacement
(n-1)th (page)
Block error occurs. Buffer memory controller. Block
(n-1)th (page)
Step1 When error happens page Block during erase program operation. Step2 Copy page data Block buffer memory page another free block. (Block 'B') Step3 Then, copy data (n-1)th page same location Block 'B'. Step4 further erase Block creating 'invalid Block' table other appropriate scheme.
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KAA00B209M-TGxx
Pointer Operation
MEMORY
Samsung NAND Flash address pointer commands substitute most significant column address. '00h' command sets pointer area(0~255word), '50h' command sets pointer area(256~263word). With these commands, starting column address whole page(0~263word). '00h' '50h' sustained until another address pointer command inputted. program data starting from area, '00h' '50h' command must inputted before '80h' command written. complete read operation prior '80h' command necessary.
area (00h plane)
area (50h plane) Word
Table Destination pointer Command Pointer position word word Area main array(A) spare array(B)
Word
Internal Page Register
Pointer select command (00h, 50h)
Pointer
Figure Block Diagram Pointer Operation
Command input sequence programming area
address pointer area(0~255), sustained Address Data input Address Data input
'A','B' area programmed. depends many data inputted.
'00h' command omitted.
Command input sequence programming area
address pointer area(256~263), sustained Address Data input Address Data input
Only area programmed.
'50h' command omitted.
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KAA00B209M-TGxx
System Interface Using don't-care.
MEMORY
easier system interface, inactive during data-loading sequential data-reading shown below. internal 264word page registers utilized seperate buffers this operation system design gets more flexible. addition, voice audio applications which slow cycle time order u-seconds, de-activating during data-loading reading would provide significant savings power consumption.
Figure Program Operation with don't-care.
don't-care
I/Ox
Start Add.(3Cycle)
Data Input
Data Input
tCEA
tREA I/O0~15
Figure Read Operation with don't-care.
don't-care
I/Ox
Start Add.(3Cycle)
Data Output(sequential)
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KAA00B209M-TGxx
Command Latch Cycle
MEMORY
tCLS tCLH
tALS I/Ox
tALH
Command
Address Latch Cycle
tCLS
tALS I/Ox tALH tALS
tALH tALS
tALH
AO~A7
A9~A16
A17~A24
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KAA00B209M-TGxx
Input Data Latch Cycle
MEMORY
tCLH
tALS
I/Ox
Sequential Cycle after Read(CLE=L, WE=H, ALE=L)
tREH tCHZ*
tRHZ*
tREA
tREA
tREA
tRHZ* Dout
I/Ox
Dout
Dout
NOTE Transition measured ±200mV from steady state voltage with load. This parameter sampled 100% tested.
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KAA00B209M-TGxx
Status Read Cycle
MEMORY
tCLR tCLS tWHR I/Ox tREA tRHZ Status Output tCEA tCHZ tCLH
READ1 OPERATION(READ PAGE)
Address
tCHZ
tRHZ
I/Ox
Dout Dout Dout Dout
Dout
Column Address
Page(Row) Address Busy
R/Bn
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KAA00B209M-TGxx
READ1 OPERATION (INTERCEPTED
MEMORY
Address I/Ox
Col. Add1 Add2
tCHZ
Dout
Dout
Dout
Dout
Column Address
Page(Row) Address Busy
READ2 OPERATION (READ PAGE)
I/Ox
Col.
Add1
Add2
Dout 256+M
Dout 256+M+1
Dout
Address
A0~A2 Valid Address A3~A7
Selected
Start address
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KAA00B209M-TGxx
PAGE PROGRAM OPERATION
MEMORY
tPROG
Address
I/Ox
Col.
Add1
Add2
Sequential Data Column Input Command Address
Page(Row) Address
Data Serial Input
Program Command
Read Status Command
I/O0
tPROG
I/O0=0 Successful Program I/O0=1 Error Program
COPY-BACK PROGRAM OPERATION
I/Ox
Col.
Add1
Add2
A0~A7 A9~A16 A17~A24 Address
Read Status Command
I/O0
Column Page(Row) Address Address
Program Column Page(Row)
CommandAddress
Busy
Busy
I/O0=0 Successful Program I/O0=1 Error Program
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KAA00B209M-TGxx
BLOCK ERASE OPERATION(ERASE BLOCK)
MEMORY
tBERS
I/Ox
A9~A16
A17~A24
Page(Row) Address
Auto Block Erase Setup Command Erase Command
Busy
Read Status Command
I/O0=0 Successful Erase I/O0=1 Error Erase
MANUFACTURE DEVICE READ OPERATION
tREA I/Ox
Read Command Address. 1cycle Maker Code xx45h Device Code
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KAA00B209M-TGxx
DEVICE OPERATION PAGE READ
MEMORY
Upon initial device power device defaults Read1 mode. This operation also initiated writing command register along with three address cycles. Once command latched, does need written following page read operation. types operations available random read, serial page read. random read mode enabled when page address changed. words data within selected page transferred data registers less than 10µs(tR). system controller detect completion this data transfer(tR) analyzing output pin. Once data page loaded into registers, they read 50ns cycle time sequentially pulsing High transitions clock output data starting from selected column address last column address[column 255/ depending state input pin]. Read1 Read2 commands work like pointer either main area spare area. spare area ~263 words selectively accessed writing Read2 command with input low. Addresses A0~A2 starting address spare area while addresses A3~A7 must low. Read1 command needed move pointer back main area. Figures6,7 show typical sequence timings each read operation.
Figure Read1 Operation
I/Ox
Start Add.(3Cycle) (00h Command) Data Output(Sequential)
Main array
Data Field
Spare Field
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KAA00B209M-TGxx
Figure Read2 Operation
MEMORY
I/Ox
Start Add.(3Cycle) Data Output(Sequential) Spare Field
Main array
Data Field
Spare Field
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KAA00B209M-TGxx
PAGE PROGRAM
MEMORY
device programmed basically page basis, does allow multiple partial page programing word consecutive words 264, single page program cycle. number consecutive partial page programming operation within same page without intervening erase operation should exceed main array spare array. addressing done random order block. page program cycle consists serial data loading period which words data loaded into page register, followed non-volatile programming period where loaded data programmed into appropriate cell. About pointer operation, please refer attached technical notes. serial data loading period begins inputting Serial Data Input command(80h), followed three cycle address input then serial data loading. words other than those programmed need loaded.The Page Program confirm command(10h) initiates programming process. Writing alone without previously entering serial data will initiate programming process. internal write controller automatically executes algorithms timings necessary program verify, thereby freeing system controller other tasks. Once program process starts, Read Status Register command entered, with low, read status register. system controller detect completion program cycle monitoring output, Status bit(I/O Status Register. Only Read Status command Reset command valid while programming progress. When Page Program complete, Write Status Bit(I/O checked(Figure internal write verify detects only errors "1"s that successfully programmed "0"s. command register remains Read Status command mode until another valid command written command register.
Figure Program Operation
tPROG I/Ox
Address Data Input
I/O0
Pass
Fail
COPY-BACK PROGRAM
copy-back program configured quickly efficiently rewrite data stored page within array another page within same array without utilizing external memory. Since time-consuming sequently-reading re-loading cycles removed, system performance improved. benefit especially obvious when portion block updated rest block also need copied newly assigned free block. operation performing copy-back sequential execution page-read without burst-reading cycle copying-program with address destination page. normal read operation with "00h" command with address source page moves whole 264words data into internal buffer. soon Flash returns Ready state, copy-back programming command "8Ah" given with three address cycles target page followed. data stored internal buffer then programmed directly into memory cells destination page. Once Copy-Back Program finished, additional partial page programming into copied pages prohibited before erase. Since memory array internally partitioned into different planes, copy-back program allowed only within same memory plane. Thus, A14, plane address, source destination page address must same.
Figure Copy-Back Program Operation
I/Ox tPROG
Add.(3Cycles) Source Address
Add.(3Cycles) Destination Address
I/O0
Pass
Fail
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KAA00B209M-TGxx
BLOCK ERASE
MEMORY
Erase operation done block basis. Block address loading accomplished cycles initiated Erase Setup command(60h). Only address valid while ignored. Erase Confirm command(D0h) following block address loading initiates internal erasing process. This two-step sequence setup followed execution command ensures that memory contents accidentally erased external noise conditions. rising edge after erase confirm command input, internal write controller handles erase erase-verify. When erase operation completed, Write Status Bit(I/O checked. Figure details sequence.
Figure Block Erase Operation
tBERS
I/Ox
Address Input(2Cycle) Block Add.
I/O0
Pass
Fail
READ STATUS
device contains Status Register which read find whether program erase operation completed, whether program erase operation completed successfully. After writing command command register, read cycle outputs content Status Register pins falling edge whichever occurs last. This line control allows system poll progress each device multiple memory connections even when pins common-wired. does need toggled updated status. Refer table specific Status Register definitions. command register remains Status Read mode until further commands issued Therefore, status register read during random read cycle, read command(00h 50h) should given before sequential page read cycle.
Table3. Read Status Register Definition
8~15 Device Operation Write Protect Reserved Future Status Program Erase Definition Successful Program Erase Error Program Erase Busy Protected Don't care Ready Protected
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KAA00B209M-TGxx
READ
MEMORY
device contains product identification mode, initiated writing command register, followed address input 00h. read cycles sequentially output manufacture code(ECh), device code respectively. command register remains Read mode until further commands issued Figure shows operation sequence.
Figure Read Operation
tCEA I/Ox tWHR
Address. 1cycle
tREA
Maker code
xx45h Device code
RESET
device offers reset feature, executed writing command register. When device Busy state during random read, program erase mode, reset operation will abort these operations. contents memory cells being altered longer valid, data will partially programmed erased. command register cleared wait next command, Status Register cleared value when high. Refer table device status after reset operation. device already reset state reset command will accepted command register. transitions tRST after Reset command written. Refer Figure below.
Figure RESET Operation
tRST I/Ox
Table4. Device Status
After Power-up Operation Mode Read After Reset Waiting next command
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KAA00B209M-TGxx
READY/BUSY
MEMORY
device output that provides hardware method indicating completion page program, erase random read completion. normally high transitions after program erase command written command register random read started after address loading. returns high when internal controller finished operation. open-drain driver thereby allowing more outputs Or-tied. Because pull-up resistor value related tr(R/B) current drain during busy(ibusy) appropriate value obtained with following reference chart. value determined following guidance.
Vccqn
ibusy
Ready Vccqn R/Bn open drain output 0.4V Busy Vccqn-0.4V
Device
Figure ibusy
1.8V, 25°C 30pF
tr,tf
200n
0.85 0.57 0.43
100n
Rp(ohm)
value guidance
Vccq(Max.) VOL(Max.) 1.9V
Rp(min, 1.8V part)
where input currents devices tied pin. Rp(max) determined maximum permissible limit
Ibusy
300n
Ibusy
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KAA00B209M-TGxx
Data Protection Power sequence
MEMORY
device designed offer protection from involuntary program/erase during power-transitions. internal voltage detector disables functions whenever below about 1.3V. provides hardware protection recommended kept during power-up power-down recovery time minimum 10µs required before internal circuit gets ready command sequences shown Figure step command sequence program/erase provides additional software protection.
Figure Waveforms Power Transition
1.5V High
1.5V
10µs
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KAA00B209M-TGxx
MEMORY
32Mb(2M UtRAM
Revision March 2003
KAA00B209M-TGxx
FUNCTIONAL DESCRIPTION
MEMORY
I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Deep Power Down Standby Active Active Active Active Active Active Active Active
means dont care.(Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Voltage VDDQ supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VDDQ TSTG Ratings -0.2 VDD+0.3V -0.2 3.6V -0.2 2.5V Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted used under recommended operating condition. Exposure absolute maximum rating conditions longer than second affect reliability.
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KAA00B209M-TGxx
STANDBY MODE STATE MACHINES
CS=VIH ZZ=VIH Power Initial State (Wait 200µs) CS=VIL, or/and LB=VIL ZZ=VIH CS=VIH ZZ=VIH ZZ=VIL Deep Power Down Mode CS=VIH, ZZ=VIH Standby Mode
MEMORY
Active
ZZ=VIL
STANDBY MODE CHARACTERISTIC
Power Mode Standby Deep Power Down Memory Cell Data Valid Invaild Standby Current(µA) Wait Time(µs)
RECOMMENDED OPERATING CONDITIONS1)
Item Power supply voltage power supply voltage Ground Input high voltage Input voltage
TA=-25 85°C, otherwise specified. Overshoot: VDDQ+1.0V case pulse width 20ns. Undershoot: -1.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
Symbol VDDQ
-0.23)
1.85
VDDQ+0.22)
Unit
CAPACITANCE1)(f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested.
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Average operating current
Symbol
Test Conditions VIN=Vss CS=VIH, ZZ=VIH, OE=VIH WE=VIL, VIO=Vss VDDQ Cycle time=1µs, 100% duty, IIO=0mA, CS0.2V, ZZVDDQ-0.2V, VIN0.2V VINVDDQ-0.2V
Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH, VIN=VIL
Typ1)
Unit
ICC1 ICC2
Output voltage Output high voltage Standby Current(CMOS) Deep Power Down
ISB1 ISBD
IOL=2.1mA IOH=-1.0mA CSVDDQ-0.2V, ZZVDDQ-0.2V, Other inputs=Vss VDDQ ZZ0.2V, Other inputs=Vss VDDQ
Typical values tested VDD=2.9V, TA=25°C guaranteed.
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KAA00B209M-TGxx
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Test Input/Output Reference)
Input pulse level: VDDQ-0.2V Input rising falling time: Input output reference voltage: VDDQ/2 Output load: CL=50pF
MEMORY
CHARACTERISTICS(VDD=2.7~3.1V, VDDQ=1.7~2.0V, TA=-25 85°C)
Speed Bins Parameter List Symbol Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Access Time Read Chip Select Low-Z Output Enable Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Write Cycle Time Chip Select Write Address Set-up Time Address Valid Write Valid Write Write Write Pulse Width Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z tBLZ tOLZ tBHZ tOHZ tWHZ
90ns
100ns
Units
tWP(min)=90ns continuous write operation over times.(Only case controlled write operation)
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KAA00B209M-TGxx
UtRAM TIMING DIAGRAMS
MEMORY
TIMING WAVEFORM READ CYCLE(1)(Address Controlled, CS=OE=VIL, ZZ=WE=VIH, or/and LB=VIL)
Address Data Previous Data Valid Data Valid
TIMING WAVEFORM READ CYCLE(2)(ZZ=WE=VIH)
tRC1 Address tRC2 tBHZ tOLZ tBLZ Data
High-Z
tOHZ Data Valid
(READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection. minimum read cycle(tRC) determined later tRC1 tRC2. tOE(max) only when becomes enable after tAA(max).
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KAA00B209M-TGxx
TIMING WAVEFORM WRITE CYCLE(1)(WE Controlled, ZZ=VIH)
Address tCW(2) tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid tWR(4)
MEMORY
High-Z
TIMING WAVEFORM WRITE CYCLE(2)(CS Controlled, ZZ=VIH)
Address
tAS(3) tCW(2) tWR(4)
tWP(1) Data Data Valid
Data
High-Z
High-Z
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KAA00B209M-TGxx
TIMING WAVEFORM WRITE CYCLE(3)(UB, Controlled, ZZ=VIH)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
MEMORY
Data
High-Z
High-Z
(WRITE CYCLE) write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends going high.
TIMING WAVEFORM DEEP POWER DOWN MODE
Read Operation Twice Stay High during 300µs 200µs
Normal Operation MODE
0.5µs Suspend
Wake Normal Operation
Deep Power Down Mode
(DEEP POWER DOWN MODE) When toggle low, device gets into Deep Power Down mode after 0.5µs suspend period. return normal operation, device needs Wake period. Wake sequence just same Power sequence shown next page
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KAA00B209M-TGxx
TIMING WAVEFORM POWER UP(1)
MEMORY
Read Operation Twice 200µs
Vcc(Min) Vccq(Min) Vccq
(POWER UP(1)) After reaches VDD(Min.) following power application, wait 200µs with high then toggle commit Read Operation least twice. Then into normal operation. Read operation should executed toggling low. read operation must satisfy spec. described page (Read cycle (1), (2)). should kept high during whole power sequence.
TIMING WAVEFORM POWER UP(2)(No Dummy Cycle)
200µs 300µs
Vcc(Min) Vccq(Min) Vccq
(POWER UP(2)) After reaches VDD(Min.) following power application, wait 200µs wait another 300µs with high don't want commit dummy read cycle. After total 500µs wait, toggle low, then into normal mode. should kept high during whole power sequence.
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KAA00B209M-TGxx
TECHNICAL NOTE
INTRODUCTION
UtRAM based single-transistor DRAM cells. with other DRAM, data these cells must periodically refreshed prevent data loss. What makes UtRAM unique that offers true SRAM style interface that hides refresh operations from memory controller.
MEMORY
UtRAM USAGE TIMING
DESIGN ACHIEVES OPERATIONS SRAM SPECIFIC
START WITH DRAM TECHNOLOGY
point UtRAM high speed power. This high speed comes from many small blocks such 32Kbits each create UtRAM arrays. small blocks have short word lines thus with little capacitance eliminating major factor operating current dissipation conventional DRAM blocks. Each independent macro-cell UtRAM device consists number these blocks. Each chip more macro. address decoding logic also fast. UtRAM performs complete read operation every tRC, UtRAM needs power sequence like DRAM. Power Sequence Diagram Apply power. Maintain stable power minium 200µs with CSu=high. Issue read operation least times.
UtRAM designed work just like SRAM without waits other overhead precharging refreshing internal DRAM cells. SAMSUNG Electronics(SAMSUNG) hides these operations inside with advanced design technology those seen from outside. Precharging takes place during every access, overlapped between cycle decoding portion next cycle. Hiding refresh more difficult. Every every block must refreshed least once during refresh interval prevent data loss. SAMSUNG provides internal refresh controller devices. When accesses within refresh interval directed macro-cell, happen signal processing applications, more sophisticated approach required hide refresh. pseudo SRAM sometimes used these applications, which requires memory controller that hold accesses when refresh operation needed. SAMSUNG's unique qualitative advantage over these parts(in addition quantitative improvements access speed power consumption) that UtRAM never need hold accesses, indeed hold signal. circuitry that gives SAMSUNG this advantage fairly simple previously been disclosed.
CSu=VIH Power Initial State (Wait 200µs)
CSu=VIL, or/and LBu=VIL ZZu=VIH Active
AVOID TIMING
Following figures show abnormal timing which supported UtRAM solution. your system timing which sustains invalid states over read mode like Figure there some guide lines proper operation UtRAM. When your system multiple invalid address signals shorter than timing shown Figure UtRAM needs normal read timing(tRC) during that cycle(Figure needs toggle once 'high' about 'tRC'(Figure 20).
Read Operation(2 times)
Figure
Over
Less than
Address Figure
Over
read operation every
Address
Revision March 2003
KAA00B209M-TGxx
Figure toggle high every
Over
MEMORY
Address Write operation similar restriction Read operation. your system timing which sustains invalid states over write mode continuous write signals with length Min. over like Figure must toggle once high Figure
Over
make stay high least every toggle once high about tRC.
Address
Figure
toggle high make stay high least every
Over
Address
Figure
Over
toggle high every
Address
Revision March 2003
KAA00B209M-TGxx
MEMORY
128Mb(8M Mobile SDRAM
Revision March 2003
KAA00B209M-TGxx
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Voltage supply relative Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG Value
MEMORY
Unit
-1.0 -1.0 +150
NOTES: Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. Functional operation should restricted recommended operating condition. Exposure higher than recommended voltage extended periods time could affect device reliability.
OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced -25°C 85°C) Parameter Supply voltage VDDQ Input logic high voltage Input logic voltage Output logic high voltage Output logic voltage Input leakage current 1.65 VDDQ -0.3 VDDQ 1.95 VDDQ -2mA Symbol 1.65 1.95 Unit Note
NOTES (max) 2.2V AC.The overshoot voltage duration 3ns. (min) -1.0V undershoot voltage duration 3ns. input VDDQ. Input leakage currents include Hi-Z output leakage bi-directional buffers with tri-state outputs. Dout disabled, VOUT VDDQ.
CAPACITANCE (VDD 1.8V, 23°C, 1MHz, VREF =0.9V
Clock RAS, CAS, CKE, Address DQ15 Symbol CCLK CADD COUT Unit Note
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KAA00B209M-TGxx
CHARACTERISTICS
Recommended operating conditions (Voltage referenced 85°C)
MEMORY
Version Parameter Symbol Test Condition Operating Current (One Bank Active) Precharge Standby Current power-down mode Burst length tRC(min) VIL(max), 10ns Unit Note
ICC1
ICC2P
ICC2PS VIL(max), ICC2N VIH(min), VIH(min), 10ns Input signals changed time during 20ns VIH(min), VIL(max), Input signals stable VIL(max), 10ns
Precharge Standby Current power-down mode ICC2NS Active Standby Current power-down mode ICC3P
ICC3PS VIL(max), ICC3N VIH(min), VIH(min), 10ns Input signals changed time during 20ns VIH(min), VIL(max), Input signals stable Page burst 4Banks Activated tCCD 2CLKs tRC(min) Internal TCSR Range
Active Standby Current power-down mode (One Bank Active)
ICC3NS
Operating Current (Burst Mode)
ICC4
Refresh Current
ICC5
40°C
85°C
Self Refresh Current
ICC6
0.2V
Banks Banks Bank
NOTES: Measured with outputs open. Refresh period 64ms. Internal TCSR Support Unless otherwise noted, input swing IeveI CMOS(VIH /VIL=VDDQ/VSSQ).
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KAA00B209M-TGxx
OPERATING TEST CONDITIONS(VDD 1.8V 0.15V,
Parameter input levels (Vih/Vil) Input timing measurement reference level Input rise fall time Output timing measurement reference level Output load condition 85°C)
MEMORY
Value VDDQ VDDQ tr/tf VDDQ Figure
Unit
VDDQ
13.9K Output (DC) VDDQ -0.2V, -0.1mA (DC) 0.2V, 0.1mA 10.6K 30pF Output Z0=50
Vtt=0.5 VDDQ
30pF
Figure Output Load Circuit
Figure Output Load Circuit
Revision March 2003
KAA00B209M-TGxx
OPERATING PARAMETER
operating conditions unless otherwise noted) Version Parameter active active delay delay precharge time active time tRAS(max) cycle time Last data precharge Last data Active delay Last data col. address delay Last data burst stop Auto refresh cycle time Exit self refresh write command Col. address col. address delay Number valid output data Number valid output data tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tARFC(min) tSRFX(min) tCCD(min) latency=3 latency=2 88.5 tRDL Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) 28.5 28.5
MEMORY
Unit
Note
NOTES: minimum number clock cycles determined dividing minimum time required with clock cycle time then rounding next higher integer. Minimum delay required complete write. Minimum tRDL=2CLK tDAL(= tRDL tRP) required complete both last data write command(tRDL) precharge command(tRP). parts allow every cycle column address change. case precharge interrupt, auto precharge read burst stop.
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KAA00B209M-TGxx
CHARACTERISTICS(AC operating conditions unless otherwise noted)
Parameter latency=3 cycle time latency=2 latency=3 valid output delay latency=2 latency=3 Output data hold time latency=2 high pulse width pulse width Input setup time Input hold time output Low-Z latency=3 output Hi-Z latency=2
NOTES Parameters depend programmed latency. clock rising time longer than 1ns, (tr/2-0.5)ns should added parameter. Assumed input rise fall time 1ns. longer than 1ns, transient time compensation should considered, i.e., [(tr tf)/2-1]ns should added parameter.
MEMORY
Unit Note 1000 1000
Symbol tSAC tSLZ tSHZ
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KAA00B209M-TGxx
SIMPLIFIED TRUTH TABLE
COMMAND Register Mode Register Auto Refresh Entry Refresh Self Refresh Exit Bank Active Addr. Read Auto Precharge Disable Column Address Auto Precharge Enable Write Auto Precharge Disable Column Address Auto Precharge Enable Burst Stop Bank Selection Precharge Banks Clock Suspend Active Power Down Entry Exit Entry Precharge Power Down Mode Exit Operation Command CKEn-1 CKEn
MEMORY
A11,
BA0,1 A10/AP
Note
CODE
Address Column Address (A0~A8) Column Address (A0~A8)
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) NOTES Code Operand Code Program keys. (@MRS) issued only banks precharge state. command issued after cycles MRS. Auto refresh functions same refresh DRAM. automatical precharge without precharge command meant "Auto". Auto/self refresh issued only banks precharge state. Bank select addresses. During burst read write with auto precharge, read/write command issued. Another bank read/write command issued after burst. active associated bank issued after burst. Burst stop command valid every burst length. sampled positive going edge masks data-in that same write operation (Write latency read operation, makes data-out Hi-Z state after cycles. (Read latency
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KAA00B209M-TGxx
MODE REGISTER FIELD TABLE PROGRAM MODES
Register Programmed with Normal Address Function BA1*1 Setting Normal A10/ A9*2
MEMORY
Burst Length
W.B.L
Test Mode
Latency
Normal Mode
Test Mode Type Mode Register Reserved Reserved Reserved Latency Latency Reserved Reserved Reserved Reserved Reserved Burst Single Reserved Reserved Setting Normal Burst Type Type Sequential Interleave Mode Select Mode Burst Length BT=0 Reserved Reserved Reserved Full Page BT=1 Reserved Reserved Reserved Reserved
Write Burst Length Length
Full Page Length 512(x16)
Register Programmed with Extended Address Function A10/AP PASR
Mode Select
EMRS PASR(Partial Array Self Ref.) DS(Driver Strength)
Mode Select Mode Normal Reserved EMRS Mobile SDRAM Reserved Reserved Address A11~A10/AP
NOTES: 1.RFU(Reserved future use) should stay during cycle. 2.If high during cycle, "Burst Read Single Write" function will enabled. 3.Mobile SDRAM supports PASR banks, banks banks.
Driver Strength Driver Strength Full Reserved Reserved
PASR Banks Banks Banks Bank Reserved Reserved Reserved Reserved Reserved
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KAA00B209M-TGxx
Partial Array Self Refresh
order save power consumption, Mobile SDRAM PASR option. Mobile SDRAM supports kinds PASR self refresh mode Banks, Banks Bank.
MEMORY
BA1=0 BA0=0
BA1=0 BA0=1
BA1=0 BA0=0
BA1=0 BA0=1
BA1=0 BA0=0
BA1=0 BA0=1
BA1=1 BA0=0
BA1=1 BA0=1
BA1=1 BA0=0
BA1=1 BA0=1
BA1=1 BA0=0
BA1=1 BA0=1
Banks
Banks
Bank
Partial Self Refresh Area
Internal Temperature Compensated Self Refresh
order save power consumption, Mobile DRAM Internal TCSR option. Mobile DRAM supports kinds TCSR range Internal Temperature sensor. Self Refresh Current (Icc6) Temperature Range Banks 40°C 85°C Banks Bank Unit
Deep Power Down Mode External
controls DPD(Power Off) mode. When toggle low, device gets into Deep Power Down mode. should kept high during normal operation. After DPD(Power Off) mode, operation non-active data volatilized. pins except Hi-Z during mode. After mode exit, power sequence should asserted again 200us waiting time required before precharging banks command. After precharging banks, auto refresh command, mode register command extended mode register command should asserted.
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KAA00B209M-TGxx
POWER SEQUENCE Mobile SDRAM
MEMORY
Apply power attempt maintain high state other inputs undefined. Apply before same time VDDQ. Maintain stable power, stable clock input condition minimum 200us. Issue precharge commands banks devices. Issue more auto-refresh commands. Issue mode register command initialize mode register. Issue extended mode register command define PASR operating type device after normal MRS. EMRS cycle mandatory EMRS command needs issued only when TCSR used. default state without EMRS command issued full driver strength, banks refreshed. device ready operation selected EMRS. operating with PASR, PASR mode EMRS setting stage. order adjust another mode state PASR mode, additional EMRS required power sequence needed again this time. that case, banks have idle state prior adjusting EMRS set.
BURST SEQUENCE BURST LENGTH
Initial Address Sequential Interleave
BURST LENGTH
Initial Address Sequential Interleave
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KAA00B209M-TGxx
DEVICE OPERATIONS ADDRESSES 128Mb BANK ADDRESSES (BA0 BA1)
This SDRAM organized four independent banks 2,097,152 words bits memory arrays. inputs latched time assertion select bank used operation. bank addresses latched bank active, read, write, mode register precharge operations.
MEMORY
DEVICE DESELECT
When RAS, high, SDRAM performs operation (NOP). does initiate operation, needed complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. device deselect also entered asserting high. high disables command decoder that RAS, CAS, address inputs ignored.
ADDRESS INPUTS A11)
address bits required decode 2,097,152 word locations multiplexed into address input pins A11). addresses latched along with during bank activate command. column addresses latched along with CAS, during read write command.
OPERATION
used mask input output operations. works similar during read operation inhibits writing during write operation. read latency cycles from zero cycle write, which means masking occurs cycles later read cycle occurs same cycle during write cycle. operation synchronous with clock. signal important during burst interruptions write with read precharge SDRAM. asynchronous nature internal write, operation critical avoid unwanted incomplete writes when complete burst write required. Please refer timing diagram also.
CLOCK (CLK)
clock input used reference SDRAM operations. operations synchronized positive going edge clock. clock transitions must monotonic between VIH. During operation with high inputs assumed valid state (low high) duration setup hold time around positive edge clock order function well perform specifications.
MODE REGISTER (MRS)
mode register stores data controlling various operating modes SDRAM. programs latency, burst type, burst length, test mode various vendor specific options make SDRAM useful variety different applications. default value mode register defined, therefore mode register must written after power operate SDRAM. mode register written asserting RAS, (The SDRAM should active mode with already high prior writing mode register). state address pins same cycle RAS, going data written mode register. clock cycles required complete write mode register. mode register contents changed using same command clock cycle requirements during operation long banks idle state. mode register divided into various fields depending fields functions. burst length field uses burst type uses latency (read latency from column address) vendor specific options test mode A10/AP BA1. write burst length programmed using A10/AP must normal SDRAM operation. Refer table specific codes various burst length, burst type latencies.
CLOCK ENABLE (CKE)
clock enable(CKE) gates clock onto SDRAM. goes synchronously with clock (set-up hold time same other inputs), internal clock suspended from next clock cycle state output burst address frozen long remains low. other inputs ignored from next clock cycle after goes low. When banks idle state goes synchronously with clock, SDRAM enters power down mode from next clock cycle. SDRAM remains power down mode ignoring other inputs long remains low. power down exit synchronous internal clock suspended. When goes high least "1CLK tSS" before high going edge clock, then SDRAM becomes active from same clock edge accepting input commands.
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KAA00B209M-TGxx
DEVICE OPERATIONS (continued) EXTENDED MODE REGISTER (EMRS)
extended mode register stores data selecting driver strength, partial self refresh temperature compensated self refresh. EMRS cycle mandatory EMRS command needs issued only when PASR used. default state without EMRS command issued full driver strength, banks refreshed. extended mode register written asserting RAS, CAS, high ,low BA0(The SDRAM should bank precharge with already high prior writing into extended mode register). state address pins same cycle RAS, going written extended mode register. clock cycles required complete write operation extended mode register. mode register contents changed using same command clock cycle requirements during operation long banks idle state. used partial self refresh used Driver strength, "Low" "High" used EMRS. other address pins except BA1, must proper EMRS operation. Refer table specific codes.
MEMORY
SDRAM four internal banks same chip shares part internal circuitry reduce chip area, therefore restricts activation four banks simultaneously. Also noise generated during sensing each bank SDRAM high, requiring some time power supplies recover before another bank sensed reliably. tRRD(min) specifies minimum time required between activating different bank. number clock cycles required between different bank activation must calculated similar tRCD specification. minimum time required bank active initiate sensing restoring complete dynamic cells determined tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before precharge command that active bank asserted. maximum time bank active state determined tRAS(max). number cycles both tRAS(min) tRAS(max) calculated similar tRCD specification.
BURST READ
burst read command used access burst data consecutive clock cycles from active active bank. burst read command issued asserting with being high positive edge clock. bank must active least tRCD(min) before burst read command issued. first output appears latency number clock cycles after issue burst read command. burst length, burst sequence latency from burst read command determined mode register which already programmed. burst read initiated column address active row. address wraps around initial address does start from boundary such that number outputs from each equal burst length programmed mode register. output goes into high-impedance burst, unless burst read initiated keep data output gapless. burst read terminated issuing another burst read burst write same bank other active bank precharge command same bank. burst stop command valid every page burst length.
BANK ACTIVATE.
bank activate command used select random idle bank. asserting with desired bank address, access initiated. read write operation occur after time delay tRCD(min) from time bank activation. tRCD internal timing parameter SDRAM, therefore dependent operating clock frequency. minimum number clock cycles required between bank activate read write command should calculated dividing tRCD(min) with cycle time clock then rounding result next higher integer.
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KAA00B209M-TGxx
DEVICE OPERATIONS (continued) BURST WRITE
burst write command similar burst read command used write data into SDRAM consecutive clock cycles adjacent addresses depending burst length burst sequence. asserting with valid column address, write burst initiated. data inputs provided initial address same clock cycle burst write command. input buffer deselected burst length, even though internal writing completed yet. writing completed issuing burst read blocking data inputs burst write same another active bank. burst stop command valid every burst length. write burst also terminated using blocking data procreating bank tRDL after last data input written into active row. OPERATION also.
MEMORY
AUTO REFRESH
storage cells 64Mb, 128Mb 256Mb SDRAM need refreshed every 64ms maintain data. auto refresh cycle accomplishes refresh single storage cells. internal counter increments automatically every auto refresh cycle refresh rows. auto refresh command issued asserting with high auto refresh command only asserted with banks being idle state device power down mode (CKE high previous cycle). time required complete auto refresh operation specified tRC(min). minimum number clock cycles required calculated driving with clock cycle time them rounding next higher integer. auto refresh command must followed NOP's until auto refresh operation completed. banks will idle state auto refresh operation. auto refresh preferred refresh mode when SDRAM being used normal data transactions. 64Mb 128Mb SDRAM's auto refresh cycle performed once 15.6us burst 4096 auto refresh cycles once 64ms. 256Mb 512Mb SDRAM's auto refresh cycle performed once 7.8us burst 8192 auto refresh cycles once 64ms.
BANKS PRECHARGE
banks precharged same time using Precharge command. Asserting RAS, with high A10/AP after banks have satisfied tRAS(min) requirement, performs precharge banks. after performing precharge banks, banks idle state.
SELF REFRESH
self refresh another refresh mode available SDRAM. self refresh preferred refresh mode data retention power operation SDRAM. self refresh mode, SDRAM disables internal clock input buffers except CKE. refresh addressing timing internally generated reduce power consumption. self refresh mode entered from banks idle state asserting RAS, with high Once self refresh mode entered, only state being matters, other inputs including clock ignored order remain self refresh mode. self refresh exited restarting external clock then asserting high CKE. This must followed NOP's minimum time tSRFC before SDRAM reaches idle state begin normal operation. case that system uses burst auto refresh during normal operation, recommended burst 8192 auto refresh cycles 256Mb 512Mb, burst 4096 auto refresh cycles 128Mb 64Mb immediately before entering self refresh mode after exiting self refresh mode. other hand, system uses distributed auto refresh, system only keep refresh duty cycle.
PRECHARGE
precharge operation performed active bank asserting RAS, A10/AP with valid bank precharged. precharge command asserted anytime after tRAS(min) satisfied from bank active command desired bank. defined minimum number clock cycles required complete precharge calculated dividing with clock cycle time rounding next higher integer. Care should taken make sure that burst write completed used inhibit writing before precharge command asserted. maximum time bank active specified tRAS(max). Therefore, each bank activate command. precharge, bank enters idle state ready activated again. Entry Power down, Auto refresh, Self refresh Mode register etc. possible only when banks idle state.
AUTO PRECHARGE
precharge operation also performed using auto precharge. SDRAM internally generates timing satisfy tRAS(min) "tRP" programmed burst length latency. auto precharge command issued same time burst read burst write asserting high A10/AP. burst read burst write asserting high A10/AP, bank left active until command asserted. Once auto precharge command given, commands possible that particular bank until bank achieves idle state.
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KAA00B209M-TGxx
BASIC FEATURE FUNCTION DESCRIPTIONS CLOCK Suspend
Clock Suspended During Write
Masked
MEMORY
Clock Suspended During Read (BL=4)
Masked
Internal DQ(CL2) DQ(CL3)
Internal DQ(CL2) DQ(CL3)
Written
Suspended Dout
Operation
Write Mask (BL=4)
Masked
Read Mask (BL=4)
DQ(CL2) DQ(CL3)
DQ(CL2) DQ(CL3)
Masked Hi-Z
Hi-Z
Data-in Mask
Data-out Mask
with Clock Suspended (Full Page Read) DQ(CL2) DQ(CL3)
Hi-Z Hi-Z
Hi-Z Hi-Z
Hi-Z Hi-Z
*NOTE disable/enable 1CLK. makes data Hi-Z after 2CLKs which should masked masks both data-in data-out.
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KAA00B209M-TGxx
Interrupt
MEMORY
Read interrupted Read (BL=4)
DQ(CL2) DQ(CL3)
tCCD
Write interrupted Write (BL=2)
tCCD
Write interrupted Read (BL=2)
DQ(CL2) DQ(CL3)
tCCD
tCDL
tCDL
*NOTE: Interrupt", meant stop burst read/write external command before burst. "CAS Interrupt", stop burst read/write access read write. tCCD delay. (=1CLK) tCDL Last data column address delay. (=1CLK)
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KAA00B209M-TGxx
Interrupt (II) Read Interrupted Write
CL=2, BL=4 iii) CL=3, BL=4 iii)
Hi-Z
MEMORY
Hi-Z
Hi-Z
Hi-Z
Hi-Z
*NOTE: prevent contention, there should least between data data out.
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KAA00B209M-TGxx
Write Interrupted Precharge
tRDL 2CLK
Masked
MEMORY
*NOTE:
prevent contention, should issued which makes least between data data out. inhibit invalid write, should issued. This precharge command burst write command should same bank, otherwise precharge interrupt only another bank precharge four banks operation.
Precharge
Normal Write BL=4 tRDL=2CLK
tRDL*1
Normal Read (BL=4)
DQ(CL2) DQ(CL3)
Auto Precharge
Normal Write (BL=4)
tRDL =2CLK tDAL =tRDL tRP*4 Auto Precharge Starts Auto Precharge Starts@tRDL=2CLK
Normal Read (BL=4) DQ(CL2) DQ(CL3)
*NOTE:
SAMSUNG support tRDL=1CLK tRDL=2CLK memory devices. SAMSUNG recommends tRDL=2 CLK. Number valid output data after precharge Latency respectively. active command precharge bank issued after from this point. read/write command other activated bank issued from this point. burst read/write with auto precharge, interrupt same bank illegal tDAL defined Last data Active delay. SAMSUNG support tDAL=tRDL+
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KAA00B209M-TGxx
Burst Stop Interrupted Precharge
Normal Write BL=4 tRDL=2CLK
tRDL*1
MEMORY
Write Burst Stop (BL=8)
tBDL
Read Interrupted Precharge (BL=4)
STOP
DQ(CL2) DQ(CL3)
Read Burst Stop (BL=4) DQ(CL2) DQ(CL3)
STOP
Mode Register
2CLK
*NOTE:
SAMSUNG support tRDL=1CLK tRDL=2CLK memory devices. SAMSUNG recommends tRDL=2 CLK. tBDL Last data burst stop delay. Read write burst stop command valid every burst length. Number valid output data after precharge burst stop latency= respectively. banks precharge necessary. issued only banks precharge state.
Revision March 2003
KAA00B209M-TGxx
Clock Suspend Exit Power Down Exit
Clock Suspend (=Active Power Down) Exit Internal
MEMORY
Power Down (=Precharge Power Down) Exit
Internal
Auto Refresh Self Refresh Auto Refresh
auto refresh command issued having held with high rising edge clock(CLK). banks must precharged idle tRP(min) before auto refresh command applied. control external address pins required once this cycle started because internal address counter. When refresh cycle completed, banks will idle state. delay between auto refresh command next activate command subsequent auto refresh command must greater than equal tARFC(min).
Command High
Auto Refresh
tARFC(min) 105ns
Self Refresh
Self Refresh command defined having RAS, held with high rising edge clock. Once self Refresh command initiated, must held keep device Self Refresh mode. After clock cycle from self refresh command, external control signals including system clock(CLK) disabled except CKE. clock internally disabled during Self Refresh operation reduce power. exit Self Refresh mode, supply stable clock input before returning high, assert deselect command then assert high. case that system uses burst auto refresh during normal opreation, recommended burst 4096 auto refresh cycle immediately before entering self refresh mode after exiting self refresh mode. other hand, system uses distributed auto refresh, system only keep refresh duty cycle.
Command
Self Refresh
Stable Clock
tSRFX(min) 120ns
Revision March 2003
KAA00B209M-TGxx
About Burst Type Control
Sequential Counting Basic MODE Interleave Counting
MEMORY
"0". BURST SEQUENCE TABLE. (BL=4, BL=1, full page. "1". BURST SEQUENCE TABLE. (BL=4, BL=4, BL=1, Interleave Counting Sequential Counting. Every cycle Read/Write Command with random column address realize Random Column Access. That similar Extended Data (EDO) Operation conventional DRAM.
Random MODE
Random column Access tCCD
About Burst Length Control
A2,1,0 "000". auto precharge, tRAS should violated. A2,1,0 "001". auto precharge, tRAS should violated. A2,1,0 "010". A2,1,0 "011". A2,1,0 "111". Wrap around mode(infinite burst length) should stopped burst stop. interrupt interrupt. "1". Read burst full page write Burst auto precharge write, tRAS should violated. tBDL= Valid after burst stop latency respectively Using burst stop command, burst length control possible. Before burst, precharge command same bank stops read/write burst with precharge. tRDL= with DQM, valid after burst stop latency respectively. During read/write burst with auto precharge, interrupt issued. Before burst, read/write stops read/write burst starts read/write burst. During read/write burst with auto precharge, interrupt issued.
Basic MODE Full Page
Special MODE Random MODE
BRSW
Burst Stop
Interrupt (Interrupted Precharge) Interrupt MODE Interrupt
Revision March 2003
KAA00B209M-TGxx
FUNCTION TRUTH TABLE (TABLE
Current State IDLE Active Read Write Read with Auto Precharge Write with Auto Precharge code Address A10/AP code ILLEGAL
MEMORY
Action
Note
A10/AP ILLEGAL Bank) Active Latch Auto Refresh Self Refresh Mode Register Access ILLEGAL
A10/AP Begin Read latch determine A10/AP Begin Read latch determine A10/AP ILLEGAL Precharge ILLEGAL (Continue Burst Active) (Continue Burst Active) Term burst active
A10/AP Term burst, Read, Determine A10/AP Term burst, Write, Determine A10/AP ILLEGAL Term burst, Precharge timing Reads ILLEGAL (Continue Burst Active) (Continue Burst Active) Term burst active
A10/AP Term burst, read, Determine A10/AP Term burst, Write, Determine A10/AP RA10 RA10 ILLEGAL Term burst, precharge timing Writes ILLEGAL (Continue Burst Precharge) (Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL (Continue Burst Precharge) (Continue Burst Precharge) ILLEGAL ILLEGAL ILLEGAL
A10/AP ILLEGAL
A10/AP ILLEGAL
Revision March 2003
KAA00B209M-TGxx
FUNCTION TRUTH TABLE (TABLE
Current Precharging Activating Refreshing Mode Register Accessing Address A10/AP A10/AP
MEMORY
Action Idle after Idle after ILLEGAL ILLEGAL ILLEGAL Idle after ILLEGAL Active after tRCD Active after tRCD ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Idle after Idle after ILLEGAL ILLEGAL ILLEGAL Idle after clocks Idle after clocks ILLEGAL ILLEGAL ILLEGAL Note
Abbreviations Address Operation Command
Bank Address Column Address
Auto Precharge
*NOTE: entries assume active (High) during precharge clock current clock cycle. Illegal bank specified state Function Iegal bank indicated depending state that bank. Must satisfy contention, turn around, and/or write recovery requirements. bank precharging idle state. precharge bank indicated (and A10/AP). Illegal bank idle.
Revision March 2003
KAA00B209M-TGxx
FUNCTION TRUTH TABLE (TABLE
Current State (n-1) Self Refresh Banks Precharge Power Down Banks Idle State other than Listed above Address
MEMORY
Action Exit Self Refresh Idle after tsRFX(ABI) Exit Self Refresh Idle after tsRFX (ABI) Exit Self Refresh Idle after tsRFX (ABI) ILLEGAL ILLEGAL ILLEGAL (Maintain Self Refresh) INVALID Exit Power Down Exit Power Down ILLEGAL ILLEGAL ILLEGAL (Maintain Power Mode) Refer Table Enter Power Down Enter Power Down ILLEGAL ILLEGAL Bank) Active Enter Self Refresh Refer Operations Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend
Note
Code Mode Register Access
Abbreviations Banks Idle, Address *NOTE: high transition asynchronous. high transition asynchronous restarts internal clock. minimum setup time 1CLK must satisfied before command other than exit. Power down self refresh entered only from banks idle state. Must legal command.
Revision March 2003
KAA00B209M-TGxx
Power Sequence Single Read Write Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 Read Write Cycle Same Bank @Burst Length=4, tRDL=2CLK Page Read Write Cycle Same Bank @Burst Length=4, tRDL=2CLK Page Read Cycle Different Bank @Burst Length=4 Page Write Cycle Different Bank @Burst Length=4, tRDL=2CLK Read Write Cycle Different Bank @Burst Length=4 Read Write Cycle With Auto Precharge @Burst Length=4 Read Write Cycle With Auto Precharge @Burst Length=4 Clock Suspension Operation Cycle @CAS Letency=2, Burst Length=4 Read Interrupted Precharge Command Read Burst Stop Cycle Full Page Burst Write Interrupted Precharge Command Write Burst Stop Cycle Full Page Burst, tRDL=2CLK Burst Read Single Write Cycle @Burst Length Active/precharge Power Dower Down Mode @CAS Latency=2 Burst Length=4 Self Refresh Entry Exit Cycle Exit Cycle Mode Register Cycle Auto Refresh Cycle Extended Mode Register Cycle
MEMORY
Revision March 2003
KAA00B209M-TGxx
Power Sequence Mobile SDRAM
CLOCK
MEMORY
ADDR
A10/AP
Hi-Z
Hi-Z
High level necessary
Precharge (All Bank) Auto Refresh
tARFC
Auto Refresh
tARFC
Normal Extended Active (A-Bank)
Don't care
*NOTE: Apply power attempt maintain high state other inputs undefined. Apply before same time VDDQ. Maintain stable power, stable clock input condition minimum 200us. Issue precharge commands banks devices. Issue more auto-refresh commands. Issue mode register command initialize mode register. Issue extended mode register command define PASR operating type device after normal MRS. EMRS cycle mandatory EMRS command needs issued only when PASR TCSR used. default state without EMRS command issued full driver strength, banks refreshed. device ready operation selected EMRS. operating with PASR, PASR mode EMRS setting stage. order adjust another mode state PASR mode, additional EMRS required power sequence needed again this time. that case, banks have idle state prior adjusting EMRS set.
Revision March 2003
KAA00B209M-TGxx
MEMORY
Single Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
CLOCK
*Note
tRAS HIGH
tRCD
*Note
ADDR
*Note
*Note *Note
*Note
*Note
BA0,BA1
*Note
*Note
*Note
*Note
A10/AP
tSAC
tSLZ
Active
Read
Write
Read Precharge
Active
Don't care
*NOTE: input except don't care when high high going edge. Bank active read/write controlled BA0,BA1.
Revision March 2003
KAA00B209M-TGxx
Read Write Cycle Same Bank @Burst Length=4, tRDL=2CLK
CLOCK
MEMORY
HIGH
*Note
*Note
ADDR
A10/AP
CL=2
tRCD
tSAC
tSHZ
*Note
tRDL
CL=3
tSAC
tSHZ
*Note
tRDL
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank)
Active (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Don't care
*NOTE: Minimum cycle times required complete internal DRAM operation. precharge interrupt burst cycle. [CAS Latency number valid output data available after precharge. Last valid output will Hi-Z(tSHZ) after clcok. Ouput will Hi-Z after burst. Full page burst)
Revision March 2003
KAA00B209M-TGxx
MEMORY
Page Read Write Cycle Same Bank @Burst Length=4, tRDL=2CLK
CLOCK
HIGH
*Note
ADDR
A10/AP
tRDL
CL=2
tRCD
tDAL *Note
CL=3
tCDL
*Note *Note
Active (A-Bank)
Read (A-Bank)
Read (A-Bank)
Write (A-Bank)
Write (A-Bank)
Precharge (A-Bank)
Active (A-Bank)
Don't care
*NOTE: write data before burst read ends, should asserted three cycle prior write command avoid contention. precharge will interrupt writing. Last data input, tRDL before precharge, will written. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally. tDAL ,last data active delay, 2CLK tRP.
Revision March 2003
KAA00B209M-TGxx
Page Read Cycle Different Bank @Burst Length=4
CLOCK
MEMORY
*Note
HIGH
*Note
ADDR
A10/AP
CL=2
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
CL=3
QAa0 QAa1 QAa2 QBb0 QBb1 QBb2 QCc0 QCc1 QCc2 QDd0 QDd1 QDd2
Active (A-Bank)
Read (A-Bank) Active (B-Bank)
Read (B-Bank) Active (C-Bank)
Read (C-Bank) Active (D-Bank)
Read (D-Bank) Precharge (C-Bank)
Precharge (D-Bank)
Precharge (A-Bank)
Precharge (B-Bank)
Don't care
*NOTE: don't cared when RAS, high clock high going dege. interrupt burst read precharge, both read precharge banks must same.
Revision March 2003
KAA00B209M-TGxx
Page Write Cycle Different Bank @Burst Length=4, tRDL=2CLK
CLOCK
MEMORY
HIGH
*Note
ADDR
A10/AP
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DCc0 DCc1 DDd0 DDd1 DDd2
tCDL
*Note
tRDL
Active (A-Bank)
Write (A-Bank) Active (B-Bank)
Write (B-Bank) Active (C-Bank)
Active (D-Bank) Write (C-Bank)
Write (D-Bank)
Precharge (All Banks)
Don't care
*NOTE: interrupt burst write precharge, should asserted mask invalid input data. interrupt burst write precharge, both write precharge banks must same.
Revision March 2003
KAA00B209M-TGxx
Read Write Cycle Different Bank @Burst Length=4
CLOCK
MEMORY
HIGH
ADDR
A10/AP
tCDL
QAa0 QAa1 QAa2 QAa3 DDb0 DDb1 DDb2 DDb3
*Note
CL=2
QBc0 QBc1 QBc2
CL=3
QAa0 QAa1 QAa2 QAa3
DDb0 DDb1 DDb2 DDb3
QBc0 QBc1
Active (A-Bank)
Read (A-Bank)
Precharge (A-Bank) Active (D-Bank)
Write (D-Bank) Active (B-Bank)
Read (B-Bank)
Don't care
*NOTE: tCDL should complete write.
Revision March 2003
KAA00B209M-TGxx
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK
MEMORY
HIGH
ADDR
A10/AP
CL=2
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DAc0 DAc1
CL=3
QAa0 QAa1 QBb0 QBb1 QBb2 DBb3
DAc0 DAc1
Active (A-Bank)
Read with Auto charge (A-Bank) Active (B-Bank)
Read without Auto Precharge(B-Bank) Auto Precharge Start Point (A-Bank) *Note1
Precharge (B-Bank)
Active (A-Bank)
Write with Auto Precharge (A-Bank)
Don't care
*NOTE: When Read(Write) command with auto precharge issued A-Bank after Bank activation. Read(Write) command without auto precharge issued B-Bank before A-Bank auto precharge starts, A-Bank auto precharge will start B-Bank read command input point command issued A-Bank during after A-Bank auto precharge starts.
Revision March 2003
KAA00B209M-TGxx
Read Write Cycle with Auto Precharge @Burst Length=4
CLOCK
MEMORY
HIGH
ADDR
A10/AP
CL=2
CL=3
*Note1
Active (A-Bank)
Read with Auto Precharge (A-Bank)
Auto Precharge Start Point (A-Bank) Active (B-Bank)
Read with Auto Precharge (B-Bank)
Auto Precharge Start Point (B-Bank)
Don't care
*NOTE: command A-bank allowed this period. determined from auto precharge start point
Revision March 2003
KAA00B209M-TGxx
MEMORY
Clock Suspension Operation Cycle @CAS Latency=2, Burst Length=4
CLOCK
ADDR
A10/AP
tSHZ
tSHZ
*Note
Active
Read
Clock Suspension
Read
Read
Write Write Clock Suspension
Write
Don't care
*NOTE: needed prevent contention.
Revision March 2003
KAA00B209M-TGxx
MEMORY
Read Interrupted Precharge Command Read Burst Stop Cycle @Full Page Burst
CLOCK
HIGH
ADDR
A10/AP
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
CL=2
QAa0 QAa1 QAa2 QAa3 QAa4
CL=3 QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
Active (A-Bank)
Read (A-Bank)
Burst Stop
Read (A-Bank)
Precharge (A-Bank)
Don't care
*NOTE: full page mode, burst finished burst stop precharge. About valid after burst stop, same case interrupt. Both cases illustrated above timing diagram. label them. burst write, Burst stop interrupt should compared carefully. Refer timing diagram "Full page write burst stop cycle". Burst stop valid every burst length.
Revision March 2003
KAA00B209M-TGxx
MEMORY
Write Interrupted Precharge Command Write Burst Stop Cycle Full Page Burst, tRDL=2CLK
CLOCK
HIGH
ADDR
A10/AP
tBDL
*Note *Note
tRDL
DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
DAa0 DAa1 DAa2 DAa3 DAa4
Active (A-Bank)
Write (A-Bank)
Burst Stop
Write (A-Bank)
Precharge (A-Bank)
Don't care
*NOTE: full page mode, burst finished burst stop precharge. Data-in cycle interrupted precharge written into corresponding memory cell. defined parameter tRDL. write interrupted precharge command needed prevent invalid write. should mask invalid input data precharge command cycle when asserting precharge before burst. Input data after precharge cycle will masked internally. Burst stop valid every burst length.
Revision March 2003
KAA00B209M-TGxx
Burst Read Single Write Cycle @Burst Length=2
CLOCK
MEMORY
HIGH
*Note
ADDR
A10/AP
CL=2
DAa0
QAb0 QAb1
DBc0
QCd0 QCd1
CL=3
DAa0
QAb0 QAb1
DBc0
QCd0 QCd1
Active (A-Bank)
Active (B-Bank) Write Read with (A-Bank) Auto Precharge (A-Bank)
Active (C-Bank) Write with Auto Precharge (B-Bank)
Read (C-Bank)
Precharge (C-Bank)
Don't care
*NOTE: BRSW modes enabled setting "High" (Mode Register Set). BRSW Mode, burst length write fixed regardless programmed burst length. When BRSW write command with auto precharge executed, keep mind that tRAS should violated. Auto precharge executed burst-end cycle, case BRSW write command, next cycle starts precharge.
Revision March 2003
KAA00B209M-TGxx
MEMORY
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
CLOCK
*Note
*Note
*Note
*Note
ADDR
A10/AP
tSHZ
Precharge Power-down Entry
Active
Read
Precharge
Precharge Power-down Exit
Active Power-down Entry
Active Power-down Exit
Don't care
*NOTE: banks should idle state prior entering precharge power down mode. should high least 1CLK prior active command. violate minimum refresh specification. (64ms)
Revision March 2003
KAA00B209M-TGxx
Self Refresh Entry Exit Cycle
CLOCK
*Note *Note
MEMORY
*Note
tSRFX
*Note
*Note
ADDR
BA0,BA1
A10/AP
Hi-Z
Hi-Z
Self Refresh Entry
Self Refresh Exit
Auto Refresh
Don't care
*NOTE: ENTER SELF REFRESH MODE with should same clcok cycle. After clock cycle, inputs including system clock don't care except CKE. device remains self refresh mode long stays "Low". cf.) Once device enters self refresh mode, minimum tRAS required before exit from self refresh. EXIT SELF REFRESH MODE System clock restart stable before returning high. starts from high. Minimum tSRFX required after going high complete self refresh exit. cycle(64Mb ,128Mb) cycle(256Mb, 512Mb) burst auto refresh required before self refresh entry after self refresh exit system uses burst refresh.
Revision March 2003
KAA00B209M-TGxx
Mode Register Cycle
CLOCK
MEMORY
Auto Refresh Cycle
HIGH
HIGH
*Note
tARFC
*Note
*Note
ADDR
Hi-Z
Hi-Z
Command
Auto Refresh
Command
banks precharge should completed before Mode Register cycle auto refresh cycle.
Don't care
*NOTE: MODE REGISTER CYCLE RAS, CAS, BA0, activation same clock cycle with address will internal mode register. Minimum clock cycles should before activation. Please refer Mode Register table.
Revision March 2003
KAA00B209M-TGxx
Extended Mode Register Cycle
CLOCK
MEMORY
HIGH
*Note
*Note
*Note
ADDR
Hi-Z
EMRS
Command
Don't care
*NOTE: EXTENDED MODE REGISTER CYCLE RAS, CAS, BA0, activation same clock cycle with address will internal mode register. Minimum clock cycles should before activation. Please refer Mode Register table.
Revision March 2003
KAA00B209M-TGxx
PACKAGE DIMENSION 127-Ball Tape Ball Grid Array Package (measured millimeters)
MEMORY
View
Bottom View
10.50±0.10 0.80 x11=8.80
10.50±0.10
(Datum
0.80
(Datum 12.00±0.10
4.80 0.80x12=9.60 0.80 12.00±0.10
4.40 127- 0.45±0.05
0.20
Side View
0.45±0.05 0.32±0.05 1.30±0.10
0.08MAX
12.00±0.10
Revision March 2003

Multi-Chip Package MEMORY MEMORY 256M Bit(16Mx16) Nand Flash

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