Multi-Chip Package MEMORY Preliminary MEMORY 128M Bit(8Mx16)
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KBF0x0800M
Multi-Chip Package MEMORY
Preliminary MEMORY
128M Bit(8Mx16) Synchronous Burst Multi Bank Flash Bit(4Mx16) Synchronous Burst UtRAM
Revision History
Revision History
Initial Draft (128M Flash M-die_rev0.7) (64M UtRAM B-die_rev0.6)
Draft Date
Remark
November 2003 Preliminary
Note more detailed features specifications including FAQ, please refer Samsung's site. attached datasheets prepared approved SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications. SAMSUNG Electronics will evaluate reply your requests questions about device. have questions, please contact SAMSUNG branch office near you.
Revision November 2003
KBF0x0800M
Multi-Chip Package MEMORY
Preliminary MEMORY
128M Bit(8Mx16) Synchronous Burst Multi Bank Flash Bit(4Mx16) Synchronous Burst UtRAM
FEATURES
<Common> Operating Temperature -25°C 85°C Package 115Ball FBGA Type 8.0mm 12.0mm 0.8mm ball pitch 1.4mm (Max.) Thickness <NOR Flash(for each device)> Single Voltage, 1.7V 1.9V Read Write operations Organization 8,388,608 Word Mode Only) Read While Program/Erase Operation Multiple Bank Architecture Banks (8Mb Partition) Read Access Time CL=30pF) Asynchronous Random Access Time 88.5ns (54MHz) 70ns (66MHz) Synchronous Random Access Time 88.5ns (54MHz) 71ns (66MHz) Burst Access Time 14.5ns (54MHz) 11ns (66MHz) Burst Length Continuous Linear Burst Linear Burst 8-word 16-word with No-wrap Wrap Block Architecture Eight 4Kword blocks hundreds fifty-five 32Kword blocks Bank contains eight Kword blocks fifteen 32Kword blocks Bank Bank contain hundred forty 32Kword blocks Reduce program time using Power Consumption (Typical value, CL=30pF) Burst Access Current 25mA Program/Erase Current 15mA Read While Program/Erase Current 35mA Standby Mode/Auto Sleep Mode Block Protection/Unprotection Using software command sequence Last boot blocks protected WP=VIL blocks protected VPP=VIL Handshaking Feature Provides host system with minimum latency monitoring Erase Suspend/Resume Program Suspend/Resume Unlock Bypass Program/Erase Hardware Reset (RESET) Data Polling Toggle Bits Provides software method detecting status program erase completion Endurance 100K Program/Erase Cycles Minimum Data Retention years Support Common Flash Memory Interface Write Inhibit
<UtRAM(for each device)> Process Technology: CMOS Organization: Power Supply Voltage: 2.5~2.7V
VCCQ 1.7~2.0V
Three State Outputs Compatible with Power SRAM Supports (Mode Register Set) Supports Asynchronous Read/Write Operation Asynchronous
mode
Supports Synchronous Burst Read Asynchronous Write
Operation Synchronous mode
Synchronous Burst Read Operation
Supports word word word Burst Read mode Supports Linear Burst type Interleave Burst type Latency support (depends clock frequency) Max. Burst Clock Frequency 54MHz
GENERAL DESCRIPTION
KBF0x0800M Multi Chip Package Memory which combines 128Mbit Synchronous Burst Multi Bank Flash Memory 64Mbit Synchronous Burst UtRAM. 128Mbit Synchronous Burst Multi Bank Flash Memory organized bits 64Mbit Synchronous Burst UtRAM organized bits. 128Mbit Synchronous Burst Multi Bank Flash Memory, memory architecture device designed divide memory arrays into blocks with independent hardware protection. This block architecture provides highly flexible erase program capability. Flash consists sixteen banks. This device capable reading data from bank while programming erasing other bank. Regarding read access time, 54MHz, device provides burst access 14.5ns with initial access times 88.5ns 30pF. 66MHz, device provides burst access 11ns with initial access times 71ns 30pF. device performs program operation units bits (Word) erases units block. Single multiple blocks erased. block erase operation completed within typically sec. device requires 15mA program/erase current extended temperature ranges. 64Mbit Synchronous Burst UtRAM, device supports DPD(Deep Power Down) mode power saving. mode controlled pin. device supports MRS(Mode Register Set) synchronous burst read mode. KBF0x0800M suitable data memory mobile communication system reduce only mount area also power consumption. This device available 115-ball FBGA Type.
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision November 2003
KBF0x0800M
CONFIGURATION
Preliminary MEMORY
ADVf
CLKf
Vccu
ADVu
CLKu
RESET
Vccu
CEf1
DQ13
DQ15
DQ10
Vccf
Vccqu
DQ12
CEf2
DQ11
DQ14
Vccf
115-FBGA: View (Ball Down)
Revision November 2003
KBF0x0800M
DESCRIPTION
Ball Name DQ15 CEf1 CEf2 RESET CLKf CLKu Description Address Input Balls (Common) Data Input/Output Balls (Common) Chip Enable (Flash1, Flash2) Chip Select (UtRAM) Output Enable (Common) Hardware Reset (Flash Memory) Accelerates Programming (Flash Memory) Write Enable (Common) Write Protection (Flash1) Write Protection (Flash2) Clock (Flash Memory) Clock (UtRAM) Ball Name ADVf ADVu Vccf Vccu Vccqu
Preliminary MEMORY
Description Ready Output (Flash Memory) Address Input Valid (Flash Memory) Address Input Valid (UtRAM) Mode Register (UtRAM) Lower Byte Enable (UtRAM) Upper Byte Enable (UtRAM) Power Supply (Flash Memory) Power Supply (UtRAM) Data Power (UtRAM) Ground (Common) Connection
ORDERING INFORMATION
Samsung MCP(4 Chip) Memory Device Type Flash Flash UtRAM UtRAM Flash Density Org. 128Mbit 128Mbit, Vcc=1.8V, x16(Burst) Bank Size(Boot Block) 16M, 16Bank(Bottom) 16M, 16Bank(TOP) NAND Flash Density Org. NONE Access Time 18.5ns, 18.5ns, 18.5ns, 18.5ns Package FBGA(Lead Free)
Version Generation
SDRAM Density Org. NONE
UtRAM Density Vcc/Vccq Org. 64Mbit 64Mbit, 2.6V/1.8V, x16, Burst
SRAM Density Org. NONE
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KBF0x0800M
Figure FUNCTIONAL BLOCK DIAGRAM
Preliminary MEMORY
Vccf Address(A0 A22) CEF1 RESET CLKF ADVF
128M Flash Memory
DQ15
Vccf
128M Flash Memory
CEF2 Vccu Vccqu
DQ15
DQ15
CLKu ADVu
UtRAM
DQ15
Vccu Vccqu
UtRAM
DQ15
Revision November 2003
KBF0x0800M
Preliminary MEMORY
128M Bit(8Mx16) Synchronous Burst, Multi Bank Flash M-die Each Device
Revision November 2003
KBF0x0800M
Table PRODUCT LINE-UP
Synchronous/Burst Speed Option Max. Initial Access Time (tIAA, VCC=1.7V-1.9V Max. Burst Access Time (tBA, Max. Access Time (tOE, (54MHz) 88.5 14.5 (66MHz)
Preliminary MEMORY
Asynchronous Speed Option Access Time (tAA, Access Time (tCE, Access Time (tOE, (54MHz) (66MHz) 88.5 14.5
Table Flash DEVICE BANK DIVISIONS
Bank Mbit Mbit Block Sizes Eight 4Kwords, Fifteen 32Kwords Mbit Mbit Bank Bank Block Sizes hundred forty 32Kwords
Revision November 2003
KBF0x0800M
Table 3-1. Boot Block Address Table
Bank Block BA262 BA261 BA260 BA259 BA258 BA257 BA256 BA255 BA254 BA253 BA252 Bank BA251 BA250 BA249 BA248 BA247 BA246 BA245 BA244 BA243 BA242 BA241 BA240 BA239 BA238 BA237 BA236 BA235 BA234 BA233 BA232 Bank BA231 BA230 BA229 BA228 BA227 BA226 BA225 BA224 BA223 BA222 Bank BA221 BA220 BA219 Kwords Kwords Kwords Kwords Kwords Kwords Kwords kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 7FF000h-7FFFFFh 7FE000h-7FEFFFh 7FD000h-7FDFFFh 7FC000h-7FCFFFh 7FB000h-7FBFFFh 7FA000h-7FAFFFh 7F9000h-7F9FFFh 7F8000h-7F8FFFh 7F0000h-7F7FFFh 7E8000h-7EFFFFh 7E0000h-7E7FFFh 7D8000h-7DFFFFh 7D0000h-7D7FFFh 7C8000h-7CFFFFh 7C0000h-7C7FFFh 7B8000h-7BFFFFh 7B0000h-7B7FFFh 7A8000h-7AFFFFh 7A0000h-7A7FFFh 798000h-79FFFFh 790000h-797FFFh 788000h-78FFFFh 780000h-787FFFh 778000h-77FFFFh 770000h-777FFFh 768000h-76FFFFh 760000h-767FFFh 758000h-75FFFFh 750000h-757FFFh 748000h-74FFFFh 740000h-747FFFh 738000h-73FFFFh 730000h-737FFFh 728000h-72FFFFh 720000h-727FFFh 718000h-71FFFFh 710000h-717FFFh 708000h-70FFFFh 700000h-707FFFh 6F8000h-6FFFFFh 6F0000h-6F7FFFh 6E8000h-6EFFFFh 6E0000h-6E7FFFh 6D8000h-6DFFFFh
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Table 3-1. Boot Block Address Table
Bank Block BA218 BA217 BA216 BA215 BA214 Bank BA213 BA212 BA211 BA210 BA209 BA208 BA207 BA206 BA205 BA204 BA203 BA202 BA201 BA200 Bank BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 BA186 BA185 BA184 Bank BA183 BA182 BA181 BA180 BA179 BA178 BA177 BA176 Bank BA175 Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 6D0000h-6D7FFFh 6C8000h-6CFFFFh 6C0000h-6C7FFFh 6B8000h-6BFFFFh 6B0000h-6B7FFFh 6A8000h-6AFFFFh 6A0000h-6A7FFFh 698000h-69FFFFh 690000h-697FFFh 688000h-68FFFFh 680000h-687FFFh 678000h-67FFFFh 670000h-677FFFh 668000h-66FFFFh 660000h-667FFFh 658000h-65FFFFh 650000h-657FFFh 648000h-64FFFFh 640000h-647FFFh 638000h-63FFFFh 630000h-637FFFh 628000h-62FFFFh 620000h-627FFFh 618000h-61FFFFh 610000h-617FFFh 608000h-60FFFFh 600000h-607FFFh 5F8000h-5FFFFFh 5F0000h-5F7FFFh 5E8000h-5EFFFFh 5E0000h-5E7FFFh 5D8000h-5DFFFFh 5D0000h-5D7FFFh 5C8000h-5CFFFFh 5C0000h-5C7FFFh 5B8000h-5BFFFFh 5B0000h-5B7FFFh 5A8000h-5AFFFFh 5A0000h-5A7FFFh 598000h-59FFFFh 590000h-597FFFh 588000h-58FFFFh 580000h-587FFFh 578000h-57FFFFh
Revision November 2003
KBF0x0800M
Table 3-1. Boot Block Address Table
Bank Block BA174 BA173 BA172 BA171 BA170 BA169 BA168 Bank BA167 BA166 BA165 BA164 BA163 BA162 BA161 BA160 BA159 BA158 BA157 BA156 BA155 BA154 BA153 BA152 Bank BA151 BA150 BA149 BA148 BA147 BA146 BA145 BA144 BA143 BA142 BA141 BA140 BA139 BA138 BA137 Bank BA136 BA135 BA134 BA133 BA132 BA131 BA130 Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 570000h-577FFFh 568000h-56FFFFh 560000h-567FFFh 558000h-55FFFFh 550000h-557FFFh 548000h-54FFFFh 540000h-547FFFh 538000h-53FFFFh 530000h-537FFFh 528000h-52FFFFh 520000h-527FFFh 518000h-51FFFFh 510000h-517FFFh 508000h-50FFFFh 500000h-507FFFh 4F8000h-4FFFFFh 4F0000h-4F7FFFh 4E8000h-4EFFFFh 4E0000h-4E7FFFh 4D8000h-4DFFFFh 4D0000h-4D7FFFh 4C8000h-4CFFFFh 4C0000h-4C7FFFh 4B8000h-4BFFFFh 4B0000h-4B7FFFh 4A8000h-4AFFFFh 4A0000h-4A7FFFh 498000h-49FFFFh 490000h-497FFFh 488000h-48FFFFh 480000h-487FFFh 478000h-47FFFFh 470000h-477FFFh 468000h-46FFFFh 460000h-467FFFh 458000h-45FFFFh 450000h-457FFFh 448000h-44FFFFh 440000h-447FFFh 438000h-43FFFFh 430000h-437FFFh 428000h-42FFFFh 420000h-427FFFh 418000h-41FFFFh 410000h-417FFFh
Revision November 2003
KBF0x0800M
Table 3-1. Boot Block Address Table
Bank Bank BA128 BA127 BA126 BA125 BA124 BA123 BA122 BA121 BA120 Bank BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 Bank BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 Bank BA90 BA89 BA88 BA87 BA86 BA85 Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block BA129 Block Size Kwords
Preliminary MEMORY
(x16) Address Range 408000h-40FFFFh 400000h-407FFFh 3F8000h-3FFFFFh 3F0000h-3F7FFFh 3E8000h-3EFFFFh 3E0000h-3E7FFFh 3D8000h-3DFFFFh 3D0000h-3D7FFFh 3C8000h-3CFFFFh 3C0000h-3C7FFFh 3B8000h-3BFFFFh 3B0000h-3B7FFFh 3A8000h-3AFFFFh 3A0000h-3A7FFFh 398000h-39FFFFh 390000h-397FFFh 388000h-38FFFFh 380000h-387FFFh 378000h-37FFFFh 370000h-377FFFh 368000h-36FFFFh 360000h-367FFFh 358000h-35FFFFh 350000h-357FFFh 348000h-34FFFFh 340000h-347FFFh 338000h-33FFFFh 330000h-337FFFh 328000h-32FFFFh 320000h-327FFFh 318000h-31FFFFh 310000h-317FFFh 308000h-30FFFFh 300000h-307FFFh 2F8000h-2FFFFFh 2F0000h-2F7FFFh 2E8000h-2EFFFFh 2E0000h-2E7FFFh 2D8000h-2DFFFFh 2D0000h-2D7FFFh 2C8000h-2CFFFFh 2C0000h-2C7FFFh 2B8000h-2BFFFFh 2B0000h-2B7FFFh 2A8000h-2AFFFFh
Revision November 2003
KBF0x0800M
Table 3-1. Boot Block Address Table
Bank Block BA84 BA83 Bank BA82 BA81 BA80 BA79 BA78 BA77 BA76 BA75 BA74 BA73 BA72 Bank BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 Bank BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 Bank BA43 BA42 BA41 BA40 Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 2A0000h-2A7FFFh 298000h-29FFFFh 290000h-297FFFh 288000h-28FFFFh 280000h-287FFFh 278000h-27FFFFh 270000h-277FFFh 268000h-26FFFFh 260000h-267FFFh 258000h-25FFFFh 250000h-257FFFh 248000h-24FFFFh 240000h-247FFFh 238000h-23FFFFh 230000h-237FFFh 228000h-22FFFFh 220000h-227FFFh 218000h-21FFFFh 210000h-217FFFh 208000h-20FFFFh 200000h-207FFFh 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh
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Table 3-1. Boot Block Address Table
Bank Block BA39 BA38 BA37 BA36 Bank BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 Bank BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 Bank Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh
Revision November 2003
KBF0x0800M
Table 3-2. Bottom Boot Block Address Table
Bank Block BA262 BA261 BA260 BA259 BA258 BA257 BA256 Bank BA255 BA254 BA253 BA252 BA251 BA250 BA249 BA248 BA247 BA246 BA245 BA244 BA243 BA242 BA241 BA240 BA239 Bank BA238 BA237 BA236 BA235 BA234 BA233 BA232 BA231 BA230 BA229 Bank BA228 BA227 BA226 Kwords Kwords Kwords Kwords Kwords Kwords Kwords kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 7F8000h-7FFFFFh 7F0000h-7F7FFFh 7E8000h-7EFFFFh 7E0000h-7E7FFFh 7D8000h-7DFFFFh 7D0000h-7D7FFFh 7C8000h-7CFFFFh 7C0000h-7C7FFFh 7B8000h-7BFFFFh 7B0000h-7B7FFFh 7A8000h-7AFFFFh 7A0000h-7A7FFFh 798000h-79FFFFh 790000h-797FFFh 788000h-78FFFFh 780000h-787FFFh 778000h-77FFFFh 770000h-777FFFh 768000h-76FFFFh 760000h-767FFFh 758000h-75FFFFh 750000h-757FFFh 748000h-74FFFFh 740000h-747FFFh 738000h-73FFFFh 730000h-737FFFh 728000h-72FFFFh 720000h-727FFFh 718000h-71FFFFh 710000h-717FFFh 708000h-70FFFFh 700000h-707FFFh 6F8000h-6FFFFFh 6F0000h-6F7FFFh 6E8000h-6EFFFFh 6E0000h-6E7FFFh 6D8000h-6DFFFFh
Revision November 2003
KBF0x0800M
Table 3-2. Bottom Boot Block Address Table
Bank Block BA225 BA224 BA223 BA222 BA221 Bank BA220 BA219 BA218 BA217 BA216 BA215 BA214 BA213 BA212 BA211 BA210 BA209 BA208 BA207 Bank BA206 BA205 BA204 BA203 BA202 BA201 BA200 BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 Bank BA190 BA189 BA188 BA187 BA186 BA185 BA184 BA183 Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 6D0000h-6D7FFFh 6C8000h-6CFFFFh 6C0000h-6C7FFFh 6B8000h-6BFFFFh 6B0000h-6B7FFFh 6A8000h-6AFFFFh 6A0000h-6A7FFFh 698000h-69FFFFh 690000h-697FFFh 688000h-68FFFFh 680000h-687FFFh 678000h-67FFFFh 670000h-677FFFh 668000h-66FFFFh 660000h-667FFFh 658000h-65FFFFh 650000h-657FFFh 648000h-64FFFFh 640000h-647FFFh 638000h-63FFFFh 630000h-637FFFh 628000h-62FFFFh 620000h-627FFFh 618000h-61FFFFh 610000h-617FFFh 608000h-60FFFFh 600000h-607FFFh 5F8000h-5FFFFFh 5F0000h-5F7FFFh 5E8000h-5EFFFFh 5E0000h-5E7FFFh 5D8000h-5DFFFFh 5D0000h-5D7FFFh 5C8000h-5CFFFFh 5C0000h-5C7FFFh 5B8000h-5BFFFFh 5B0000h-5B7FFFh 5A8000h-5AFFFFh 5A0000h-5A7FFFh 598000h-59FFFFh 590000h-597FFFh 588000h-58FFFFh 580000h-587FFFh
Revision November 2003
KBF0x0800M
Table 3-2. Bottom Boot Block Address Table
Bank Block BA182 BA181 BA180 BA179 BA178 BA177 BA176 BA175 Bank BA174 BA173 BA172 BA171 BA170 BA169 BA168 BA167 BA166 BA165 BA164 BA163 BA162 BA161 BA160 BA159 Bank BA158 BA157 BA156 BA155 BA154 BA153 BA152 BA151 BA150 BA149 BA148 BA147 BA146 BA145 BA144 Bank BA143 BA142 BA141 BA140 BA139 BA138 BA137 Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 578000h-57FFFFh 570000h-577FFFh 568000h-56FFFFh 560000h-567FFFh 558000h-55FFFFh 550000h-557FFFh 548000h-54FFFFh 540000h-547FFFh 538000h-53FFFFh 530000h-537FFFh 528000h-52FFFFh 520000h-527FFFh 518000h-51FFFFh 510000h-517FFFh 508000h-50FFFFh 500000h-507FFFh 4F8000h-4FFFFFh 4F0000h-4F7FFFh 4E8000h-4EFFFFh 4E0000h-4E7FFFh 4D8000h-4DFFFFh 4D0000h-4D7FFFh 4C8000h-4CFFFFh 4C0000h-4C7FFFh 4B8000h-4BFFFFh 4B0000h-4B7FFFh 4A8000h-4AFFFFh 4A0000h-4A7FFFh 498000h-49FFFFh 490000h-497FFFh 488000h-48FFFFh 480000h-487FFFh 478000h-47FFFFh 470000h-477FFFh 468000h-46FFFFh 460000h-467FFFh 458000h-45FFFFh 450000h-457FFFh 448000h-44FFFFh 440000h-447FFFh 438000h-43FFFFh 430000h-437FFFh 428000h-42FFFFh 420000h-427FFFh 418000h-41FFFFh 410000h-417FFFh
Revision November 2003
KBF0x0800M
Table 3-2. Bottom Boot Block Address Table
Bank Bank BA135 BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 Bank BA126 BA125 BA124 BA123 BA122 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 Bank BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 Bank BA97 BA96 BA95 BA94 BA93 BA92 Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block BA136 Block Size Kwords
Preliminary MEMORY
(x16) Address Range 408000h-40FFFFh 400000h-407FFFh 3F8000h-3FFFFFh 3F0000h-3F7FFFh 3E8000h-3EFFFFh 3E0000h-3E7FFFh 3D8000h-3DFFFFh 3D0000h-3D7FFFh 3C8000h-3CFFFFh 3C0000h-3C7FFFh 3B8000h-3BFFFFh 3B0000h-3B7FFFh 3A8000h-3AFFFFh 3A0000h-3A7FFFh 398000h-39FFFFh 390000h-397FFFh 388000h-38FFFFh 380000h-387FFFh 378000h-37FFFFh 370000h-377FFFh 368000h-36FFFFh 360000h-367FFFh 358000h-35FFFFh 350000h-357FFFh 348000h-34FFFFh 340000h-347FFFh 338000h-33FFFFh 330000h-337FFFh 328000h-32FFFFh 320000h-327FFFh 318000h-31FFFFh 310000h-317FFFh 308000h-30FFFFh 300000h-307FFFh 2F8000h-2FFFFFh 2F0000h-2F7FFFh 2E8000h-2EFFFFh 2E0000h-2E7FFFh 2D8000h-2DFFFFh 2D0000h-2D7FFFh 2C8000h-2CFFFFh 2C0000h-2C7FFFh 2B8000h-2BFFFFh 2B0000h-2B7FFFh 2A8000h-2AFFFFh
Revision November 2003
KBF0x0800M
Table 3-2. Bottom Boot Block Address Table
Bank Block BA91 BA90 Bank BA89 BA88 BA87 BA86 BA85 BA84 BA83 BA82 BA81 BA80 BA79 Bank BA78 BA77 BA76 BA75 BA74 BA73 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 Bank BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 Bank BA50 BA49 BA48 BA47 Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 2A0000h-2A7FFFh 298000h-29FFFFh 290000h-297FFFh 288000h-28FFFFh 280000h-287FFFh 278000h-27FFFFh 270000h-277FFFh 268000h-26FFFFh 260000h-267FFFh 258000h-25FFFFh 250000h-257FFFh 248000h-24FFFFh 240000h-247FFFh 238000h-23FFFFh 230000h-237FFFh 228000h-22FFFFh 220000h-227FFFh 218000h-21FFFFh 210000h-217FFFh 208000h-20FFFFh 200000h-207FFFh 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh
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Table 3-2. Bottom Boot Block Address Table
Bank Block BA46 BA45 BA44 BA43 Bank BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 BA34 BA33 BA32 Bank BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 Bank BA11 BA10 Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Kwords Block Size Kwords Kwords Kwords Kwords
Preliminary MEMORY
(x16) Address Range 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh
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PRODUCT INTRODUCTION
Preliminary MEMORY
device 128Mbit (134,217,728 bits) NOR-type Burst Flash memory. device features 1.8V single voltage power supply operating within range 1.7V 1.9V. device programmed using Channel Electron (CHE) injection mechanism which used program EPROMs. device erased electrically using Fowler-Nordheim tunneling mechanism. provide highly flexible erase program capability, device adapts block memory architecture that divides memory array into blocks (32-Kword 4-Kword Programming done units bits (Word). bits data multiple blocks erased when device executes erase operation. prevent device from accidental erasing over-writing programmed data, memory blocks hardware protected. Regarding read access time, 54MHz, device provides burst access 14.5ns with initial access times 88.5ns 30pF. 66MHz, device provides burst access 11ns with initial access times 71ns 30pF. command device compatible with standard Flash devices. device uses Chip Enable (CE), Write Enable (WE), Address Valid(AVD) Output Enable (OE) control asynchronous read write operation. burst operations, device additionally requires Ready (RDY) Clock (CLK). Device operations executed selective command codes. command codes combined with addresses data sequentially written command registers using microprocessor write timing. command codes serve inputs internal state machine which controls program/erase circuitry. Register contents also internally latch addresses data necessary execute program erase operations. device implemented with Internal Program/Erase Routines execute program/erase operations. Internal Program/Erase Routines invoked program/erase command sequences. Internal Program Routine automatically programs verifies data specified addresses. Internal Erase Routine automatically pre-programs memory cell which programmed then executes erase operation. device means indicate status completion program/erase operations. status indicated Data polling DQ7, Toggle (DQ6). Once operations have been completed, device automatically resets itself read mode. device requires only burst asynchronous mode read current program/erase operations.
Table Device Operations
Operation Asynchronous Read Operation A0-22 DQ0-15 RESET
Write
Standby
High-Z
Hardware Reset
High-Z
Load Initial Burst Address
Burst DOUT High-Z
Burst Read Operation Terminate Burst Read Cycle
Terminate Burst Read Cycle RESET
High-Z
Terminate Current Burst Read Cycle Start Burst Read Cycle Note L=VIL (Low), H=VIH (High), X=Don't Care.
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COMMAND DEFINITIONS
Preliminary MEMORY
device operates selecting executing operational modes. Each operational mode command set. order select certain mode, proper command with specific address data sequences must written into command register. Writing incorrect information which include address data writing improper command will reset device read mode. defined valid register command sequences stated Table
Table Command Sequences
Command Definitions Asynchronous Read Data Reset(Note Data Autoselect Manufacturer ID(Note Autoselect Device ID(Note Autoselect Block Protection Verify(Note Autoselect Handshaking(Note Program Data Unlock Bypass Data Unlock Bypass Program(Note Data Unlock Bypass Block Erase(Note Data Unlock Bypass Chip Erase(Note Data Unlock Bypass Reset Data Chip Erase Data Block Erase Data Erase Suspend (Note Data Erase Resume (Note Data Program Suspend (Note12) Data Program Resume (Note11) Data (DA)XXXH (DA)XXXH (DA)XXXH (DA)XXXH 555H 2AAH 555H 555H 2AAH 555H 2AAH 555H 555H 2AAH 555H XXXH XXXH XXXH XXXH Data Data Data Data 555H 2AAH 555H 555H 2AAH 555H 0H/1H 555H 2AAH (DA)555H 00H/ (DA)X03H 555H 2AAH (BA)555H Note6 (BA)X02H 555H 2AAH (DA)555H (DA)X01H 555H 2AAH (DA)555H (DA)X00H XXXH Cycle Cycle Cycle Cycle Cycle Cycle Cycle
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Table Command Sequences (Continued)
Command Definitions Block Protection/Unprotection (Note Data Query (Note Data Burst Mode Configuration Register (Note Data Notes: (DA)X55H 555H 2AAH (CR)555H Cycle Cycle Cycle Cycle
Preliminary MEMORY
Cycle
Cycle
Cycle
Read Address Program Address, Read Data, Program Data Block Address (A22 A12) Bank Address (A22 A19) Address block protected unprotected, Configuration Register Setting cycle data autoselect mode output data. others input data. Data bits DQ15-DQ8 don't care command sequences, except Device Unless otherwise noted, address bits A22-A11 don't cares. reset command required return read mode. bank entered autoselect mode during erase suspend mode, writing reset command returns that bank erase suspend mode. bank entered autoselect mode during program suspend mode, writing reset command returns that bank program suspend mode. goes high during program erase operation, writing reset command returns that bank read mode erase suspend mode that bank erase suspend mode. cycle bank address autoselect mode must same. Device Data "22F4H" Boot Block Device, "22F5H" Bottom Boot Block Device unprotected block protected block. handshaking, non-handshaking unlock bypass command sequence required prior this command sequence. system read program non-erasing blocks when erase suspend mode. system enter autoselect mode when erase suspend mode. erase suspend command valid only during block erase operation, requires bank address. erase/program resume command valid only during erase/program suspend mode, requires bank address. This mode used only enable Data Read suspending Program operation. ABP(Address block protected unprotected) either VIH, unprotected VIL,
protected.
Command valid when device Read mode Autoselect mode. "Set Burst Mode Configuration Register" details.
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DEVICE OPERATION
Preliminary MEMORY
write command command sequence (which includes programming data device erasing blocks memory), system must drive CLK, when providing address data. device provide unlock bypass mode save program time program operation. Unlike standard program command sequence which comprised four cycles, only program cycles required program word unlock bypass mode. block, multiple blocks, entire device erased. Table indicates address space that each block occupies. device's address space divided into sixteen banks: Bank contains boot/parameter blocks, other banks(from Bank consist uniform blocks. "bank address" address bits required uniquely select bank. Similarly, "block address" address bits required uniquely select block. ICC2 Characteristics table represents active current specification write mode. Characteristics section contains timing specification tables timing diagrams write operations.
Read Mode
device automatically enters asynchronous read mode after device power-up. commands required retrieve data asynchronous mode. After completing Internal Program/Erase Routine, each bank ready read array data. reset command required return bank read(or erase-suspend-read)mode goes high during active program/erase operation, bank autoselect mode. synchronous(burst) mode will automatically enabled first rising edge input while held low. That means device enters burst read mode from asynchronous read mode burst read mode using signal. When burst read finished(or terminated), device return asynchronous read mode automatically.
Asynchronous Read Mode
asynchronous read mode valid address should asserted A0-A22, while driving VIL. should remain data will appear DQ0-DQ15. Since memory array divided into sixteen banks, each bank remains enabled read access until command register contents altered. Address access time (tAA) equal delay from valid addresses valid output data. chip enable access time(tCE) delay from falling edge valid data outputs. output enable access time(tOE) delay from falling edge valid data output. prevent memory content from spurious altering during power transition, initial state machine reading array data upon device power-up, after hardware reset.
Synchronous (Burst) Read Mode
device capable continuous linear burst operation linear burst operation preset length. burst mode, system should determine many clock cycles desired initial word(tIACC) each burst access what mode burst operation desired using "Burst Mode Configuration Register" command sequences. "Set Burst Mode Configuration" further details. status data also read during burst read mode using signal with bank address. initiate synchronous read again, address pulse needed after host completed status reads device completed program erase operation. Continuous Linear Burst Read synchronous(burst) mode will automatically enabled first rising edge input while held low. Note that device enabled asynchronous mode when first powers initial word output tIAA after rising edge first cycle. Subsequent words output after rising edge each successive clock cycle, which automatically increments internal address counter. Note that device internal address boundary that occurs every words. When device crossing first word boundary, additional clock cycles needed before data appears next address. number addtional clock cycle varies from zero three cycles, exact number additional clock cycle depends starting address burst read.(Refer Figure output indicates this condition system pulsing low. device will continue output sequential burst data, wrapping around address 000000h after reaches highest addressable memory location until system asserts high, RESET conjunction with address.(See Table reset command does terminate burst read operation. host system crosses bank boundary while reading burst mode, accessed bank programming erasing, additional clock cycles needed previously mentioned. host system crosses bank boundary while accessed bank programming erasing, that busy bank, synchronous read will terminated.
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Preliminary MEMORY
8-,16-Word Linear Burst Read well Continuous Linear Burst Mode, there two(8 word) linear wrap no-wrap mode, which fixed number words read from consecutive addresses. these modes, addresses burst read determined group within which starting address falls. groups sized according number words read single burst sequence given mode.(See Table.
Table Burst Address Groups(Wrap mode only)
Burst Mode word word Group Size words 16words Group Address Ranges 0-7h, 8-Fh, 10-17h, 0-Fh, 10-1Fh, 20-2Fh,
example: wrap mode case, starting address 8-word mode address range read would 0-7h, wrap burst sequence would 2-3-4-5-6-7-0-1h. burst sequence begins with starting address written device, wraps back first address selected group. similar manner, 16-word wrap mode begin their burst sequence starting address written device, then wrap back first address selected address group. no-wrap mode case, starting address 8-word mode no-wrap burst sequence would 2-3-4-5-6-7-8-9h. burst sequence begins with starting address written device, continue address from starting address. similar manner, 16-word no-wrap mode begin their burst sequence starting address written device, continue 16th address from starting address. Also, when address cross word boundary no-wrap mode, same number additional clock cycles continuous linear mode needed.
Programmable Wait State
programmable wait state feature indicates device number additional clock cycles that must elapse after driven active burst read mode. Upon power number total initial access cycles defaults seven.
Handshaking
handshaking feature allows host system simply monitor signal from device determine when initial word burst data ready read. number initial cycle optimal burst mode, host should programmable wait state configuration.(See "Set Burst Mode Configuration Register" details.) rising edge after goes indicates initial word valid burst data. Using autoselect command sequence handshaking feature verified device.
Burst Mode Configuration Register
device uses configuration register various burst parameters number initial cycles burst burst read mode. burst mode configuration register must before device enter burst mode. burst mode configuration register loaded with three-cycle command sequences. third cycle, data should C0h, address bits A11-A0 should 555h, address bits A18-A12 code latched. device will power after hardware reset with default setting.
Table Burst Mode Configuration Register Table
Address Burst Read Mode Programmable Wait State Function Active Settings(Binary) active clock cycle before data active with data(default) Continuous(default) 8-word linear with wrap 16-word linear with wrap 8-word linear with no-wrap 16-word linear with no-wrap Reserve Data valid active edge after transition Data valid active edge after transition Data valid active edge after transition Data valid active edge after transition (default) Reserve Reserve Reserve Reserve
Programmable Wait State Configuration
This feature informs device number clock cycles that must elapse after AVD# driven active before data will available. This value determined input frequency device. Address bits A14-A12 determine setting. (See Burst Mode Configuration Register Table)
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Preliminary MEMORY
Programmable wait state setting instructs device particular number clock cycles initial access burst mode. Note that hardware reset will wait state default setting, that initial cycles.
Burst Read Mode Setting
device supports five different burst read modes continuous linear mode, word linear burst modes with wrap word linear burst modes with no-wrap.
Configuration
default, will high whenever there valid data output. device that goes active data cycle before active data. Address determine this setting. Note that always high with valid data case word boundary crossing.
Table Burst Address Sequences
Start Addr. Wrap No-wrap Burst Address Sequence(Decimal) Continuous Burst 0-1-2-3-4-5-6. 1-2-3-4-5-6-7. 2-3-4-5-6-7-8. 0-1-2-3-4-5-6. 1-2-3-4-5-6-7. 2-3-4-5-6-7-8. 8-word Burst 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 16-word Burst 0-1-2-3-4-.-13-14-15 1-2-3-4-5-.-14-15-0 2-3-4-5-6-.-15-0-1 0-1-2-3-4-.-13-14-15 1-2-3-4-5-.-14-15-16 2-3-4-5-6-.-15-16-17
Autoselect Mode
writing autoselect command sequences system, device enters autoselect mode. This mode read only asynchronous read mode. system then read autoselect codes from internal register(which separate from memory array). Standard asynchronous read cycle timings apply this mode. device offers Autoselect mode identify manufacturer device type reading binary code. addition, this mode allows host system verify block protection unprotection. Table shows address data requirements. autoselect command sequence written address within bank that read mode, erase-suspend-read mode program-suspend-read mode. autoselect command written while device actively programming erasing device. autoselect command sequence initiated first writing unlock cycles. This followed third write cycle that contains address autoselect command. Note that block address needed verification block protection. system read address within same bank number times without initiating another autoselect command sequence. burst read should prohibited during Autoselect Mode. terminate autoselect operation, write Reset command(F0H) into command register.
Table Autoselct Mode Description
Description Manufacturer Device Block Protection/Unprotection revision Handshaking Address (DA) (DA) (BA) (DA) Read Data 22F4H(Top Boot Block), 22F5H(Bottom Boot Block) (protected), (unprotected) handshaking, non-handshaking
Standby Mode
When RESET inputs both held 0.2V system reading writing, device enters Stand-by mode minimize power consumption. this mode, device outputs placed high impedence state, independent input. When device either these standby modes, device requires standard access time (tCE read access before ready read data. device deselected during erasure programming, device draws active current until operation completed. ICC5 Characteristics table represents standby current specification.
Automatic Sleep Mode
device features Automatic Sleep Mode minimize device power consumption during both asynchronous burst mode. When addresses remain stable tAA+60ns, device automatically enables this mode. automatic sleep mode independent control signals. sleep mode, output data latched always available system. When addresses changed, device provides data without wait time. Automatic sleep mode current equal standby mode current.
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Output Disable Mode
Preliminary MEMORY
When input output from device disabled. outputs placed high impedance state.
Block Protection Unprotection
protect block from accidental writes, block protection/unprotection command sequence used. power blocks device protected. unprotect block, system must write block protection/unprotection command sequence. first cycles written: addresses don't care data 60h. Using third cycle, block address (ABP) command (60h) written, while specifying with addresses whether that block should protected VIL, VIH, VIL) unprotected VIH, VIH, VIL). After third cycle, system continue protect unprotect additional cycles, exit sequence writing (reset command). device offers three types data protection block level: block protection/unprotection command sequence disables re-enables both program erase operations block. When VIL, outermost blocks protected. When VIL, blocks protected. Note that user never float that always connected with VIH, VIL.
Hardware Reset
device features hardware method resetting device RESET input. When RESET held low(VIL) least period tRP, device immediately terminates operation progress, tristates outputs, ignores read/write commands duration RESET pulse. device also resets internal state machine asynchronous read mode. ensure data integrity, interrupted operation should reinitiated once device ready accept another command sequence. previously noted, when RESET held 0.2V, device enters standby mode. RESET tied system reset pin. system reset occurs during Internal Program Erase Routine, device will automatically reset asynchronous read mode; this will enable systems microprocessor read boot-up firmware from Flash memory. RESET asserted during program erase operation, device requires time tREADY (during Internal Routines) before device ready read data again. RESET asserted when program erase operation executing, reset operation completed within time tREADY (not during Internal Routines). needed read data after RESET returns VIH. Refer Characteristics tables RESET parameters Figure timing diagram.
Software Reset
reset command provides that bank reseted read mode, erase-suspend-read mode program-suspend-read mode. addresses Don't Care state. reset command written between sequence cycles erase command sequence before erasing begins, program command sequence before programming begins. device begins erasure programming, reset command ignored until operation completed. program command sequence written bank that Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode. reset command valid between sequence cycles autoselect command sequence. autoselect mode, reset command must written return read mode. bank entered autoselect mode while Erase Suspend mode, writing reset command returns that bank erase-suspend-read mode. Also, bank entered autoselect mode while Program Suspend mode, writing reset command returns that bank program-suspend-read mode. goes high during program erase operation, writing reset command returns banks read mode. erase-suspend-read mode bank Erase Suspend)
Program
device programmed units word. Programming writing into memory array executing Internal Program Routine. order perform Internal Program Routine, four-cycle command sequence necessary. first cycles unlock cycles. third cycle assigned program setup command. last cycle, address memory location data programmed that location written. device automatically generates adequate program pulses verifies programmed cell margin Internal Program Routine. During execution Routine, system required provide further controls timings. During Internal Program Routine, commands written device will ignored. Note that hardware reset during program operation will cause data corruption corresponding location.
Accelerated Program Operation
device provides accelerated program operations through input. Using this mode, faster manufacturing throughput factory possible. When asserted input, device automatically enters Unlock Bypass mode, temporarily unprotects protected blocks, uses higher voltage input reduce time required program operations. accelerated program mode, system would two-cycle program command sequence. removing returns device normal operation mode.
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Unlock Bypass
Preliminary MEMORY
device provides unlock bypass mode save operation time. This mode possible program, block erase chip erase operation. There methods enter unlock bypass mode. mode invoked unlock bypass command sequence assertion pin. Unlike standard program/erase command sequence that contains four cycles, unlock bypass program/erase command sequence comprises only cycles. unlock bypass mode engaged issuing unlock bypass command sequence which comprised three cycles. Writing first unlock cycles followed third cycle containing unlock bypass command (20H). Once device unlock bypass mode, unlock bypass program/erase command sequence necessary. unlock bypass program command sequence comprised only cycles; writing unlock bypass program command (A0H) followed program address data. This command sequence only valid programming device unlock bypass mode. Also, unlock bypass erase command sequence comprised cycles; writing unlock bypass block erase command(80H-30H) writing unlock bypass chip erase command(80H-10H). This command sequences only valid ones erasing device unlock bypass mode. unlock bypass reset command sequence only valid command sequence exit unlock bypass mode. unlock bypass reset command sequence consists cycles. first cycle must contain data (90H). second cycle contains only data (00H). Then, device returns read mode. enter unlock bypass mode hardware level, also used. assertion pin, device enters unlock bypass mode. Also, blocks temporarily unprotected when device using unlock bypass mode. exit unlock bypass mode, just remove asserted from pin.(Note that user never float Vpp, that always connected with VIH, VID.).
Chip Erase
erase chip write into entire memory array executing Internal Erase Routine. Chip Erase requires cycles write command sequence. erase set-up command written after first "unlock" cycles. Then, there more write cycles prior writing chip erase command. Internal Erase Routine automatically pre-programs verifies entire memory zero data pattern prior erasing. automatic erase begins rising edge last pulse command sequence terminates when "1". After that device returns read mode.
Block Erase
erase block write into desired memory block executing Internal Erase Routine. Block Erase requires cycles write command sequence shown Table After first "unlock" cycles, erase setup command (80H) written third cycle. Then there more "unlock" cycles followed Block Erase command. Internal Erase Routine automatically pre-programs verifies entire memory prior erasing Multiple blocks erased sequentially writing sixth bus-cycle. Upon completion last cycle Block Erase, additional block address Block Erase command (30H) written perform Multi-Block Erase. Multi-Block Erase, only sixth cycle(block address 30H) needed.(Similarly, only second cycle needed unlock bypass block erase.) 50us (typical) "time window" required between Block Erase command writes. Block Erase command must written within 50us "time window", otherwise Block Erase command will ignored. 50us "time window" reset when falling edge occurs within 50us "time window" latch Block Erase command. During 50us "time window", command other than Block Erase Erase Suspend command written device will reset device read mode. After "time window", Block Erase command will initiate Internal Erase Routine erase selected blocks. Block Erase address command following exceeded "time window" accepted. other commands will recognized except Erase Suspend command during Block Erase operation.
Erase Suspend Resume
Erase Suspend command interrupts Block Erase read program data block that being erased. Also, possible protect unprotect block that being erased erase suspend mode. Erase Suspend command only valid during Block Erase operation including time window Erase Suspend command valid while Chip Erase Internal Program Routine sequence running. When Erase Suspend command written during Block Erase operation, device requires maximum us(recovery time) suspend erase operation. Therefore system must wait 20us(recovery time) read data from bank which include block being erased. Otherwise, system read data immediately from bank which don't include block being erased without recovery time(max. 20us) after Erase Suspend command. And, after maximum 20us recovery time, device availble programming data block that being erased. But, when Erase Suspend command written during block erase time window device immediately terminates block erase time window suspends erase operation. system also write autoselect command sequence when device Erase Suspend mode. When Erase Resume command executed, Block Erase operation will resume. When Erase Suspend Erase Resume command executed, addresses Don't Care state.
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Program Suspend Resume
Preliminary MEMORY
device provides Program Suspend/Resume mode. This mode used enable Data Read suspending Program operation. device accepts Program Suspend command Program mode(including Program operations performed during Erase Suspend) other commands ignored. After input Program Suspend command, needed enter Program Suspend Read mode. Therefore system must wait 2us(recovery time) read data from block being programmed. Otherwise, system read data immediately from block(except block being programmed) without recovery time after Program Suspend command. Like Erase Suspend mode, device returned Program mode using Program Resume command.
Read While Write Operation
device capable reading data from bank while writing other banks. This called Read While Write operation. erase operation also suspended read from program another location within same bank(except block being erased). Read While Write operation prohibited during chip erase operation. Figure shows read write cycles initiated simultaneous operation with zero latency. Refer Characteristics table read-while-write current specifications.
Write Inhibit
avoid initiation write cycle during power-up power-down, write cycle locked less than VLKO. VLKO (Lock-Out Voltage), command register internal program/erase circuits disabled. Under this condition device will reset itself read mode.Subsequent writes will ignored until level greater than VLKO. user's responsibility ensure that control pins logically correct prevent unintentional writes when above VLKO.
Write Pulse "Glitch" Protection
Noise pulses less than (typical) initiate write cycle.
Logical Inhibit
Write cycles inhibited holding VIH. initiate write cycle, must logical zero while logical one.
Power-up Protection
avoid initiation write cycle during power-up, RESET must asserted during Power-up. After RESET goes high. device reset read mode.
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FLASH MEMORY STATUS FLAGS
Preliminary MEMORY
device means indicate status operation bank where program erase operation processes. Address must include bank address being executed internal routine operation. status indicated raising device status flag corresponding pins. This status read supported burst mode asynchronous mode. status data read during burst read mode using signal with bank address. That means status read supported synchronous mode. status read performed, data provided burst read identical data initial access. initiate synchronous read again, address pulse needed after host completed status reads device completed program erase operation. corresponding pins DQ7, DQ6, DQ5, DQ2.
Table Hardware Sequence Flags
Status
Programming Block Erase Chip Erase Erase Suspend Read Erase Suspend Read Progress Erase Suspend Program Program Suspend Read Program Suspend Read Programming Exceeded Time Limits Block Erase Chip Erase Erase Suspend Program Erase Suspended Block Non-Erase Suspended Block Non-Erase Suspended Block Program Suspended Block Non- program Suspended Block
Data Data
Toggle Toggle Data Toggle Data Toggle Toggle Toggle
Data Data
Data Data
Toggle Toggle (Note Data Toggle (Note Data Toggle (Note Toggle
Notes will toggle when device performs successive read operations from erase/program suspended block. High (exceeded timing limits), successive reads from problem block will cause toggle.
Data Polling
When attempt read device made while executing Internal Program, complement data written indication Routine progress. When Routine completed attempt access device will produce true data written DQ7. When user attempts read block being erased, will low. device placed Erase/Program Suspend Mode, status detected pin. system tries read address which belongs block that being erase suspended, will high. And, system tries read address which belongs block that being program suspended, output will true data itself. non-erase-suspended non-program-suspended block address read, device will produce true data DQ7. attempt made program protected block, outputs complements data approximately device then returns Read Mode without changing data block. attempt made erase protected block, outputs complement data approximately 100us device then returns Read Mode without erasing data block.
Toggle
Toggle another option detect whether Internal Routine progress completed. Once device busy state, will toggle. Toggling will stop after device completes Internal Routine. device Erase/Program Suspend Mode, attempt read address that belongs block that being erased programmed will produce high output DQ6. address belongs block that being erased programmed, toggling halted valid data produced DQ6. attempt made program protected block, toggles approximately device then returns Read Mode without changing data block. attempt made erase protected block, toggles approximately 100µs device then returns Read Mode without erasing data block.
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Exceed Timing Limits
Preliminary MEMORY
Internal Program/Erase Routine extends beyond timing limits, will High, indicating program/erase failure.
Block Erase Timer
status multi-block erase operation detected pin. will High 50µs block erase time window expires. this case, Internal Erase Routine will initiate erase operation.Therefore, device will accept further write commands until erase operation completed. block erase time window expired. Within block erase time window, additional block erase command (30H) accepted. confirm that block erase command been accepted, software check status following each block erase command.
Toggle
device generates toggling pulse only Internal Erase Routine Erase/Program Suspend progress. When device executes Internal Erase Routine, toggles only erasing block read. Although Internal Erase Routine Exceeded Time Limits, toggles only erasing block Exceeded Time Limits read. When device Erase/Program Suspend mode, toggles only address erasing programming block read. non-erasing nonprogrammed block address read during Erase/Program Suspend mode, then will produce valid data. will High user tries program non-erase suspend block while device Erase Suspend mode.
RDY: Ready
Normally signal used indicate burst data available rising edge clock cycle not. state, data valid expected time, high state, data valid. Note that, high, high state.
Start
Start
Data
Toggle
Data
Toggle
Fail
Pass
Fail
Pass
Figure Data Polling Algorithms
Figure Toggle Algorithms
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Commom Flash Memory Interface
Preliminary MEMORY
Common Flash Momory Interface contrived increase compatibility host system software. provides specific information device, such memory size electrical features. Once this information been obtained, system software will know which command sets enable flash writes, block erases, control flash component. When system writes command(98H) address device enters mode. then system writes address shown Table system read data. Query data always presented lowest-order data outputs(DQ0-7) only. word(x16) mode, upper data outputs(DQ8-15) 00h. terminate this operation, system must write reset command.
Table Common Flash Memory Interface Code
Description Addresses (Word Mode) Data 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0017H 0019H
Query Unique ASCII string "QRY"
Primary Command Address Primary Extended Table Alternate Command (00h none exists) Address Alternate Extended Table (00h none exists) Min. (write/erase) D7-D4: volt, D3-D0: millivolt Max. (write/erase) D7-D4: volt, D3-D0: millivolt Vpp(Acceleration Program) Supply Minimum Supported, Volt, 100mV Vpp(Acceleration Program) Supply Maximum Supported, Volt, 100mV Typical timeout single word write Typical timeout Min. size buffer write us(00H supported) Typical timeout individual block erase Typical timeout full chip erase ms(00H supported) Max. timeout word write times typical Max. timeout buffer write times typical Max. timeout individual block erase times typical Max. timeout full chip erase times typical(00H supported) Device Size byte Flash Device Interface description Max. number byte multi-byte write Number Erase Block Regions within device
0085H
0095H 0004H 0000H 000AH 0012H 0005H 0000H 0004H 0000H 0018H 0000H 0000H 0000H 0000H 0002H
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Table Common Flash Memory Interface Code (Continued)
Description Erase Block Region Information Bits 0~15: y+1=block number Bits 16~31: block size= 256bytes
Preliminary MEMORY
Addresses (Word Mode)
Data 0007H 0000H 0020H 0000H 00FEH 0000H 0000H 0001H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0050H 0052H 0049H 0031H 0030H 0000H
Erase Block Region Information
Erase Block Region Information
Erase Block Region Information
Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1-0) Required, Required Silcon Revision Number(Bits 7-2) Erase Suspend Supported, Read Only, Read Write Block Protect Supported, Supported Block Temporary Unprotect Supported, Supported Block Protect/Unprotect scheme Supported, Supported Simultaneous Operation Supported, Supported Burst Mode Type Supported, Supported Page Mode Type Supported, Word Page Word Page Top/Bottom Boot Block Flag Bottom Boot Device, Boot Device Max. Operating Clock Frequency (MHz RWW(Read While Write) Functionality Restriction (00H exists exists) Handshaking Supported both mode, Supported Sync. Mode Supported Async. Mode, Supported both Mode
0002H 0001H 0000H 0001H 0001H 0001H 0000H 0003H 0042H 0000H 0001H
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage relative Other Pins Temperature Under Bias Storage Temperature Short Circuit Output Current Operating Temperature Commercial Extended Tstg (Commercial Temp.) (Extended Temp.) Tbias Symbol Rating -0.5 +2.5 -0.5 +9.5 -0.5 +2.5 +125 +125 +150
Preliminary MEMORY
Unit
Notes Minimum voltage -0.5V Input/ Output pins. During transitions, this level fall -2.0V periods <20ns. Maximum voltage Vcc+0.6V input output pins which, during transitions, overshoot Vcc+2.0V periods <20ns. Minimum input voltage -0.5V During transitions, this level fall -2.0V periods <20ns. Maximum input voltage +9.5V which, during transitions, overshoot +12.0V periods <20ns. Permanent device damage occur ABSOLUTE MAXIMUM RATINGS exceeded. Functional operation should restricted conditions detailed operational sections this data sheet. Exposure absolute maximum rating conditions extended periods affect reliability.
RECOMMENDED OPERATING CONDITIONS Voltage reference
Parameter Supply Voltage Supply Voltage Symbol Typ. Unit
CHARACTERISTICS
Parameter Input Leakage Current Leakage Current Output Leakage Current Active Burst Read Current Active Asynchronous Read Current Active Write Current (Note Read While Write Current Accelerated Program Current Standby Current Standby Current During Reset Automatic Sleep Mode(Note Input Voltage Input High Voltage Output Voltage Output High Voltage Voltage Accelerated Program Lock-out Voltage Symbol ILIP ICCB1 ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VLKO VCC=VCCmin -100 VCC=VCCmin Test Conditions VIN=VSS VCC, VCC=VCCmax VCC=VCCmax VPP=9.5V VOUT=VSS VCC, VCC=VCCmax, OE=VIH CE=VIL, OE=VIH CE=VIL, OE=VIH 10MHz 1MHz -0.5 VCC-0.4 VCC-0.1 VCC+0.4 Unit
CE=VIL, OE=VIH, WE=VIL, VPP=VIH CE=VIL, OE=VIH CE=VIL, OE=VIH VPP=9.5V RESET=VCC 0.2V RESET 0.2V CE=VSS 0.2V, Other Pins=VIL 0.2V, 0.2V
Notes: Maximum specifications tested with VCCmax. active while Internal Erase Internal Program progress. Device enters automatic sleep mode when addresses stable 60ns.
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CAPACITANCE(TA 1.8V, 1.0MHz)
Item Input Capacitance Output Capacitance Control Capacitance Symbol COUT CIN2 Test Condition VIN=0V VOUT=0V
Preliminary MEMORY
Unit
VIN=0V
Note Capacitance periodically sampled 100% tested.
TEST CONDITION
Parameter Input Pulse Levels Input Rise Fall Times Input Output Timing Levels Output Load Value
VCC/2
30pF
VCC/2 Input Output Test Point VCC/2
Device Under Test
30pF including scope capacitance Input Pulse Test Point
Output Load
CHARACTERISTICS Synchronous/Burst Read
Parameter Initial Access Time Burst Access Time Valid Clock Output Delay Setup Time Hold Time from High Address Setup Time Address Hold Time from Data Hold Time from Next Clock Cycle Output Enable Data Output Enable valid Disable High Disable High Setup Time Setup Time Setup Time High Time Fall Rise Time Symbol tIAA tAVDS tAVDH tAVDO tACS tACH tBDH tOER tCEZ tOEZ tCES tRDYA tRDYS tCH/L tCHCL MHz) 88.5 14.5 14.5 14.5 MHz) Unit
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SWITCHING WAVEFORMS
cycles initial access shown. setting A14=0, A13=0, A12=1 tCES 15.2 typ.
Preliminary MEMORY
tCEZ
tAVDS tAVDH tACS A0-A22 tACH DQ0-DQ15 tIAA tOER Hi-Z tRDYA tRDYS Da+1 Da+2 Da+3 tBDH
Hi-Z Da+n tOEZ
Hi-Z
Figure Burst Mode Read MHz)
Note: order avoid conflict signal enabled next rising edge after going high. cycles initial access shown. setting A14=0, A13=0, A12=1 tCES 18.5 typ. tCEZ
tAVDS tAVDH tACS A0-A22 tACH DQ0-DQ15 tIAA tOER Hi-Z tRDYA tRDYS Da+1 Da+2 Da+3 tBDH
Hi-Z Da+n tOEZ
Hi-Z
Figure Burst Mode Read MHz)
Note: order avoid conflict signal enabled next rising edge after going high.
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SWITCHING WAVEFORMS
cycles initial access shown. setting A14=0, A13=0, A12=1 tCES 15.2 typ.
Preliminary MEMORY
tAVDS tAVDH tACS A0-A22 tACH DQ0-DQ15 tIAA tOER Hi-Z tRDYA tRDYS tBDH
Figure word Linear Burst Mode with Wrap Around MHz)
Note: order avoid conflict signal enabled next rising edge after going high.
cycles initial access shown. setting A14=0, A13=0, A12=1 tCES 15.2 typ.(66MHz)
tAVDS tAVDH tACS A0-A22 tACH DQ0-DQ15 tIAA tOER Hi-Z tRDYA tRDYS tBDH
Figure word Linear Burst with Cycle Before Data setting A18=1)
Note: order avoid conflict signal enabled next rising edge after going high.
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SWITCHING WAVEFORMS
cycles initial access shown. setting A14=0, A13=0, A12=1 tCES 15.2 typ(66MHz).
Preliminary MEMORY
tCEZ
tAVDS tAVDH tACS A0-A22 tACH DQ0-DQ15 tIAA tOER Hi-Z tRDYA tRDYS tBDH
Hi-Z tOEZ
Figure word Linear Burst Mode Wrap Case)
Hi-Z
Note: order avoid conflict signal enabled next rising edge after going high.
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CHARACTERISTICS Asynchronous Read
Preliminary MEMORY
Parameter
Access Time from Asynchronous Access Time Time Output Enable Output Valid Read Output Enable Hold Time Toggle Data Polling
Symbol
tAVDP
88.5 88.5
Unit
tOEH
tOEZ
Output Disable High Z(Note
Note: 100% tested.
SWITCHING WAVEFORMS
Asynchronous Mode Read
tOEH
Valid
tOEZ
DQ0-DQ15
A0-A22
Figure Asynchronous Mode Read
Note: VA=Valid Read Address, RD=Read Data.
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CHARACTERISTICS
Hardware Reset(RESET)
Parameter
RESET Low(During Internal Routines) Read Mode (Note) RESET Low(NOT During Internal Routines) Read Mode (Note) RESET Pulse Width Reset High Time Before Read (Note) RESET Standby Mode
Preliminary MEMORY
Symbol
tReady tReady tRPD
Speed Options
Unit
Note: 100% tested.
SWITCHING WAVEFORMS
RESET tReady
Reset Timings during Internal Routines
tReady
RESET
Reset Timings during Internal Routines
Figure Reset Timings
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CHARACTERISTICS Erase/Program Operation
Parameter
Cycle Time(Note Address Setup Time(Note Address Hold Time(Note Data Setup Time Data Hold Time Read Recovery Time Before Write Setup Time Hold Time Pulse Width Pulse Width High Latency Between Read Write Operations Word Programming Operation Accelerated Programming Operation Block Erase Operation (Note Rise Fall Time Setup Time (During Accelerated Programming) Setup Time
Preliminary MEMORY
Symbol
tGHWL tWPH tSR/W tPGM tACCPGM tBERS tVPP tVPS tVCS
11.5
Unit
Notes: 100% tested. write timing, addresses latched falling edge include preprogramming time.
FLASH Erase/Program Performance
Limits Parameter Min. Kword Block Erase Time Kword Chip Erase Time Accelerated Chip Erase Time Word Programming Time Accelerated Word Programming Time Chip Programming Time Accelerated Chip Programming Time Erase/Program Endurance (Note 100,000 11.5 Cycles Minimum 100,000 cycles guaranteed Bank Excludes system level overhead Excludes programming prior erasure Typ. Max. Unit Comments
Notes: 25°C, 1.8V, 100,000 cycles, typical pattern. System-level overhead defined time required execute four cycle command necessary program each word. preprogramming step Internal Erase Routine, words programmed before erasure. 100K Program/Erase Cycle Bank
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SWITCHING WAVEFORMS Program Operations
Preliminary MEMORY
Program Command Sequence (last cycles) A0:A22 555h
Read Status Data
DQ0-DQ15
Progress
Complete
tWPH tVCS tPGM
Notes:
Program Address, Program Data, Valid Address reading status bits. progress" "complete" refer status program operation. A16-A22 don't care during command sequence unlock cycles. Status reads this figure asynchronous read, status read synchronous mode also supported.
Figure Program Operation Timing
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SWITCHING WAVEFORMS Erase Operation
Erase Command Sequence (last cycles) A0:A22 2AAh 555h chip erase chip erase DQ0-DQ15
Preliminary MEMORY
Read Status Data
Progress
Complete
tWPH tVCS tBERS
Notes:
block address Block Erase. Address bits A16-A22 don't cares during unlock cycles command sequence. Status reads this figure asynchronous read, status read synchronous mode also supported.
Figure Chlp/Block Erase Operations
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SWITCHING WAVEFORMS Unlock Bypass Program Operations(Accelerated Program)
Preliminary MEMORY
A0:A22
DQ0-DQ15
Don't Care
Don't Care
Don't Care
tVPS
tVPP
Unlock Bypass Block Erase Operations
A0:A22
555h chip erase chip erase Don't Care
DQ0-DQ15
Don't Care
Don't Care
tVPS
Notes:
tVPP
left high subsequent programming pulses. setup hold times from conventional program operations. Unlock Bypass Program/Erase commands used when applied Vpp.
Figure Unlock Bypass Operation Timings
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SWITCHING WAVEFORMS Data Polling Operations
tCES
Preliminary MEMORY
tAVDS tAVDH A0-A22 tACS tACH DQ0-DQ15 tIAA Hi-Z
Notes:
Valid Address. When Internal Routine operation complete, Data Polling will output true data.
Figure Data Polling Timings (During Internal Routine)
Toggle Operations
tCES
Status Data
Status Data
tRDYS
tAVDS tAVDH tACS A0-A22 tACH DQ0-DQ15 tIAA Hi-Z
Notes:
Valid Address. When Internal Routine operation complete, toggle bits will stop toggling.
Status Data
Status Data
tRDYS
Figure Toggle Timings(During Internal Routine)
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SWITCHING WAVEFORMS Read While Write Operations
Preliminary MEMORY
Last Cycle Program Block Erase Command Sequence
Read status same bank and/or array data from other bank
Begin another Program Erase Command Sequences
tOEH tWPH DQ0-DQ15 PD/30h tSR/W tOEH tGHWL
A0-A22
PA/BA
555h
Figure Read While Write Operation
Note: Breakpoints waveforms indicate that system alternately read array data from "non-busy bank" checking status program erase operation "busy" bank.
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Crossing First Word Boundary Burst Read Mode
Preliminary MEMORY
additional clock insertion word boundary needed only first crossing word boundary. This means that addtional clock cycle needed from word boundary crossing continuous burst read. Also, number addtional clock cycle first word boundary varies from zero three cycles, exact number additional clock cycle depends starting address burst read. rule determine additional clock cycle follows. addresses divided into groups. applied rule "The residue obtained when address divided "two bits address". Using this rule, address divided different groups shown below table. simplicity terminology, "4N" stands address which residue "0"(or bits "00") "4N+1" address which residue "1"(or bits "01"), etc. additional clock cycles first word boundary crossing zero, one, three when burst read start from "4N" address, "4N+1" address, "4N+2" address "4N+3" address respectively.
Starting Address Additional Clock Cycles first word boundary
Srarting Address Group Burst Read 4N+1 4N+2 4N+3 Residue (Address/4) Bits Address Additional Clock Cycles First Word Boundary Crossing cycle cycle cycles cycles
Case Start from "4N" address group
cycle initial access shown.(54MHz case)
A0-A22 Data
Additional Cycle First Word Boundary
tCEZ
tOER tOEZ
Notes:
Address boundry occurs every words beginning address 00000FH 00001FH 00002FH etc. Address 000000H also boundry crossing. additional clock cycles needed except boundary crossing.
Figure Crossing first word boundary burst read mode.
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Case2 Start from "4N+1" address group
Preliminary MEMORY
cycle initial access shown.(54MHz case)
A0-A22 Data
Additional Cycle First Word Boundary
tCEZ
tOER tOEZ
Case Start from "4N+2" address group
cycle initial access shown.(54MHz case)
A0-A22 Data
Additional Cycle First Word Boundary
tCEZ
tOER tOEZ
Notes:
Address boundry occurs every words beginning address 00000FH 00001FH 00002FH etc. Address 000000H also boundry crossing. additional clock cycles needed except boundary crossing.
Figure Crossing first word boundary burst read mode.
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Preliminary MEMORY
Case4 Start from "4N+3" address group
cycle initial access shown.(54MHz case)
A0-A22 Data
Additional Cycle First Word Boundary
tCEZ
tOER tOEZ
Notes:
Address boundry occurs every words beginning address 00000FH 00001FH 00002FH etc. Address 000000H also boundry crossing. additional clock cycles needed except boundary crossing.
Figure Crossing first word boundary burst read mode.
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Preliminary MEMORY
64Mb(4Mbx16) Synchronous Burst UtRAM B-die
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POWER SEQUENCE
Apply power. Maintain stable power(Vcc min.=2.5V) minimum 200µs with high.
Preliminary MEMORY
TIMING WAVEFORM POWER
200µs
VCC(Min) VCCQ(Min) VCCQ Min.
Min. 200µs
Min.
Power Mode
(POWER
Normal Operation
After reaches VCC(Min.), wait 200µs with high. Then device gets into normal operation.
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FUNCTIONAL DESCRIPTION ASYNCHRONOUS MODE(A15=0)
Preliminary MEMORY
DQ0~7 High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z High-Z
DQ8~15 High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z High-Z
Mode Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Mode Register
Power Standby Active Active Active Active Active Active Active Active Active
must high state. asynchronous mode, Clock ignored.
FUNCTIONAL DESCRIPTION SYNCHRONOUS MODE(A15=1)
DQ0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z High-Z
DQ8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z High-Z
Mode Deselected Deselected Output Disabled Output Disabled Read Add. Input Load
Power Standby Active Active Active Active Active Active Active Active Active Active
Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Mode Register
must high state. means "Don't care"(can low, high toggling).
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KBF0x0800M
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Power supply voltage relative Output power supply voltage relative Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VDDQ TSTG
Preliminary MEMORY
Ratings -0.2 VDD+0.3V -0.2 3.0V -0.2 2.5V
Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted used under recommended operating condition. Exposure absolute maximum rating conditions longer than second affect reliability.
STANDBY MODE STATE MACHINES
CS=VIH MRS=VIH Power Initial State (Wait 200µs) CS=VIL, LB=VIL WE=VIL, MRS=VIL Setting CS=VIL, LB=VIL MRS=VIH Active CS=VIH Standby Mode Mode
MRS=VIL
MRS=VIH NOTE Default mode after power Asynchronous mode enable. this default mode 100% guaranteed setting sequence highly recommended after power after getting mode. Synchronous operation needed, A15=1. more detail, please refer Mode Register Set(See Page 54). Once device gets mode, register settings initialized into default mode. entry mode, drive into over 0.5us(suspend period) during standby mode after setting been completed(A4=0). mode, drive into with wake sequence(See Page 69).
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RECOMMENDED OPERATING CONDITIONS1)
Item Power supply voltage power supply voltage Ground Input high voltage Input voltage
TA=-25 85°C, otherwise specified. Overshoot: VCC+1.0V case pulse width 20ns. Undershoot: -1.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
Preliminary MEMORY
Symbol VCCQ
-0.2
1.85
VDDQ+0.22)
Unit
CAPACITANCE1)(f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested.
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current Average operating current Output voltage Output high voltage Standby Current(CMOS) Deep Power Down
Symbol
Test Conditions VIN=Vss VCCQ CS=VIH, MRS=VIH, OE=VIH WE=VIL, VIO=Vss VCCQ Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, MRS=VIH, VIN=VIL IOL=0.1mA IOH=-0.1mA CSVCCQ-0.2V, MRSVCCQ-0.2V, Other inputs=Vss VCCQ MRS0.2V, CSVCCQ-0.2V, Other inputs=Vss VCCQ
Unit
ICC2 ISB1 ISBD
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DEVICE OPERATION
Preliminary MEMORY
device several modes Synchronous Burst Read mode, Asynchronous Write mode, Standby mode Deep Power Down(DPD) mode. Deep Power Down(DPD) mode defined through Mode Register Set(MRS) option. Mode Register Set(MRS) option also defines Burst Length, Burst Type First Access Latency Count Synchronous Burst Read mode. Mode Register, system must drive ADV, drive during valid address. into Standby mode, system must drive VIH. into Deep Power Down(DPD) mode, system must drive CMOS VIH(VCC-0.2V) CMOS VIL(0.2V).
Mode Register (MRS)
mode register stores data controlling various operation modes UtRAM. programs Deep Power Down(DPD) mode, Burst Length, Burst Type, First Access Latency Count various vendor specific options make UtRAM useful variety different applications. default values mode register defined, therefore unless user specifies specific modes, device runs default modes. user wants modes other than default modes, user should write specific mode value mode register after power mode register written driving ADV, driving during valid address. mode register divided into various fields depending fields functions. Deep Power Down(DPD) field uses Burst Length field uses A6~A7, Burst Type uses First Access Latency Count uses A9~A11. Refer Table below detailed Mode Register Setting. Mode Register Setting according field function Address Function An~A16 A14~A12 A11~A9 Latency A7~A6
NOTE RFU(Reserved Future Use), BT(Burst Type), BL(Burst Length), DPD(Deep Power Down), MS(Mode Select)
Mode Select Async./Sync. Async. Mode Sync. Mode
First Access Latency Count Latency Reserved Reserved Reserved Reserved
Burst Type Type Linear Interleave
Burst Length Length Reserved
Deep power Down Enable Disable
NOTE Default mode(when user does write specific value mode register) Async. mode enable. Even though device used work sync. mode, once device gets mode, register settings initialized into default mode.But this default mode 100% guaranteed setting sequence highly recommended after power after getting mode.
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Asynchronous Read Operation
Preliminary MEMORY
Asynchronous read operation starts when driven under valid address.(MRS should driven during asynchronous read operation)
Asynchronous Write Operation
Asynchronous write operation starts when driven under valid address.(MRS should driven during write operation.)
Asynchronous Write Operation Synchronous Mode
write operation starts when driven under valid address. Clock input does have affect write operation.(MRS should driven during write operation. toggling address latch driven VIL)
Synchronous Burst Read Operation
device supports Linear Synchronous Burst Read mode Interleave Synchronous Burst Read mode. optimized Burst Mode each system, system should determine many clock cycles desirable initial word each burst access(First Access Latency Count), many words device outputs access(Burst Length) which type burst operation(Burst Type Linear Interleave) desired.(See Table "Mode Register Set")
Clock(CLK)
clock input used reference synchronous burst read operation UtRAM. Synchronous burst read operation synchronized rising edge clock. clock transitions must swing between VIH.
First Access Latency Count
First Access Latency Count configuration tells device many clocks must elapse from de-assertion(VIH) before first data word should driven onto data pins. This value depends input clock frequency. supported Latency Count follows. Latency Count support Clock Frequency Latency Count First Access Latency Configuration
Upto 54MHz
Upto 40MHz
Clock
Address Latency Data Latency Data Latency Data Latency Data NOTE Other First Access Latency Configuration settings reserved. Only rising edge clock allowed during pulse
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Burst Sequence
Start Address Burst Address Sequence word Burst Linear 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleave 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 word Burst Linear 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Interleave 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Linear 0-1-2-3-4.14-15 1-2-3-4.14-15-0 2-3-4.14-15-0-1 3-4-5.15-0-1-2 4-5-6.15-0-1-2-3 5-6.15-0-1-2-3-4
Preliminary MEMORY
word Burst Interleave 0-1-2-3-4.14-15 1-0-3-2-5.15-14 2-3-0-1-6.12-13 3-2-1-0-7.13-12 4-5-6-7-0.10-11 5-4-7-6-1.11-10 6-7-4-5-2.8-9 7-6-5-4-3.9-8 14-15-12-13-10.0-1 15-14-13-12-11.1-0
6-7.15-0-1-2-3-4-5 7-8.15-0-1.5-6 14-15-0-1.12-13 15-0-1.12-13-14
Burst Stop
Burst stop used when system wants stop burst operation special purpose. driving during burst read operation, then burst operation will stopped. During burst read operation, burst operation issued. burst operation issued only after previous burst operation finished.
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OPERATING CONDITIONS
TEST CONDITIONS(Test Load Test Input/Output Reference)
Input pulse level: VCCQ-0.2V Input rising falling time: Input output reference voltage: VCCQ Output load: CL=50pF
Preliminary MEMORY
ASYNCHRONOUS CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V, TA=-25 85°C)
Parameter List Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Access Time Async. Read Chip Select Low-Z Output Enable Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Disable High-Z Output Output Disable High-Z Output Output Hold Write Cycle Time Chip Select Write Address Set-up Time Beginning Write Async. Write Address Valid Write Valid Write Write Pulse Width Write Recovery Time Data Write Time Overlap Data Hold from Write Time Enable Register Write Start Register Write Recovery Time Write Disable
tWP(min)=85ns continuous write operation over times.
Symbol tBLZ tOLZ tBHZ tOHZ tRWR 601)
Speed
Units
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ASYNCHRONOUS READ TIMING WAVEFORM
Preliminary MEMORY
TIMING WAVEFORM ASYNCHRONOUS READ CYCLE(1)(Address Controlled, CS=OE=VIL, MRS=WE=VIH, LB=VIL)
Address
Data
Data Valid
Previous Data Valid
TIMING WAVEFORM ASYNCHRONOUS READ CYCLE(2)(MRS=WE=VIH)
Address
tBHZ
Data
High-Z
tOLZ tBLZ Data Valid
tOHZ
(ASYNCHRONOUS READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection. tOE(max) only when becomes enabled after tAA(max). invalid address signals shorter than min. continuously repeated over 4us, device needs normal read timing(tRC) needs sustain standby state min. least once every 4us. asynchronous mode, Clock ignored.
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KBF0x0800M
ASYNCHRONOUS WRITE TIMING WAVEFORM
TIMING WAVEFORM WRITE CYCLE(1)(MRS=VIH, OE=VIH, Controlled)
Address
Preliminary MEMORY
tCW(2)
tWR(4)
tWP(1)
tAS(3)
Data
Data Valid
High-Z
High-Z
Data
High-Z
High-Z
TIMING WAVEFORM WRITE CYCLE(2)(MRS=VIH, OE=VIH, Controlled)
Address
tCW(2)
tWR(4)
tAS(3) tWP(1)
Data
Data Valid
Data (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends with going high. asynchronous mode, Clock ignored.
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KBF0x0800M
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Test Input/Output Reference)
Input pulse level: VCCQ-0.2V Input rising falling time: Input output reference voltage: VCCQ Output load: CL=50pF
Preliminary MEMORY
SYNCHRONOUS CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V, TA=-25 85°C, Maximum Main
Clock Frequency=54MHz) Parameter List Clock Cycle Time Address Set-up Time Falling Address Hold Time from Rising Setup Time Hold Time Setup Time Clock Rising Hold Time from Clock Sync. Burst Read High Pulse Width High Pulse Width Valid Latency Output Enable Latency Valid Low-Z Output Output Enable Low-Z Output Latency Clock Rising Edge Data Output Output Hold Output High-Z Write Cycle Time Address Set-up Time Falling Address Hold Time from Rising Setup Time Rising Address Set-up Time Beginning Write Write Recovery Time Async. Write Burst Read Clock Next Falling Chip Select Write Address Valid Write Valid Write Write Pulse Width High Pulse Width Data Write Time Overlap Data Hold from Write Time Enable Register Write Start Register Write Recovery Time Write Disable
tWP(min)=85ns continuous write operation over times. ADDRESS LATCH TYPE WRITE TIMING, same tAW.
Symbol tAS(R) tAH(R) tADVS tADVH tCSS(R) tCSLH tCSHP tADHP tBEL tOEL tBLZ tOLZ
WC2)
Speed Latency-1 clock
Units Clock Clock
18.5 601)
tAS(W) tAH(W) tCSS(W) tBEWA tWHP tRWR
Revision November 2003
KBF0x0800M
SYNCHRONOUS BURST READ TIMING WAVEFORM
Preliminary MEMORY
TIMING WAVEFORM BURST READ CYCLE(1) [Latency=5, Burst Length=4](WE=VIH, MRS=VIH)
tADVH tADVS
tADVH tADVS tAS(R)
Valid
tAS(R)
Address
tAH(R)
Don't Care
tAH(R)
Valid
tCSS(R)
tCSS(R)
tBEL
tBLZ tOEL
Latency
Data
tOLZ
Latency
Undefined
(SYNCHRONOUS BURST READ CYCLE) Only rising edge clock allowed during pulse. burst operation issued only after previous burst operation finished.
TIMING WAVEFORM BURST READ CYCLE(2) [Latency=5, Burst Length=4](WE=VIH, MRS=VIH)
tADVH tADVS
tAS(R)
Address
tAH(R)
Don't Care
Valid
tCSS(R)
tBEL
tBLZ tOEL
Latency
Data
tOLZ
Undefined
(SYNCHRONOUS BURST READ CYCLE) 1.Only rising edge clock allowed during pulse.
Revision November 2003
KBF0x0800M
BURST STOP TIMING WAVEFORM
Preliminary MEMORY
TIMING WAVEFORM BURST STOP [Latency=5, Burst Length=4](WE=VIH, MRS=VIH)
tADVH tADVS
tAS(R)
Address
tAH(R)
Don't Care Valid
Valid
tCSS(R)
tCSHP tCSLH
tBEL
tBLZ tOEL
Latency
Data
tOLZ
Undefined
(SYNCHRONOUS BURST STOP) Only rising edge clock allowed during pulse.
Revision November 2003
KBF0x0800M
Preliminary MEMORY
ASYNCHRONOUS WRITE TIMING WAVEFORM SYNCHRONOUS MODE
TIMING WAVEFORM WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, Controlled)
Address
tAS(W) tAH(W)
Valid Don't Care
tCSS(W)
tAW(2), tCW(3) tBW(4)
tWP(1)
Data
Data Valid Read Latency Read Latency Clock High-Z
Data
High-Z
TIMING WAVEFORM WRITE CYCLE(Address Latch Type)(MRS=VIH, OE=VIH, Controlled)
Address
tAS(W) tAH(W)
Valid Don't Care
tCSS(W)
tAW(2), tCW(3) tBW(4)
tWP(1)
Data
Data Valid Read Latency Read Latency Clock High-Z High-Z
Data
High-Z
(ADDRESS LATCH TYPE WRITE CYCLE) write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from address valid write. this address latch type write timing, same tAW. measured from going write. measured from going write. Clock input does have affect write operation driven before Read Latency-1 clock. Read Latency-1 clock write timing just reference going proper write operation.
Revision November 2003
KBF0x0800M
Preliminary MEMORY
ASYNCHRONOUS WRITE TIMING WAVEFORM SYNCHRONOUS MODE
TIMING WAVEFORM WRITE CYCLE(Low Type)(MRS=VIH, OE=VIH, Controlled)
Address
tCW(2)
tWR(4)
tWP(1)
tAS(3)
Data
Data Valid Read Latency Read Latency Clock High-Z
Data
High-Z
TIMING WAVEFORM WRITE CYCLE(Low Type)(MRS=VIH, OE=VIH, Controlled)
Address
tCW(2)
tWR(4)
tAS(3) tWP(1)
Data
Data Valid Read Latency Read Latency Clock High-Z
Data
High-Z
(LOW TYPE WRITE CYCLE) write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends with going high. Clock input does have affect write operation driven before Read Latency-1 clock. Read Latency-1 clock write timing just reference going proper write operation.
Revision November 2003
KBF0x0800M
Preliminary MEMORY
ASYNCHRONOUS WRITE TIMING WAVEFORM SYNCHRONOUS MODE
TIMING WAVEFORM CONTINUOUS WRITE CYCLE(Low Type)(MRS=VIH, OE=VIH, Controlled)
Address
tWHP Data Valid
Data Valid
Data
Data
High-Z
High-Z
(LOW TYPE CONTINUOUS WRITE CYCLE) write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends with going high. Clock input does have affect continuous write operation tWHP shorter than (Read Latency clock duration. tWP(min)=85ns continuous write operation over times.
Revision November 2003
KBF0x0800M
[Latency=5, Burst Length=4](MRS=VIH)
Preliminary MEMORY
SYNCH. BURST READ ASYNCH. WRITE(Address Latch Type) TIMING WAVEFORM
tADVS
tADVH tAH(R) tBEWA tAS(W)
Don't Care Valid
tAH(W)
tAS(R)
Address
Valid
tCSS(R)
tCSS(W)
tOEL
tBEL
Data
Data Valid Latency
High-Z Read Latency-1 Clock
Data
High-Z
(SYNCHRONOUS BURST READ CYCLE) Only rising edge clock allowed during pulse. next operation issued only after previous burst operation finished. (ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE controlled) Clock input does have affect write operation driven before Read Latency-1 clock. Read Latency-1 clock write timing just reference going proper write operation.
Revision November 2003
KBF0x0800M
Preliminary MEMORY
SYNCH. BURST READ ASYNCH. WRITE(Low Type) TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
tADVS
tADVH tAH(R) tBEWA
tAS(R)
Address
Valid
Don't Care
Valid Address
tCSS(R)
tOEL
tBEL
Data
Data Valid Latency
High-Z Read Latency-1 Clock
Data
High-Z
(SYNCHRONOUS BURST READ CYCLE) Only rising edge clock allowed during pulse. next operation issued only after previous burst operation finished. (LOW TYPE ASYNCHRONOUS WRITE CYCLE controlled) Clock input does have affect write operation driven before Read Latency-1 clock. Read Latency-1 clock write timing just reference going proper write operation.
Revision November 2003
KBF0x0800M
Preliminary MEMORY
ASYNCH. WRITE(Address Latch Type) SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
tADVS
tADVH tAH(R)
tAS(W)
Address
tAH(W) tAS(R)
Don't Care
Valid
Valid
Don't Care
tCSS(W)
tCSS(R)
tOEL
tBEL
Data
Data Valid Latency
Data
High-Z Read Latency-1 Clock
(SYNCHRONOUS BURST READ CYCLE) Only rising edge clock allowed during pulse. next operation issued only after previous burst operation finished. (ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE controlled) Clock input does have affect write operation driven before Read Latency-1 clock. Read Latency-1 clock write timing just reference going proper write operation.
Revision November 2003
KBF0x0800M
Preliminary MEMORY
ASYNCH. WRITE(Low Type) SYNCH. BURST READ TIMING WAVEFORM
[Latency=5, Burst Length=4](MRS=VIH)
tADVS tADHP
tADVH
tAH(R) tAS(R)
Valid Don't Care Valid
Address
tCSS(R)
tOEL
tBEL
Data
Data Valid Latency
Data
High-Z Read Latency-1 Clock
(SYNCHRONOUS BURST READ CYCLE) Only rising edge clock allowed during pulse. next operation issued only after previous burst operation finished. (LOW TYPE ASYNCHRONOUS WRITE CYCLE controlled) Clock input does have affect write operation driven before Read Latency-1 clock. Read Latency-1 clock write timing just reference going proper write operation.
Revision November 2003
KBF0x0800M
TIMING WAVEFORM MODE SETTING(OE=VIH)
Preliminary MEMORY
Address
tRWR
Register Update Complete Register Write Start Register Write Complete
(MRS SETTING TIMING) Clock input does have affect register write operation.
Revision November 2003
KBF0x0800M
Preliminary MEMORY
TIMING WAVEFORM DEEP POWER DOWN MODE ENTRY EXIT
200µs
Normal Operation MODE
0.5µs Suspend
Wake Normal Operation
Deep Power Down Mode
(DEEP POWER DOWN MODE) When driven under standby state, device gets into Deep Power Down mode after 0.5µs suspend period. this case, stanby state achieved toggling high. return normal operation, device needs Wake period. Wake sequence just same Power sequence.
Revision November 2003
KBF0x0800M
PACKAGE DIMENSION 115-Ball FINE PITCH Package (measured millimeters)
Preliminary MEMORY
INDEX MARK 0.10 8.00±0.10 (Datum 0.45±0.05 (Datum 5.20 0.32±0.05 1.30±0.10 115- 0.45±0.05 VIEW
0.20
8.00±0.10 0.80x9=7.20
0.80
0.80
0.80x13=10.40 3.60 BOTTOM VIEW
12.00±0.10
12.00±0.10
Revision November 2003
12.00±0.10
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