Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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K6F3216U6M Family
Super Power Voltage Full CMOS Static
CMOS SRAM
Revision History
Revision History
Initial draft Revised Changed ICC2 from 35mA 40mA 55ns product from 25mA 35mA 70ns product Changed ISB1 from 30µA 40µA Changed from 15µA 20µA Finalize
Draft Date
January 2002 July 2002
Remark
Preliminary Preliminary
December 2002
Final
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision December 2002
K6F3216U6M Family
FEATURES
Process Technology: Full CMOS Organization: Power Supply Voltage: 2.7~3.3V Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 55-TBGA-7.50x12.00
CMOS SRAM
GENERAL DESCRIPTION
K6F3216U6M families fabricated SAMSUNGs advanced full CMOS process technology. families support industrial operating temperature ranges have chip scale package user flexibility system design. families also support data retention voltage battery back-up operation with data retention current.
Super Power Voltage Full CMOS Static
PRODUCT FAMILY
Power Dissipation Product Family K6F3216U6M-F Operating Temperature Industrial(-40~85°C) Range 2.7~3.3V Speed 551)/70ns Standby (ISB1, Max.) 40µA Operating (ICC1, Max) Type 55-TBGA-7.50x12.00
parameter measured with 30pF test load.
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
Addresses
select
Memory Cell Array
I/O9
I/O1
I/O10
I/O11
I/O2
I/O3
I/O12
I/O4
I/O1~I/O8
Data cont Data cont Data cont
Circuit Column select
I/O13
I/O5
I/O9~I/O16
I/O15
I/O14
I/O6
I/O7
I/O16
I/O8
Column Addresses
Control Logic
55-TBGA: View (Ball Down)
Name CS1, A0~A20
Function Chip Select Inputs Output Enable Input Write Enable Input Address Inputs
Name
Function Power Ground Upper Byte(I/O 9~16) Lower Byte(I/O 1~8) Connection
1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision December 2002
K6F3216U6M Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F3216U6M-EF55 K6F3216U6M-EF70 Function 55-TBGA, 55ns, 3.0V 55-TBGA, 70ns, 3.0V
CMOS SRAM
FUNCTIONAL DESCRIPTION
I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Standby Active Active Active Active Active Active Active Active
means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT TSTG Ratings -0.2 VCC+0.3V(Max. 3.6V) -0.2 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended period affect reliability.
Revision December 2002
K6F3216U6M Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol -0.3
CMOS SRAM
Vcc+0.3
Unit
Note: A=-40 85°C, otherwise specified Overshoot: VCC+2.0V case pulse width 20ns. Undershoot: -2.0V case pulse width 20ns. Overshoot Undershoot sampled, 100% tested.
CAPACITANCE (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current
Symbol
Test Conditions VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL LB=UB=VIH, VIO=Vss Cycle time=1µs, 100%duty, IIO=0mA, 10.2V, LB0.2V or/and UB0.2V, CS2Vcc-0.2V, VIN0.2V VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL 2.1mA -1.0mA Other input =0~Vcc CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0VCS20.2V(CS2 controlled) 70ns 55ns
Unit
ICC1
Average operating current ICC2 Output voltage Output high voltage Standby Current (CMOS) ISB1
Typical values measured VCC=3.0V, TA=25°C 100% tested.
Revision December 2002
K6F3216U6M Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Input/Output Reference)
Input pulse level: 2.2V Input rising falling time: Input output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL
CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance =3070, =3150 V=2.8V
CHARACTERISTICS Vcc=2.7~3.3V, Industrial product:TA=-40 85°C
Speed Parameter List Symbol Read cycle time Address access time Chip select output Output enable valid output valid data output Read Chip select low-Z output enable low-Z output Output enable low-Z output Chip disable high-Z output disable high-Z output Output disable high-Z output Output hold from address change Write cycle time Chip select write Address set-up time Address valid write Valid Write Write Write pulse width Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z tCO1, tCO2 tLZ1, tLZ2 tBLZ tOLZ tHZ1, tHZ2 tBHZ tOHZ tCW1, tCW2 tWHZ 55ns 70ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V VIN0V
Unit
Vcc=1.5V, CS1Vcc-0.2V VIN0V
data retention waveform
Vcc-0.2V, 2Vcc-0.2V(CS1 controlled) 0CS2 0.2V(CS2 controlled)
Revision December 2002
K6F3216U6M Family
TIMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1)
Address Data Previous Data Valid
CMOS SRAM
(Address Controlled, CS1=OE=VIL CS2=WE=VIH, or/and LB=VIL)
Data Valid
TIMING WAVEFORM READ CYCLE(2)
(WE=VIH)
Address
tBHZ tOLZ tBLZ Data Valid tOHZ
Data
High-Z
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision December 2002
K6F3216U6M Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWR(4)
CMOS SRAM
tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid High-Z
TIMING WAVEFORM WRITE CYCLE(2) (CS1 Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision December 2002
K6F3216U6M Family
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends with going high.
DATA RETENTION WAVE FORM
controlled
2.7V tSDR Data Retention Mode tRDR
2.2V 1VCC 0.2V
controlled
2.7V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision December 2002
K6F3216U6M Family
PACKAGE DIMENSION
BALL TAPE BALL GRID ARRAY(0.75mm ball pitch)
View Bottom View
CMOS SRAM
Unit: millimeters
Detail 0.35/Typ. Notes. Bump counts: 55(12 column) Bump pitch: (x,y)=(0.75 0.75)(typ.) tolerence ±0.050 unless otherwise specified. Typ: Typical coplanarity: 0.08(Max)
C1/2
Side View
7.40 11.90 0.40 0.80 0.30
0.75 7.50 5.25 12.00 8.25 0.45 0.90 0.55 0.35
7.60 12.10 0.50 1.00 0.40 0.08
0.55/Typ.
Revision December 2002

Super Power Voltage Full CMOS Static CMOS SRAM Revision Hist

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