Super Power Voltage Full CMOS Static Preliminary CMOS SRAM R
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K6F1616U6C Family
Super Power Voltage Full CMOS Static
Preliminary CMOS SRAM
Revision History
Revision History
Initial draft
Draft Date
November 2003
Remark
Preliminary
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision November 2003
K6F1616U6C Family
FEATURES
Process Technology: Full CMOS Organization: Power Supply Voltage: 2.7~3.3V Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 48-FBGA 6.00x7.00
Preliminary CMOS SRAM
GENERAL DESCRIPTION
K6F1616U6C families fabricated SAMSUNGs advanced full CMOS process technology. families support industrial operating temperature ranges. families also support data retention voltage battery back-up operation with data retention current.
Super Power Voltage Full CMOS Static
PRODUCT FAMILY
Power Dissipation Product Family K6F1616U6C-F Operating Temperature Industrial(-40~85°C) Range 2.7~3.3V Speed 551)/70ns Standby (ISB1, Typ.) 5µA2) Operating (ICC1, Max) Type 48-FBGA 6.00x7.00
parameter measured with 30pF test load. Typical value measured VCC=3.0V, TA=25°C 100% tested.
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
I/O9
I/O1
I/O10
I/O11
I/O2
I/O3
Addresses
select
I/O12
I/O4
Memory Cell Array
I/O13
I/O5
Data cont Data cont Data cont Circuit Column select
I/O15
I/O14
I/O6
I/O7
I/O1~I/O8
I/O9~I/O16
I/O16
I/O8
Column Addresses
48-FBGA: View (Ball Down)
Name
Function
Name
Function Power Ground Upper Byte(I/O9~16) Lower Byte(I/O1~8) Connection
CS1, Chip Select Inputs A0~A19 Output Enable Input Write Enable Input Address Inputs
Control Logic
I/O1~I/O16 Data Inputs/Outputs
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
Revision November 2003
K6F1616U6C Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F1616U6C-FF55 K6F1616U6C-FF70 Function 48-FBGA, 55ns, 3.0V 48-FBGA, 70ns, 3.0V
Preliminary CMOS SRAM
FUNCTIONAL DESCRIPTION
I/O1~8 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z
I/O9~16 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z
Mode Deselected Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write
Power Standby Standby Standby Active Active Active Active Active Active Active Active
means dont care. (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN,VOUT TSTG Ratings -0.2 VCC+0.3V(Max. 3.6V) -0.2 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision November 2003
K6F1616U6C Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage Symbol -0.23)
Preliminary CMOS SRAM
Vcc+0.22) Unit
Note: TA=-40 85°C, otherwise specified Overshoot: VCC+2.0V case pulse width 20ns. Undershoot: -2.0V case pulse width 20ns. Overshoot Undershoot sampled, 100% tested.
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current
Symbol
Test Conditions VIN=Vss CS1=VIH CS2=VIL OE=VIH WE=VIL LB=UB=VIH, VIO=Vss Cycle time=1µs, 100%duty, IIO=0mA, CS10.2V, LB0.2V or/and UB0.2V, CS2Vcc-0.2V, VIN0.2V VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, LB=VIL or/and UB=VIL, VIN=VIL 2.1mA -1.0mA Other input =0~Vcc CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0VCS20.2V(CS2 controlled) 70ns 55ns
Typ1)
Unit
ICC1
Average operating current ICC2 Output voltage Output high voltage Standby Current (CMOS) ISB1
Typical values measured VCC=3.0V, TA=25°C 100% tested.
Revision November 2003
K6F1616U6C Family
OPERATING CONDITIONS
TEST CONDITIONS(Test Load Input/Output Reference)
Input pulse level: 0.2V Vcc-0.2V Input rising falling time: Input output reference voltage:1.5V Output load(see right): CL=100pF+1TTL CL=30pF+1TTL
Preliminary CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance R1=3070, R2=3150 V=2.8V
CHARACTERISTICS (Vcc=2.7~3.3V, TA=-40 85°C)
Speed Bins Parameter List Symbol Read cycle time Address access time Chip select output Output enable valid output valid data output Read Chip select low-Z output Output enable low-Z output enable low-Z output Output hold from address change Chip disable high-Z output disable high-Z output disable high-Z output Write cycle time Chip select write Address set-up time Address valid write Write pulse width Write Write recovery time Write output high-Z Data write time overlap Data hold from write time write output low-Z valid write tOLZ tBLZ tOHZ tBHZ tWHZ 55ns 70ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V VIN0V
1.02)
Unit
Vcc=1.5V, CS1Vcc-0.2V1), VIN0V data retention waveform
CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0CS20.2V(CS2 controlled) Typical value measured TA=25°C 100% tested.
Revision November 2003
K6F1616U6C Family
TIMING DIAGRAMS
Preliminary CMOS SRAM
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH, or/and LB=VIL)
Address Data Previous Data Valid Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address
tBHZ tOLZ tBLZ Data
High-Z
tOHZ Data Valid
NOTES (READ CYCLE) tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision November 2003
K6F1616U6C Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tWR(4)
Preliminary CMOS SRAM
tWP(1) tAS(3) Data High-Z tWHZ Data Data Undefined Data Valid High-Z
TIMING WAVEFORM WRITE CYCLE(2) (CS1 Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision November 2003
K6F1616U6C Family
TIMING WAVEFORM WRITE CYCLE(3) (UB, Controlled)
Address tCW(2) tAS(3) tWP(1) Data Data Valid tWR(4)
Preliminary CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap(tWP) write begins when goes goes with asserting single byte operation simultaneously asserting double byte operation. write ends earliest transition when goes high goes high. measured from beginning write write. measured from going write. measured from address valid beginning write. measured from write address change. applied case write ends with going high.
DATA RETENTION WAVEFORM
controlled
2.7V tSDR Data Retention Mode tRDR
2.2V CS1VCC 0.2V
controlled
2.7V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision November 2003
K6F1616U6C Family
PACKAGE DIMENSION
BALL FINE PITCH BGA(0.75mm ball pitch)
View Bottom View
Preliminary CMOS SRAM
Unit: millimeters
C1/2 Detail 0.32/Typ. 0.58/Typ. Notes. Bump counts: 48(8 column) Bump pitch: (x,y)=(0.75 0.75)(typ.) tolerence ±0.050 unless specified beside figure. Typ: Typical coplanarity: 0.10(Max)
Side View
5.90 6.90 0.40 0.80 0.27
0.75 6.00 3.75 7.00 5.25 0.45 0.90 0.58 0.32
6.10 7.10 0.50 1.00 0.37 0.10
Revision November 2003
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