Preliminary CMOS SRAM 512K Super Power Voltage Full CMOS Static

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Preliminary CMOS SRAM 512K Super Power Voltage Full CMOS Static

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K6F4008U2G Family
Preliminary CMOS SRAM
512K Super Power Voltage Full CMOS Static
Revision History
Revision History
Initial Draft
Draft Date
June 2003
Remark
Preliminary
attached datasheets provided SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve right change specifications products. SAMSUNG Electronics will answer your questions about device. have questions, please contact SAMSUNG branch offices.
Revision June 2003
K6F4008U2G Family
FEATURES
Preliminary CMOS SRAM
GENERAL DESCRIPTION
K6F4008U2G families fabricated SAMSUNGs advanced full CMOS process technology. families support industrial temperature range Chip Scale Package user flexibility system design. families also supports data retention voltage battery back-up operation with data retention current.
512K Super Power Voltage Full CMOS Static
Process Technology: Full CMOS Organization: 512K Power Supply Voltage: 2.7~3.3V Data Retention Voltage: 1.5V(Min) Three State Outputs Package Type: 48(36)-TBGA-6.00x7.00
PRODUCT FAMILY
Power Dissipation Product Family Operating Temperature Range Speed Standby (ISB1, Typ.) 3µA2) Operating (ICC1, Max) Type
K6F4008U2G-F
Industrial(-40~85°C)
2.7~3.3V
551)/70ns
48(36)-TBGA-6.00x7.00
parameter measured with 30pF test load. Typical values VCC=3.0V, TA=25°C 100% tested.
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
gen. Precharge circuit.
I/O5 I/O6
I/O1 I/O2
select
Address
Memory Cell Array
48(36)-TBGA
I/O7 I/O8
I/O1
I/O3 I/O4
I/O8
Data cont
Circuit Column select
Data cont Column Address
Name
Function
Name
Function
CS1, Chip Select Inputs A0~A18 Output Enable Input Write Enable Input Address Inputs
I/O1~I/O8 Data Inputs/Outputs Power Ground
Control logic
SAMSUNG ELECTRONICS CO., LTD. reserves right change products specifications without notice.
-2Revision June 2003
K6F4008U2G Family
PRODUCT LIST
Industrial Temperature Products(-40~85°C) Part Name K6F4008U2G-EF55 K6F4008U2G-EF70 Function
Preliminary CMOS SRAM
48(36)-TBGA, 55ns, 3.0V 48(36)-TBGA, 70ns, 3.0V
FUNCTIONAL DESCRIPTION
High-Z High-Z High-Z Dout
Mode Deselected Deselected Output Disabled Read Write
Power Standby Standby Active Active Active
means dont care (Must high state)
ABSOLUTE MAXIMUM RATINGS1)
Item Voltage relative Voltage supply relative Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT TSTG Ratings -0.5 VCC+0.3V(Max. 3.6V) -0.3 Unit
Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. Functional operation should restricted recommended operating condition. Exposure absolute maximum rating conditions extended periods affect reliability.
Revision June 2003
K6F4008U2G Family
RECOMMENDED OPERATING CONDITIONS1)
Item Supply voltage Ground Input high voltage Input voltage
Note: TA=-40 85°C, otherwise specified. Overshoot: Vcc+2.0V case pulse width 20ns. Undershoot: -2.0V case pulse width 20ns. Overshoot undershoot sampled, 100% tested.
Preliminary CMOS SRAM
Symbol
-0.3
Vcc+0.3
Unit
CAPACITANCE1) (f=1MHz, TA=25°C)
Item Input capacitance Input/Output capacitance
Capacitance sampled, 100% tested.
Symbol
Test Condition VIN=0V VIO=0V
Unit
OPERATING CHARACTERISTICS
Item Input leakage current Output leakage current
Symbol
Test Conditions VIN=Vss CS1=VIH, CS2=VIL OE=VIH WE=VIL, VIO=Vss Cycle time=1µs, 100%duty, IIO=0mA, CS10.2V, CS2Vcc-0.2V, VIN0.2V VINVCC-0.2V Cycle time=Min, IIO=0mA, 100% duty, CS1=VIL, CS2=VIH, VIN=VIL 2.1mA -1.0mA CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0VCS20.2V(CS2 controlled), Other inputs=0~Vcc 70ns 55ns
Typ1)
Unit
ICC1
Average operating current ICC2 Output voltage Output high voltage Standby Current (CMOS) ISB1
Typical value measured VCC=3.0V, TA=25°C, 100% tested.
Revision June 2003
K6F4008U2G Family
OPERATING CONDITIONS
TEST CONDITIONS (Test Load Test Input/Output Reference)
Input pulse level: 2.2V Input rising falling time: Input output reference voltage: 1.5V Output load (See right): 100pF+1TTL CL=30pF+1TTL
Preliminary CMOS SRAM
VTM3) R12)
CL1)
R22)
Including scope capacitance R1=3070, R2=3150 V=2.8V
CHARACTERISTICS(Vcc=2.7~3.3V, Industrial product:TA=-40 85°C)
Speed Parameter List Symbol Read Cycle Time Address Access Time Chip Select Output Output Enable Valid Output Read Chip Select Low-Z Output Output Enable Low-Z Output Chip Disable High-Z Output Output Disable High-Z Output Output Hold from Address Change Write Cycle Time Chip Select Write Address Set-up Time Address Valid Write Write Write Pulse Width Write Recovery Time Write Output High-Z Data Write Time Overlap Data Hold from Write Time Write Output Low-Z tOLZ tOHZ tWHZ 55ns 70ns Units
DATA RETENTION CHARACTERISTICS
Item data retention Data retention current Data retention set-up time Recovery time Symbol tSDR tRDR Test Condition CS1Vcc-0.2V1) Vcc=1.5V, CS1Vcc-0.2V VIN0V
Unit
data retention waveform
CS1Vcc-0.2V, CS2Vcc-0.2V(CS1 controlled) 0CS20.2V(CS2 controlled).
Revision June 2003
K6F4008U2G Family
TIMING DIAGRAMS
TIMING WAVEFORM READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)
Address Data Previous Data Valid
Preliminary CMOS SRAM
Data Valid
TIMING WAVEFORM READ CYCLE(2) (WE=VIH)
Address tCO1 tHZ(1,2) tCO2
tOLZ Data Valid tOHZ
Data
NOTES (READ CYCLE)
High-Z
tOHZ defined time which outputs achieve open circuit conditions referenced output voltage levels. given temperature voltage condition, tHZ(Max.) less than tLZ(Min.) both given device from device device interconnection.
Revision June 2003
K6F4008U2G Family
TIMING WAVEFORM WRITE CYCLE(1) Controlled)
Address tCW(2) tCW(2) tWP(1) tAS(3) Data tWHZ Data Data Undefined Data Valid tWR(4)
Preliminary CMOS SRAM
TIMING WAVEFORM WRITE CYCLE(2) (CS1 Controlled)
Address tAS(3) tWP(1) Data Data Valid tCW(2) tWR(4)
Data
High-Z
High-Z
Revision June 2003
K6F4008U2G Family
TIMING WAVEFORM WRITE CYCLE(3) (CS2 Controlled)
Address tAS(3) tCW(2) tWP(1) Data Data Valid tCW(2) tWR(4)
Preliminary CMOS SRAM
Data
NOTES (WRITE CYCLE)
High-Z
High-Z
write occurs during overlap CS1, high write begins latest transition among goes low, going high going low: write earliest transition among going high, going going high, measured from begining write write. measured from going going high write. measured from address valid beginning write. measured from write address change.
DATA RETENTION WAVE FORM
controlled
2.7V tSDR Data Retention Mode tRDR
2.2V CS1VCC 0.2V
controlled
2.7V tSDR
Data Retention Mode
tRDR
0.4V CS20.2V
Revision June 2003
K6F4008U2G Family
PACKAGE DIMENSIONS
48(36) TAPE BALL GRID ARRAY(0.75mm ball pitch)
View Bottom View
Preliminary CMOS SRAM
Units: millimeters
C1/2 Detail 0.35/Typ. 0.55/Typ. Notes. Bump counts: 48(8 column) Bump pitch: (x,y)=(0.75 0.75)(typ.) tolerence +/-0.050 unless otherwise specified. Typ: Typical coplanarity: 0.08(Max)
Side View
5.90 6.90 0.40 0.80 0.30
0.75 6.00 3.75 7.00 5.25 0.45 0.90 0.55 0.35
6.10 7.10 0.50 1.00 0.40 0.08
Revision June 2003

Preliminary CMOS SRAM 512K Super Power Voltage Full CMOS Static

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